1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "core_types.h" 28 #include "dc_dmub_srv.h" 29 #include "panel_cntl.h" 30 #include "dce_panel_cntl.h" 31 #include "atom.h" 32 33 #define TO_DCE_PANEL_CNTL(panel_cntl)\ 34 container_of(panel_cntl, struct dce_panel_cntl, base) 35 36 #define CTX \ 37 dce_panel_cntl->base.ctx 38 39 #define DC_LOGGER \ 40 dce_panel_cntl->base.ctx->logger 41 42 #define REG(reg)\ 43 dce_panel_cntl->regs->reg 44 45 #undef FN 46 #define FN(reg_name, field_name) \ 47 dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name 48 49 static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_panel_cntl *dce_panel_cntl) 50 { 51 uint64_t current_backlight; 52 uint32_t round_result; 53 uint32_t pwm_period_cntl, bl_period, bl_int_count; 54 uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en; 55 uint32_t bl_period_mask, bl_pwm_mask; 56 57 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL); 58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); 59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); 60 61 bl_pwm_cntl = REG_READ(BL_PWM_CNTL); 62 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); 63 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); 64 65 if (bl_int_count == 0) 66 bl_int_count = 16; 67 68 bl_period_mask = (1 << bl_int_count) - 1; 69 bl_period &= bl_period_mask; 70 71 bl_pwm_mask = bl_period_mask << (16 - bl_int_count); 72 73 if (fractional_duty_cycle_en == 0) 74 bl_pwm &= bl_pwm_mask; 75 else 76 bl_pwm &= 0xFFFF; 77 78 current_backlight = bl_pwm << (1 + bl_int_count); 79 80 if (bl_period == 0) 81 bl_period = 0xFFFF; 82 83 current_backlight = div_u64(current_backlight, bl_period); 84 current_backlight = (current_backlight + 1) >> 1; 85 86 current_backlight = (uint64_t)(current_backlight) * bl_period; 87 88 round_result = (uint32_t)(current_backlight & 0xFFFFFFFF); 89 90 round_result = (round_result >> (bl_int_count-1)) & 1; 91 92 current_backlight >>= bl_int_count; 93 current_backlight += round_result; 94 95 return (uint32_t)(current_backlight); 96 } 97 98 uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl) 99 { 100 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); 101 uint32_t value; 102 uint32_t current_backlight; 103 104 /* It must not be 0, so we have to restore them 105 * Bios bug w/a - period resets to zero, 106 * restoring to cache values which is always correct 107 */ 108 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); 109 110 if (value == 0 || value == 1) { 111 if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) { 112 REG_WRITE(BL_PWM_CNTL, 113 panel_cntl->stored_backlight_registers.BL_PWM_CNTL); 114 REG_WRITE(BL_PWM_CNTL2, 115 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2); 116 REG_WRITE(BL_PWM_PERIOD_CNTL, 117 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL); 118 REG_UPDATE(PWRSEQ_REF_DIV, 119 BL_PWM_REF_DIV, 120 panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); 121 } else { 122 /* TODO: Note: This should not really happen since VBIOS 123 * should have initialized PWM registers on boot. 124 */ 125 REG_WRITE(BL_PWM_CNTL, 0xC000FA00); 126 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); 127 } 128 } else { 129 panel_cntl->stored_backlight_registers.BL_PWM_CNTL = 130 REG_READ(BL_PWM_CNTL); 131 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = 132 REG_READ(BL_PWM_CNTL2); 133 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 134 REG_READ(BL_PWM_PERIOD_CNTL); 135 136 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, 137 &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); 138 } 139 140 // Have driver take backlight control 141 // TakeBacklightControl(true) 142 value = REG_READ(BIOS_SCRATCH_2); 143 value |= ATOM_S2_VRI_BRIGHT_ENABLE; 144 REG_WRITE(BIOS_SCRATCH_2, value); 145 146 // Enable the backlight output 147 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); 148 149 // Unlock group 2 backlight registers 150 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, 151 BL_PWM_GRP1_REG_LOCK, 0); 152 153 current_backlight = calculate_16_bit_backlight_from_pwm(dce_panel_cntl); 154 155 return current_backlight; 156 } 157 158 bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl) 159 { 160 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); 161 uint32_t value; 162 163 REG_GET(PWRSEQ_CNTL, LVTMA_BLON, &value); 164 165 return value; 166 } 167 168 bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl) 169 { 170 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); 171 uint32_t pwr_seq_state, dig_on, dig_on_ovrd; 172 173 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); 174 175 REG_GET_2(PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd); 176 177 return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1); 178 } 179 180 void dce_store_backlight_level(struct panel_cntl *panel_cntl) 181 { 182 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); 183 184 panel_cntl->stored_backlight_registers.BL_PWM_CNTL = 185 REG_READ(BL_PWM_CNTL); 186 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = 187 REG_READ(BL_PWM_CNTL2); 188 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 189 REG_READ(BL_PWM_PERIOD_CNTL); 190 191 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, 192 &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); 193 } 194 195 void dce_driver_set_backlight(struct panel_cntl *panel_cntl, 196 uint32_t backlight_pwm_u16_16) 197 { 198 uint32_t backlight_16bit; 199 uint32_t masked_pwm_period; 200 uint8_t bit_count; 201 uint64_t active_duty_cycle; 202 uint32_t pwm_period_bitcnt; 203 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); 204 205 /* 206 * 1. Find 16 bit backlight active duty cycle, where 0 <= backlight 207 * active duty cycle <= backlight period 208 */ 209 210 /* 1.1 Apply bitmask for backlight period value based on value of BITCNT 211 */ 212 REG_GET_2(BL_PWM_PERIOD_CNTL, 213 BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt, 214 BL_PWM_PERIOD, &masked_pwm_period); 215 216 if (pwm_period_bitcnt == 0) 217 bit_count = 16; 218 else 219 bit_count = pwm_period_bitcnt; 220 221 /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ 222 masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1); 223 224 /* 1.2 Calculate integer active duty cycle required upper 16 bits 225 * contain integer component, lower 16 bits contain fractional component 226 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24 227 */ 228 active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period; 229 230 /* 1.3 Calculate 16 bit active duty cycle from integer and fractional 231 * components shift by bitCount then mask 16 bits and add rounding bit 232 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 233 */ 234 backlight_16bit = active_duty_cycle >> bit_count; 235 backlight_16bit &= 0xFFFF; 236 backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; 237 238 /* 239 * 2. Program register with updated value 240 */ 241 242 /* 2.1 Lock group 2 backlight registers */ 243 244 REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK, 245 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1, 246 BL_PWM_GRP1_REG_LOCK, 1); 247 248 // 2.2 Write new active duty cycle 249 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); 250 251 /* 2.3 Unlock group 2 backlight registers */ 252 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, 253 BL_PWM_GRP1_REG_LOCK, 0); 254 255 /* 3 Wait for pending bit to be cleared */ 256 REG_WAIT(BL_PWM_GRP1_REG_LOCK, 257 BL_PWM_GRP1_REG_UPDATE_PENDING, 0, 258 1, 10000); 259 } 260 261 static void dce_panel_cntl_destroy(struct panel_cntl **panel_cntl) 262 { 263 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(*panel_cntl); 264 265 kfree(dce_panel_cntl); 266 *panel_cntl = NULL; 267 } 268 269 static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = { 270 .destroy = dce_panel_cntl_destroy, 271 .hw_init = dce_panel_cntl_hw_init, 272 .is_panel_backlight_on = dce_is_panel_backlight_on, 273 .is_panel_powered_on = dce_is_panel_powered_on, 274 .store_backlight_level = dce_store_backlight_level, 275 .driver_set_backlight = dce_driver_set_backlight, 276 }; 277 278 void dce_panel_cntl_construct( 279 struct dce_panel_cntl *dce_panel_cntl, 280 const struct panel_cntl_init_data *init_data, 281 const struct dce_panel_cntl_registers *regs, 282 const struct dce_panel_cntl_shift *shift, 283 const struct dce_panel_cntl_mask *mask) 284 { 285 struct panel_cntl *base = &dce_panel_cntl->base; 286 287 base->stored_backlight_registers.BL_PWM_CNTL = 0; 288 base->stored_backlight_registers.BL_PWM_CNTL2 = 0; 289 base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0; 290 base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0; 291 292 dce_panel_cntl->regs = regs; 293 dce_panel_cntl->shift = shift; 294 dce_panel_cntl->mask = mask; 295 296 dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs; 297 dce_panel_cntl->base.ctx = init_data->ctx; 298 dce_panel_cntl->base.inst = init_data->inst; 299 } 300