1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_OPP_DCE_H__ 26 #define __DC_OPP_DCE_H__ 27 28 #include "dc_types.h" 29 #include "opp.h" 30 #include "core_types.h" 31 32 #define FROM_DCE11_OPP(opp)\ 33 container_of(opp, struct dce110_opp, base) 34 35 enum dce110_opp_reg_type { 36 DCE110_OPP_REG_DCP = 0, 37 DCE110_OPP_REG_DCFE, 38 DCE110_OPP_REG_FMT, 39 40 DCE110_OPP_REG_MAX 41 }; 42 43 #define OPP_COMMON_REG_LIST_BASE(id) \ 44 SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ 45 SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ 46 SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ 47 SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ 48 SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ 49 SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ 50 SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ 51 SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ 52 SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ 53 SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ 54 SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ 55 SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ 56 SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ 57 SRI(REGAMMA_LUT_INDEX, DCP, id), \ 58 SRI(REGAMMA_LUT_DATA, DCP, id), \ 59 SRI(REGAMMA_CONTROL, DCP, id), \ 60 SRI(OUTPUT_CSC_C11_C12, DCP, id), \ 61 SRI(OUTPUT_CSC_C13_C14, DCP, id), \ 62 SRI(OUTPUT_CSC_C21_C22, DCP, id), \ 63 SRI(OUTPUT_CSC_C23_C24, DCP, id), \ 64 SRI(OUTPUT_CSC_C31_C32, DCP, id), \ 65 SRI(OUTPUT_CSC_C33_C34, DCP, id), \ 66 SRI(OUTPUT_CSC_CONTROL, DCP, id), \ 67 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 68 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 69 SRI(FMT_CONTROL, FMT, id), \ 70 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 71 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 72 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 73 SRI(FMT_CLAMP_CNTL, FMT, id), \ 74 SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \ 75 SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \ 76 SRI(FMT_CLAMP_COMPONENT_B, FMT, id) 77 78 #define OPP_DCE_80_REG_LIST(id) \ 79 OPP_COMMON_REG_LIST_BASE(id), \ 80 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \ 81 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 82 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 83 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 84 85 #define OPP_DCE_100_REG_LIST(id) \ 86 OPP_COMMON_REG_LIST_BASE(id), \ 87 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \ 88 SRI(DCFE_MEM_PWR_STATUS, CRTC, id), \ 89 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 90 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 91 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 92 93 #define OPP_DCE_110_REG_LIST(id) \ 94 OPP_COMMON_REG_LIST_BASE(id), \ 95 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ 96 SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ 97 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 98 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 99 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 100 101 #define OPP_DCE_112_REG_LIST(id) \ 102 OPP_COMMON_REG_LIST_BASE(id), \ 103 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ 104 SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ 105 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 106 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 107 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ 108 SRI(CONTROL, FMT_MEMORY, id) 109 110 #define OPP_SF(reg_name, field_name, post_fix)\ 111 .field_name = reg_name ## __ ## field_name ## post_fix 112 113 #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 114 OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ 115 OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ 116 OPP_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ 117 OPP_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ 118 OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ 119 OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ 120 OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 121 OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 122 OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 123 OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 124 OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ 125 OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ 126 OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ 127 OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ 128 OPP_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ 129 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 130 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 131 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 132 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 133 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 134 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 135 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 136 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 137 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 138 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 139 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 140 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 141 OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 142 OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 143 OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 144 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 145 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 146 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 147 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 148 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 149 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 150 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 151 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 152 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 153 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 154 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 155 OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 156 OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 157 OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 158 OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 159 OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 160 OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 161 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 162 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 163 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh) 164 165 #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ 166 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 167 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 168 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 169 OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ 170 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 171 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) 172 173 #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ 174 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 175 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 176 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 177 OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ 178 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 179 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) 180 181 #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 182 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 183 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 184 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 185 OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ 186 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 187 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 188 OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 189 OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 190 OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ 191 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 192 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) 193 194 #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ 195 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 196 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ 197 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ 198 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) 199 200 #define OPP_REG_FIELD_LIST(type) \ 201 type DCP_REGAMMA_MEM_PWR_DIS; \ 202 type DCP_LUT_MEM_PWR_DIS; \ 203 type REGAMMA_LUT_LIGHT_SLEEP_DIS; \ 204 type DCP_LUT_LIGHT_SLEEP_DIS; \ 205 type REGAMMA_CNTLA_EXP_REGION_START; \ 206 type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \ 207 type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \ 208 type REGAMMA_CNTLA_EXP_REGION_END; \ 209 type REGAMMA_CNTLA_EXP_REGION_END_BASE; \ 210 type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \ 211 type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \ 212 type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \ 213 type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \ 214 type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \ 215 type DCP_REGAMMA_MEM_PWR_STATE; \ 216 type REGAMMA_LUT_MEM_PWR_STATE; \ 217 type REGAMMA_LUT_WRITE_EN_MASK; \ 218 type GRPH_REGAMMA_MODE; \ 219 type OUTPUT_CSC_C11; \ 220 type OUTPUT_CSC_C12; \ 221 type OUTPUT_CSC_GRPH_MODE; \ 222 type FMT_DYNAMIC_EXP_EN; \ 223 type FMT_DYNAMIC_EXP_MODE; \ 224 type FMT_TRUNCATE_EN; \ 225 type FMT_TRUNCATE_DEPTH; \ 226 type FMT_TRUNCATE_MODE; \ 227 type FMT_SPATIAL_DITHER_EN; \ 228 type FMT_SPATIAL_DITHER_DEPTH; \ 229 type FMT_SPATIAL_DITHER_MODE; \ 230 type FMT_TEMPORAL_DITHER_EN; \ 231 type FMT_TEMPORAL_DITHER_RESET; \ 232 type FMT_TEMPORAL_DITHER_OFFSET; \ 233 type FMT_TEMPORAL_DITHER_DEPTH; \ 234 type FMT_TEMPORAL_LEVEL; \ 235 type FMT_25FRC_SEL; \ 236 type FMT_50FRC_SEL; \ 237 type FMT_75FRC_SEL; \ 238 type FMT_HIGHPASS_RANDOM_ENABLE; \ 239 type FMT_FRAME_RANDOM_ENABLE; \ 240 type FMT_RGB_RANDOM_ENABLE; \ 241 type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 242 type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 243 type FMT_RAND_R_SEED; \ 244 type FMT_RAND_G_SEED; \ 245 type FMT_RAND_B_SEED; \ 246 type FMT420_MEM0_SOURCE_SEL; \ 247 type FMT420_MEM0_PWR_FORCE; \ 248 type FMT_SRC_SELECT; \ 249 type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \ 250 type FMT_420_PIXEL_PHASE_LOCKED; \ 251 type FMT_CLAMP_DATA_EN; \ 252 type FMT_CLAMP_COLOR_FORMAT; \ 253 type FMT_CLAMP_LOWER_R; \ 254 type FMT_CLAMP_UPPER_R; \ 255 type FMT_CLAMP_LOWER_G; \ 256 type FMT_CLAMP_UPPER_G; \ 257 type FMT_CLAMP_LOWER_B; \ 258 type FMT_CLAMP_UPPER_B; \ 259 type FMT_PIXEL_ENCODING; \ 260 type FMT_SUBSAMPLING_ORDER; \ 261 type FMT_SUBSAMPLING_MODE; \ 262 type FMT_CBCR_BIT_REDUCTION_BYPASS;\ 263 264 struct dce_opp_shift { 265 OPP_REG_FIELD_LIST(uint8_t) 266 }; 267 268 struct dce_opp_mask { 269 OPP_REG_FIELD_LIST(uint32_t) 270 }; 271 272 struct dce_opp_registers { 273 uint32_t DCFE_MEM_PWR_CTRL; 274 uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; 275 uint32_t REGAMMA_CNTLA_START_CNTL; 276 uint32_t REGAMMA_CNTLA_SLOPE_CNTL; 277 uint32_t REGAMMA_CNTLA_END_CNTL1; 278 uint32_t REGAMMA_CNTLA_END_CNTL2; 279 uint32_t REGAMMA_CNTLA_REGION_0_1; 280 uint32_t REGAMMA_CNTLA_REGION_2_3; 281 uint32_t REGAMMA_CNTLA_REGION_4_5; 282 uint32_t REGAMMA_CNTLA_REGION_6_7; 283 uint32_t REGAMMA_CNTLA_REGION_8_9; 284 uint32_t REGAMMA_CNTLA_REGION_10_11; 285 uint32_t REGAMMA_CNTLA_REGION_12_13; 286 uint32_t REGAMMA_CNTLA_REGION_14_15; 287 uint32_t REGAMMA_LUT_WRITE_EN_MASK; 288 uint32_t REGAMMA_LUT_INDEX; 289 uint32_t DCFE_MEM_PWR_STATUS; 290 uint32_t REGAMMA_LUT_DATA; 291 uint32_t REGAMMA_CONTROL; 292 uint32_t OUTPUT_CSC_C11_C12; 293 uint32_t OUTPUT_CSC_C13_C14; 294 uint32_t OUTPUT_CSC_C21_C22; 295 uint32_t OUTPUT_CSC_C23_C24; 296 uint32_t OUTPUT_CSC_C31_C32; 297 uint32_t OUTPUT_CSC_C33_C34; 298 uint32_t OUTPUT_CSC_CONTROL; 299 uint32_t FMT_DYNAMIC_EXP_CNTL; 300 uint32_t FMT_BIT_DEPTH_CONTROL; 301 uint32_t FMT_CONTROL; 302 uint32_t FMT_DITHER_RAND_R_SEED; 303 uint32_t FMT_DITHER_RAND_G_SEED; 304 uint32_t FMT_DITHER_RAND_B_SEED; 305 uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL; 306 uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX; 307 uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX; 308 uint32_t CONTROL; 309 uint32_t FMT_CLAMP_CNTL; 310 uint32_t FMT_CLAMP_COMPONENT_R; 311 uint32_t FMT_CLAMP_COMPONENT_G; 312 uint32_t FMT_CLAMP_COMPONENT_B; 313 }; 314 315 struct dce110_regamma { 316 struct gamma_curve arr_curve_points[16]; 317 struct curve_points arr_points[3]; 318 uint32_t hw_points_num; 319 struct hw_x_point *coordinates_x; 320 struct pwl_result_data *rgb_resulted; 321 322 /* re-gamma curve */ 323 struct pwl_float_data_ex *rgb_regamma; 324 /* coeff used to map user evenly distributed points 325 * to our hardware points (predefined) for gamma 256 */ 326 struct pixel_gamma_point *coeff128; 327 struct pixel_gamma_point *coeff128_oem; 328 /* coeff used to map user evenly distributed points 329 * to our hardware points (predefined) for gamma 1025 */ 330 struct pixel_gamma_point *coeff128_dx; 331 /* evenly distributed points, gamma 256 software points 0-255 */ 332 struct gamma_pixel *axis_x_256; 333 /* evenly distributed points, gamma 1025 software points 0-1025 */ 334 struct gamma_pixel *axis_x_1025; 335 /* OEM supplied gamma for regamma LUT */ 336 struct pwl_float_data *rgb_oem; 337 /* user supplied gamma */ 338 struct pwl_float_data *rgb_user; 339 uint32_t extra_points; 340 bool use_half_points; 341 struct fixed31_32 x_max1; 342 struct fixed31_32 x_max2; 343 struct fixed31_32 x_min; 344 struct fixed31_32 divider1; 345 struct fixed31_32 divider2; 346 struct fixed31_32 divider3; 347 }; 348 349 /* OPP RELATED */ 350 #define TO_DCE110_OPP(opp)\ 351 container_of(opp, struct dce110_opp, base) 352 353 struct dce110_opp { 354 struct output_pixel_processor base; 355 const struct dce_opp_registers *regs; 356 const struct dce_opp_shift *opp_shift; 357 const struct dce_opp_mask *opp_mask; 358 struct dce110_regamma regamma; 359 }; 360 361 bool dce110_opp_construct(struct dce110_opp *opp110, 362 struct dc_context *ctx, 363 uint32_t inst, 364 const struct dce_opp_registers *regs, 365 const struct dce_opp_shift *opp_shift, 366 const struct dce_opp_mask *opp_mask); 367 368 void dce110_opp_destroy(struct output_pixel_processor **opp); 369 370 /* REGAMMA RELATED */ 371 void dce110_opp_power_on_regamma_lut( 372 struct output_pixel_processor *opp, 373 bool power_on); 374 375 bool dce110_opp_program_regamma_pwl( 376 struct output_pixel_processor *opp, 377 const struct pwl_params *params); 378 379 void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, 380 enum opp_regamma mode); 381 382 void dce110_opp_set_csc_adjustment( 383 struct output_pixel_processor *opp, 384 const struct out_csc_color_matrix *tbl_entry); 385 386 void dce110_opp_set_csc_default( 387 struct output_pixel_processor *opp, 388 const struct default_adjustment *default_adjust); 389 390 /* FORMATTER RELATED */ 391 void dce110_opp_program_bit_depth_reduction( 392 struct output_pixel_processor *opp, 393 const struct bit_depth_reduction_params *params); 394 395 void dce110_opp_program_clamping_and_pixel_encoding( 396 struct output_pixel_processor *opp, 397 const struct clamping_and_pixel_encoding_params *params); 398 399 void dce110_opp_set_dyn_expansion( 400 struct output_pixel_processor *opp, 401 enum dc_color_space color_sp, 402 enum dc_color_depth color_dpth, 403 enum signal_type signal); 404 405 void dce110_opp_program_fmt( 406 struct output_pixel_processor *opp, 407 struct bit_depth_reduction_params *fmt_bit_depth, 408 struct clamping_and_pixel_encoding_params *clamping); 409 410 void dce110_opp_set_clamping( 411 struct dce110_opp *opp110, 412 const struct clamping_and_pixel_encoding_params *params); 413 414 #endif 415