1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_OPP_DCE_H__ 26 #define __DC_OPP_DCE_H__ 27 28 #include "dc_types.h" 29 #include "opp.h" 30 #include "core_types.h" 31 32 #define FROM_DCE11_OPP(opp)\ 33 container_of(opp, struct dce110_opp, base) 34 35 enum dce110_opp_reg_type { 36 DCE110_OPP_REG_DCP = 0, 37 DCE110_OPP_REG_DCFE, 38 DCE110_OPP_REG_FMT, 39 40 DCE110_OPP_REG_MAX 41 }; 42 43 #define OPP_COMMON_REG_LIST_BASE(id) \ 44 SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ 45 SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ 46 SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ 47 SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ 48 SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ 49 SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ 50 SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ 51 SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ 52 SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ 53 SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ 54 SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ 55 SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ 56 SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ 57 SRI(REGAMMA_LUT_INDEX, DCP, id), \ 58 SRI(REGAMMA_LUT_DATA, DCP, id), \ 59 SRI(REGAMMA_CONTROL, DCP, id), \ 60 SRI(OUTPUT_CSC_C11_C12, DCP, id), \ 61 SRI(OUTPUT_CSC_C13_C14, DCP, id), \ 62 SRI(OUTPUT_CSC_C21_C22, DCP, id), \ 63 SRI(OUTPUT_CSC_C23_C24, DCP, id), \ 64 SRI(OUTPUT_CSC_C31_C32, DCP, id), \ 65 SRI(OUTPUT_CSC_C33_C34, DCP, id), \ 66 SRI(OUTPUT_CSC_CONTROL, DCP, id), \ 67 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 68 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 69 SRI(FMT_CONTROL, FMT, id), \ 70 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 71 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 72 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 73 SRI(FMT_CLAMP_CNTL, FMT, id), \ 74 SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \ 75 SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \ 76 SRI(FMT_CLAMP_COMPONENT_B, FMT, id) 77 78 #define OPP_DCE_80_REG_LIST(id) \ 79 OPP_COMMON_REG_LIST_BASE(id), \ 80 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \ 81 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 82 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 83 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 84 85 #define OPP_DCE_100_REG_LIST(id) \ 86 OPP_COMMON_REG_LIST_BASE(id), \ 87 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \ 88 SRI(DCFE_MEM_PWR_STATUS, CRTC, id), \ 89 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 90 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 91 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 92 93 #define OPP_DCE_110_REG_LIST(id) \ 94 OPP_COMMON_REG_LIST_BASE(id), \ 95 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ 96 SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ 97 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 98 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 99 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 100 101 #define OPP_DCE_112_REG_LIST(id) \ 102 OPP_COMMON_REG_LIST_BASE(id), \ 103 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ 104 SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ 105 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 106 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 107 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ 108 SRI(CONTROL, FMT_MEMORY, id) 109 110 #define OPP_DCE_120_REG_LIST(id) \ 111 OPP_COMMON_REG_LIST_BASE(id), \ 112 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ 113 SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ 114 SRI(CONTROL, FMT_MEMORY, id) 115 116 #define OPP_SF(reg_name, field_name, post_fix)\ 117 .field_name = reg_name ## __ ## field_name ## post_fix 118 119 #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 120 OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ 121 OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ 122 OPP_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ 123 OPP_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ 124 OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ 125 OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ 126 OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 127 OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 128 OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 129 OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 130 OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ 131 OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ 132 OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ 133 OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ 134 OPP_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ 135 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 136 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 137 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 138 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 139 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 140 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 141 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 142 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 143 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 144 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 145 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 146 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 147 OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 148 OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 149 OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 150 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 151 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 152 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 153 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 154 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 155 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 156 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 157 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 158 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 159 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 160 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 161 OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 162 OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 163 OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 164 OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 165 OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 166 OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 167 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 168 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 169 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh) 170 171 #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ 172 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 173 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 174 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 175 OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ 176 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 177 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 178 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 179 180 #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ 181 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 182 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 183 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 184 OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ 185 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 186 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 187 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 188 189 #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 190 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 191 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 192 OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 193 OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ 194 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 195 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 196 OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 197 OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 198 OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ 199 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 200 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 201 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 202 203 #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ 204 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 205 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ 206 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ 207 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) 208 209 #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ 210 OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 211 OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 212 OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ 213 OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ 214 OPP_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ 215 OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ 216 OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ 217 OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ 218 OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 219 OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 220 OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 221 OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 222 OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ 223 OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ 224 OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ 225 OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ 226 OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ 227 OPP_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ 228 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 229 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 230 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 231 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 232 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 233 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 234 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 235 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 236 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 237 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 238 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 239 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 240 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 241 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 242 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 243 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 244 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 245 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 246 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 247 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 248 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 249 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 250 OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\ 251 OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 252 OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 253 OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 254 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 255 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 256 OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 257 OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 258 OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 259 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 260 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 261 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 262 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 263 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 264 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 265 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 266 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 267 OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 268 OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 269 OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ 270 OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) 271 272 #define OPP_REG_FIELD_LIST(type) \ 273 type DCP_REGAMMA_MEM_PWR_DIS; \ 274 type DCP_LUT_MEM_PWR_DIS; \ 275 type REGAMMA_LUT_LIGHT_SLEEP_DIS; \ 276 type DCP_LUT_LIGHT_SLEEP_DIS; \ 277 type REGAMMA_CNTLA_EXP_REGION_START; \ 278 type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \ 279 type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \ 280 type REGAMMA_CNTLA_EXP_REGION_END; \ 281 type REGAMMA_CNTLA_EXP_REGION_END_BASE; \ 282 type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \ 283 type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \ 284 type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \ 285 type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \ 286 type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \ 287 type DCP_REGAMMA_MEM_PWR_STATE; \ 288 type REGAMMA_LUT_MEM_PWR_STATE; \ 289 type REGAMMA_LUT_WRITE_EN_MASK; \ 290 type GRPH_REGAMMA_MODE; \ 291 type OUTPUT_CSC_C11; \ 292 type OUTPUT_CSC_C12; \ 293 type OUTPUT_CSC_GRPH_MODE; \ 294 type FMT_DYNAMIC_EXP_EN; \ 295 type FMT_DYNAMIC_EXP_MODE; \ 296 type FMT_TRUNCATE_EN; \ 297 type FMT_TRUNCATE_DEPTH; \ 298 type FMT_TRUNCATE_MODE; \ 299 type FMT_SPATIAL_DITHER_EN; \ 300 type FMT_SPATIAL_DITHER_DEPTH; \ 301 type FMT_SPATIAL_DITHER_MODE; \ 302 type FMT_TEMPORAL_DITHER_EN; \ 303 type FMT_TEMPORAL_DITHER_RESET; \ 304 type FMT_TEMPORAL_DITHER_OFFSET; \ 305 type FMT_TEMPORAL_DITHER_DEPTH; \ 306 type FMT_TEMPORAL_LEVEL; \ 307 type FMT_25FRC_SEL; \ 308 type FMT_50FRC_SEL; \ 309 type FMT_75FRC_SEL; \ 310 type FMT_HIGHPASS_RANDOM_ENABLE; \ 311 type FMT_FRAME_RANDOM_ENABLE; \ 312 type FMT_RGB_RANDOM_ENABLE; \ 313 type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 314 type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 315 type FMT_STEREOSYNC_OVERRIDE; \ 316 type FMT_RAND_R_SEED; \ 317 type FMT_RAND_G_SEED; \ 318 type FMT_RAND_B_SEED; \ 319 type FMT420_MEM0_SOURCE_SEL; \ 320 type FMT420_MEM0_PWR_FORCE; \ 321 type FMT_SRC_SELECT; \ 322 type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \ 323 type FMT_420_PIXEL_PHASE_LOCKED; \ 324 type FMT_CLAMP_DATA_EN; \ 325 type FMT_CLAMP_COLOR_FORMAT; \ 326 type FMT_CLAMP_LOWER_R; \ 327 type FMT_CLAMP_UPPER_R; \ 328 type FMT_CLAMP_LOWER_G; \ 329 type FMT_CLAMP_UPPER_G; \ 330 type FMT_CLAMP_LOWER_B; \ 331 type FMT_CLAMP_UPPER_B; \ 332 type FMT_PIXEL_ENCODING; \ 333 type FMT_SUBSAMPLING_ORDER; \ 334 type FMT_SUBSAMPLING_MODE; \ 335 type FMT_CBCR_BIT_REDUCTION_BYPASS;\ 336 337 struct dce_opp_shift { 338 OPP_REG_FIELD_LIST(uint8_t) 339 }; 340 341 struct dce_opp_mask { 342 OPP_REG_FIELD_LIST(uint32_t) 343 }; 344 345 struct dce_opp_registers { 346 uint32_t DCFE_MEM_PWR_CTRL; 347 uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; 348 uint32_t REGAMMA_CNTLA_START_CNTL; 349 uint32_t REGAMMA_CNTLA_SLOPE_CNTL; 350 uint32_t REGAMMA_CNTLA_END_CNTL1; 351 uint32_t REGAMMA_CNTLA_END_CNTL2; 352 uint32_t REGAMMA_CNTLA_REGION_0_1; 353 uint32_t REGAMMA_CNTLA_REGION_2_3; 354 uint32_t REGAMMA_CNTLA_REGION_4_5; 355 uint32_t REGAMMA_CNTLA_REGION_6_7; 356 uint32_t REGAMMA_CNTLA_REGION_8_9; 357 uint32_t REGAMMA_CNTLA_REGION_10_11; 358 uint32_t REGAMMA_CNTLA_REGION_12_13; 359 uint32_t REGAMMA_CNTLA_REGION_14_15; 360 uint32_t REGAMMA_LUT_WRITE_EN_MASK; 361 uint32_t REGAMMA_LUT_INDEX; 362 uint32_t DCFE_MEM_PWR_STATUS; 363 uint32_t REGAMMA_LUT_DATA; 364 uint32_t REGAMMA_CONTROL; 365 uint32_t OUTPUT_CSC_C11_C12; 366 uint32_t OUTPUT_CSC_C13_C14; 367 uint32_t OUTPUT_CSC_C21_C22; 368 uint32_t OUTPUT_CSC_C23_C24; 369 uint32_t OUTPUT_CSC_C31_C32; 370 uint32_t OUTPUT_CSC_C33_C34; 371 uint32_t OUTPUT_CSC_CONTROL; 372 uint32_t FMT_DYNAMIC_EXP_CNTL; 373 uint32_t FMT_BIT_DEPTH_CONTROL; 374 uint32_t FMT_CONTROL; 375 uint32_t FMT_DITHER_RAND_R_SEED; 376 uint32_t FMT_DITHER_RAND_G_SEED; 377 uint32_t FMT_DITHER_RAND_B_SEED; 378 uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL; 379 uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX; 380 uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX; 381 uint32_t CONTROL; 382 uint32_t FMT_CLAMP_CNTL; 383 uint32_t FMT_CLAMP_COMPONENT_R; 384 uint32_t FMT_CLAMP_COMPONENT_G; 385 uint32_t FMT_CLAMP_COMPONENT_B; 386 }; 387 388 /* OPP RELATED */ 389 #define TO_DCE110_OPP(opp)\ 390 container_of(opp, struct dce110_opp, base) 391 392 struct dce110_opp { 393 struct output_pixel_processor base; 394 const struct dce_opp_registers *regs; 395 const struct dce_opp_shift *opp_shift; 396 const struct dce_opp_mask *opp_mask; 397 }; 398 399 bool dce110_opp_construct(struct dce110_opp *opp110, 400 struct dc_context *ctx, 401 uint32_t inst, 402 const struct dce_opp_registers *regs, 403 const struct dce_opp_shift *opp_shift, 404 const struct dce_opp_mask *opp_mask); 405 406 void dce110_opp_destroy(struct output_pixel_processor **opp); 407 408 /* REGAMMA RELATED */ 409 void dce110_opp_power_on_regamma_lut( 410 struct output_pixel_processor *opp, 411 bool power_on); 412 413 bool dce110_opp_program_regamma_pwl( 414 struct output_pixel_processor *opp, 415 const struct pwl_params *params); 416 417 void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, 418 enum opp_regamma mode); 419 420 void dce110_opp_set_csc_adjustment( 421 struct output_pixel_processor *opp, 422 const struct out_csc_color_matrix *tbl_entry); 423 424 void dce110_opp_set_csc_default( 425 struct output_pixel_processor *opp, 426 const struct default_adjustment *default_adjust); 427 428 /* FORMATTER RELATED */ 429 void dce110_opp_program_bit_depth_reduction( 430 struct output_pixel_processor *opp, 431 const struct bit_depth_reduction_params *params); 432 433 void dce110_opp_program_clamping_and_pixel_encoding( 434 struct output_pixel_processor *opp, 435 const struct clamping_and_pixel_encoding_params *params); 436 437 void dce110_opp_set_dyn_expansion( 438 struct output_pixel_processor *opp, 439 enum dc_color_space color_sp, 440 enum dc_color_depth color_dpth, 441 enum signal_type signal); 442 443 void dce110_opp_program_fmt( 444 struct output_pixel_processor *opp, 445 struct bit_depth_reduction_params *fmt_bit_depth, 446 struct clamping_and_pixel_encoding_params *clamping); 447 448 void dce110_opp_set_clamping( 449 struct dce110_opp *opp110, 450 const struct clamping_and_pixel_encoding_params *params); 451 452 #endif 453