1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "reg_helper.h" 30 31 #include "core_types.h" 32 #include "link_encoder.h" 33 #include "dce_link_encoder.h" 34 #include "stream_encoder.h" 35 #include "i2caux_interface.h" 36 #include "dc_bios_types.h" 37 38 #include "gpio_service_interface.h" 39 40 #include "dce/dce_11_0_d.h" 41 #include "dce/dce_11_0_sh_mask.h" 42 #include "dce/dce_11_0_enum.h" 43 44 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 45 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa 46 #endif 47 48 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 49 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L 50 #endif 51 52 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 53 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L 54 #endif 55 56 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 57 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c 58 #endif 59 60 #define CTX \ 61 enc110->base.ctx 62 #define DC_LOGGER \ 63 enc110->base.ctx->logger 64 65 #define REG(reg)\ 66 (enc110->link_regs->reg) 67 68 #define AUX_REG(reg)\ 69 (enc110->aux_regs->reg) 70 71 #define HPD_REG(reg)\ 72 (enc110->hpd_regs->reg) 73 74 #define DEFAULT_AUX_MAX_DATA_SIZE 16 75 #define AUX_MAX_DEFER_WRITE_RETRY 20 76 /* 77 * @brief 78 * Trigger Source Select 79 * ASIC-dependent, actual values for register programming 80 */ 81 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0 82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1 83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2 84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4 85 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08 86 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10 87 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 88 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 89 90 enum { 91 DP_MST_UPDATE_MAX_RETRY = 50 92 }; 93 94 #define DIG_REG(reg)\ 95 (reg + enc110->offsets.dig) 96 97 #define DP_REG(reg)\ 98 (reg + enc110->offsets.dp) 99 100 static const struct link_encoder_funcs dce110_lnk_enc_funcs = { 101 .validate_output_with_stream = 102 dce110_link_encoder_validate_output_with_stream, 103 .hw_init = dce110_link_encoder_hw_init, 104 .setup = dce110_link_encoder_setup, 105 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 106 .enable_dp_output = dce110_link_encoder_enable_dp_output, 107 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, 108 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 109 .disable_output = dce110_link_encoder_disable_output, 110 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 111 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, 112 .update_mst_stream_allocation_table = 113 dce110_link_encoder_update_mst_stream_allocation_table, 114 .psr_program_dp_dphy_fast_training = 115 dce110_psr_program_dp_dphy_fast_training, 116 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 117 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 118 .enable_hpd = dce110_link_encoder_enable_hpd, 119 .disable_hpd = dce110_link_encoder_disable_hpd, 120 .is_dig_enabled = dce110_is_dig_enabled, 121 .destroy = dce110_link_encoder_destroy, 122 .get_max_link_cap = dce110_link_encoder_get_max_link_cap, 123 .get_dig_frontend = dce110_get_dig_frontend, 124 }; 125 126 static enum bp_result link_transmitter_control( 127 struct dce110_link_encoder *enc110, 128 struct bp_transmitter_control *cntl) 129 { 130 enum bp_result result; 131 struct dc_bios *bp = enc110->base.ctx->dc_bios; 132 133 result = bp->funcs->transmitter_control(bp, cntl); 134 135 return result; 136 } 137 138 static void enable_phy_bypass_mode( 139 struct dce110_link_encoder *enc110, 140 bool enable) 141 { 142 /* This register resides in DP back end block; 143 * transmitter is used for the offset */ 144 145 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); 146 147 } 148 149 static void disable_prbs_symbols( 150 struct dce110_link_encoder *enc110, 151 bool disable) 152 { 153 /* This register resides in DP back end block; 154 * transmitter is used for the offset */ 155 156 REG_UPDATE_4(DP_DPHY_CNTL, 157 DPHY_ATEST_SEL_LANE0, disable, 158 DPHY_ATEST_SEL_LANE1, disable, 159 DPHY_ATEST_SEL_LANE2, disable, 160 DPHY_ATEST_SEL_LANE3, disable); 161 } 162 163 static void disable_prbs_mode( 164 struct dce110_link_encoder *enc110) 165 { 166 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); 167 } 168 169 static void program_pattern_symbols( 170 struct dce110_link_encoder *enc110, 171 uint16_t pattern_symbols[8]) 172 { 173 /* This register resides in DP back end block; 174 * transmitter is used for the offset */ 175 176 REG_SET_3(DP_DPHY_SYM0, 0, 177 DPHY_SYM1, pattern_symbols[0], 178 DPHY_SYM2, pattern_symbols[1], 179 DPHY_SYM3, pattern_symbols[2]); 180 181 /* This register resides in DP back end block; 182 * transmitter is used for the offset */ 183 184 REG_SET_3(DP_DPHY_SYM1, 0, 185 DPHY_SYM4, pattern_symbols[3], 186 DPHY_SYM5, pattern_symbols[4], 187 DPHY_SYM6, pattern_symbols[5]); 188 189 /* This register resides in DP back end block; 190 * transmitter is used for the offset */ 191 192 REG_SET_2(DP_DPHY_SYM2, 0, 193 DPHY_SYM7, pattern_symbols[6], 194 DPHY_SYM8, pattern_symbols[7]); 195 } 196 197 static void set_dp_phy_pattern_d102( 198 struct dce110_link_encoder *enc110) 199 { 200 /* Disable PHY Bypass mode to setup the test pattern */ 201 enable_phy_bypass_mode(enc110, false); 202 203 /* For 10-bit PRBS or debug symbols 204 * please use the following sequence: */ 205 206 /* Enable debug symbols on the lanes */ 207 208 disable_prbs_symbols(enc110, true); 209 210 /* Disable PRBS mode */ 211 disable_prbs_mode(enc110); 212 213 /* Program debug symbols to be output */ 214 { 215 uint16_t pattern_symbols[8] = { 216 0x2AA, 0x2AA, 0x2AA, 0x2AA, 217 0x2AA, 0x2AA, 0x2AA, 0x2AA 218 }; 219 220 program_pattern_symbols(enc110, pattern_symbols); 221 } 222 223 /* Enable phy bypass mode to enable the test pattern */ 224 225 enable_phy_bypass_mode(enc110, true); 226 } 227 228 static void set_link_training_complete( 229 struct dce110_link_encoder *enc110, 230 bool complete) 231 { 232 /* This register resides in DP back end block; 233 * transmitter is used for the offset */ 234 235 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); 236 237 } 238 239 unsigned int dce110_get_dig_frontend(struct link_encoder *enc) 240 { 241 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 242 u32 value; 243 enum engine_id result; 244 245 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); 246 247 switch (value) { 248 case DCE110_DIG_FE_SOURCE_SELECT_DIGA: 249 result = ENGINE_ID_DIGA; 250 break; 251 case DCE110_DIG_FE_SOURCE_SELECT_DIGB: 252 result = ENGINE_ID_DIGB; 253 break; 254 case DCE110_DIG_FE_SOURCE_SELECT_DIGC: 255 result = ENGINE_ID_DIGC; 256 break; 257 case DCE110_DIG_FE_SOURCE_SELECT_DIGD: 258 result = ENGINE_ID_DIGD; 259 break; 260 case DCE110_DIG_FE_SOURCE_SELECT_DIGE: 261 result = ENGINE_ID_DIGE; 262 break; 263 case DCE110_DIG_FE_SOURCE_SELECT_DIGF: 264 result = ENGINE_ID_DIGF; 265 break; 266 case DCE110_DIG_FE_SOURCE_SELECT_DIGG: 267 result = ENGINE_ID_DIGG; 268 break; 269 default: 270 // invalid source select DIG 271 result = ENGINE_ID_UNKNOWN; 272 } 273 274 return result; 275 } 276 277 void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 278 struct link_encoder *enc, 279 uint32_t index) 280 { 281 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 282 /* Write Training Pattern */ 283 284 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); 285 286 /* Set HW Register Training Complete to false */ 287 288 set_link_training_complete(enc110, false); 289 290 /* Disable PHY Bypass mode to output Training Pattern */ 291 292 enable_phy_bypass_mode(enc110, false); 293 294 /* Disable PRBS mode */ 295 disable_prbs_mode(enc110); 296 } 297 298 static void setup_panel_mode( 299 struct dce110_link_encoder *enc110, 300 enum dp_panel_mode panel_mode) 301 { 302 uint32_t value; 303 struct dc_context *ctx = enc110->base.ctx; 304 305 /* if psp set panel mode, dal should be program it */ 306 if (ctx->dc->caps.psp_setup_panel_mode) 307 return; 308 309 ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); 310 value = REG_READ(DP_DPHY_INTERNAL_CTRL); 311 312 switch (panel_mode) { 313 case DP_PANEL_MODE_EDP: 314 value = 0x1; 315 break; 316 case DP_PANEL_MODE_SPECIAL: 317 value = 0x11; 318 break; 319 default: 320 value = 0x0; 321 break; 322 } 323 324 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); 325 } 326 327 static void set_dp_phy_pattern_symbol_error( 328 struct dce110_link_encoder *enc110) 329 { 330 /* Disable PHY Bypass mode to setup the test pattern */ 331 enable_phy_bypass_mode(enc110, false); 332 333 /* program correct panel mode*/ 334 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 335 336 /* A PRBS23 pattern is used for most DP electrical measurements. */ 337 338 /* Enable PRBS symbols on the lanes */ 339 disable_prbs_symbols(enc110, false); 340 341 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */ 342 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 343 DPHY_PRBS_SEL, 1, 344 DPHY_PRBS_EN, 1); 345 346 /* Enable phy bypass mode to enable the test pattern */ 347 enable_phy_bypass_mode(enc110, true); 348 } 349 350 static void set_dp_phy_pattern_prbs7( 351 struct dce110_link_encoder *enc110) 352 { 353 /* Disable PHY Bypass mode to setup the test pattern */ 354 enable_phy_bypass_mode(enc110, false); 355 356 /* A PRBS7 pattern is used for most DP electrical measurements. */ 357 358 /* Enable PRBS symbols on the lanes */ 359 disable_prbs_symbols(enc110, false); 360 361 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */ 362 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 363 DPHY_PRBS_SEL, 0, 364 DPHY_PRBS_EN, 1); 365 366 /* Enable phy bypass mode to enable the test pattern */ 367 enable_phy_bypass_mode(enc110, true); 368 } 369 370 static void set_dp_phy_pattern_80bit_custom( 371 struct dce110_link_encoder *enc110, 372 const uint8_t *pattern) 373 { 374 /* Disable PHY Bypass mode to setup the test pattern */ 375 enable_phy_bypass_mode(enc110, false); 376 377 /* Enable debug symbols on the lanes */ 378 379 disable_prbs_symbols(enc110, true); 380 381 /* Enable PHY bypass mode to enable the test pattern */ 382 /* TODO is it really needed ? */ 383 384 enable_phy_bypass_mode(enc110, true); 385 386 /* Program 80 bit custom pattern */ 387 { 388 uint16_t pattern_symbols[8]; 389 390 pattern_symbols[0] = 391 ((pattern[1] & 0x03) << 8) | pattern[0]; 392 pattern_symbols[1] = 393 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f); 394 pattern_symbols[2] = 395 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f); 396 pattern_symbols[3] = 397 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03); 398 pattern_symbols[4] = 399 ((pattern[6] & 0x03) << 8) | pattern[5]; 400 pattern_symbols[5] = 401 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f); 402 pattern_symbols[6] = 403 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f); 404 pattern_symbols[7] = 405 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03); 406 407 program_pattern_symbols(enc110, pattern_symbols); 408 } 409 410 /* Enable phy bypass mode to enable the test pattern */ 411 412 enable_phy_bypass_mode(enc110, true); 413 } 414 415 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( 416 struct dce110_link_encoder *enc110, 417 unsigned int cp2520_pattern) 418 { 419 420 /* previously there is a register DP_HBR2_EYE_PATTERN 421 * that is enabled to get the pattern. 422 * But it does not work with the latest spec change, 423 * so we are programming the following registers manually. 424 * 425 * The following settings have been confirmed 426 * by Nick Chorney and Sandra Liu */ 427 428 /* Disable PHY Bypass mode to setup the test pattern */ 429 430 enable_phy_bypass_mode(enc110, false); 431 432 /* Setup DIG encoder in DP SST mode */ 433 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 434 435 /* ensure normal panel mode. */ 436 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 437 438 /* no vbid after BS (SR) 439 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 440 * 11000260 / 11000104 / 110000FC */ 441 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 442 DP_IDLE_BS_INTERVAL, 0xFC, 443 DP_VBID_DISABLE, 1, 444 DP_VID_ENHANCED_FRAME_MODE, 1); 445 446 /* swap every BS with SR */ 447 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); 448 449 /* select cp2520 patterns */ 450 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 451 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 452 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 453 else 454 /* pre-DCE11 can only generate CP2520 pattern 2 */ 455 ASSERT(cp2520_pattern == 2); 456 457 /* set link training complete */ 458 set_link_training_complete(enc110, true); 459 460 /* disable video stream */ 461 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 462 463 /* Disable PHY Bypass mode to setup the test pattern */ 464 enable_phy_bypass_mode(enc110, false); 465 } 466 467 #if defined(CONFIG_DRM_AMD_DC_SI) 468 static void dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2( 469 struct dce110_link_encoder *enc110, 470 unsigned int cp2520_pattern) 471 { 472 473 /* previously there is a register DP_HBR2_EYE_PATTERN 474 * that is enabled to get the pattern. 475 * But it does not work with the latest spec change, 476 * so we are programming the following registers manually. 477 * 478 * The following settings have been confirmed 479 * by Nick Chorney and Sandra Liu */ 480 481 /* Disable PHY Bypass mode to setup the test pattern */ 482 483 enable_phy_bypass_mode(enc110, false); 484 485 /* Setup DIG encoder in DP SST mode */ 486 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 487 488 /* ensure normal panel mode. */ 489 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 490 491 /* no vbid after BS (SR) 492 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 493 * 11000260 / 11000104 / 110000FC */ 494 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 495 DP_IDLE_BS_INTERVAL, 0xFC, 496 DP_VBID_DISABLE, 1, 497 DP_VID_ENHANCED_FRAME_MODE, 1); 498 499 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip swap BS with SR */ 500 501 /* select cp2520 patterns */ 502 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 503 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 504 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 505 else 506 /* pre-DCE11 can only generate CP2520 pattern 2 */ 507 ASSERT(cp2520_pattern == 2); 508 509 /* set link training complete */ 510 set_link_training_complete(enc110, true); 511 512 /* disable video stream */ 513 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 514 515 /* Disable PHY Bypass mode to setup the test pattern */ 516 enable_phy_bypass_mode(enc110, false); 517 } 518 #endif 519 520 static void set_dp_phy_pattern_passthrough_mode( 521 struct dce110_link_encoder *enc110, 522 enum dp_panel_mode panel_mode) 523 { 524 /* program correct panel mode */ 525 setup_panel_mode(enc110, panel_mode); 526 527 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT 528 * in case we were doing HBR2 compliance pattern before 529 */ 530 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 531 DP_IDLE_BS_INTERVAL, 0x2000, 532 DP_VBID_DISABLE, 0, 533 DP_VID_ENHANCED_FRAME_MODE, 1); 534 535 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); 536 537 /* set link training complete */ 538 set_link_training_complete(enc110, true); 539 540 /* Disable PHY Bypass mode to setup the test pattern */ 541 enable_phy_bypass_mode(enc110, false); 542 543 /* Disable PRBS mode */ 544 disable_prbs_mode(enc110); 545 } 546 547 #if defined(CONFIG_DRM_AMD_DC_SI) 548 static void dce60_set_dp_phy_pattern_passthrough_mode( 549 struct dce110_link_encoder *enc110, 550 enum dp_panel_mode panel_mode) 551 { 552 /* program correct panel mode */ 553 setup_panel_mode(enc110, panel_mode); 554 555 /* restore LINK_FRAMING_CNTL 556 * in case we were doing HBR2 compliance pattern before 557 */ 558 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 559 DP_IDLE_BS_INTERVAL, 0x2000, 560 DP_VBID_DISABLE, 0, 561 DP_VID_ENHANCED_FRAME_MODE, 1); 562 563 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip DPHY_SCRAMBLER_BS_COUNT restore */ 564 565 /* set link training complete */ 566 set_link_training_complete(enc110, true); 567 568 /* Disable PHY Bypass mode to setup the test pattern */ 569 enable_phy_bypass_mode(enc110, false); 570 571 /* Disable PRBS mode */ 572 disable_prbs_mode(enc110); 573 } 574 #endif 575 576 /* return value is bit-vector */ 577 static uint8_t get_frontend_source( 578 enum engine_id engine) 579 { 580 switch (engine) { 581 case ENGINE_ID_DIGA: 582 return DCE110_DIG_FE_SOURCE_SELECT_DIGA; 583 case ENGINE_ID_DIGB: 584 return DCE110_DIG_FE_SOURCE_SELECT_DIGB; 585 case ENGINE_ID_DIGC: 586 return DCE110_DIG_FE_SOURCE_SELECT_DIGC; 587 case ENGINE_ID_DIGD: 588 return DCE110_DIG_FE_SOURCE_SELECT_DIGD; 589 case ENGINE_ID_DIGE: 590 return DCE110_DIG_FE_SOURCE_SELECT_DIGE; 591 case ENGINE_ID_DIGF: 592 return DCE110_DIG_FE_SOURCE_SELECT_DIGF; 593 case ENGINE_ID_DIGG: 594 return DCE110_DIG_FE_SOURCE_SELECT_DIGG; 595 default: 596 ASSERT_CRITICAL(false); 597 return DCE110_DIG_FE_SOURCE_SELECT_INVALID; 598 } 599 } 600 601 static void configure_encoder( 602 struct dce110_link_encoder *enc110, 603 const struct dc_link_settings *link_settings) 604 { 605 /* set number of lanes */ 606 607 REG_SET(DP_CONFIG, 0, 608 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 609 610 /* setup scrambler */ 611 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); 612 } 613 614 #if defined(CONFIG_DRM_AMD_DC_SI) 615 static void dce60_configure_encoder( 616 struct dce110_link_encoder *enc110, 617 const struct dc_link_settings *link_settings) 618 { 619 /* set number of lanes */ 620 621 REG_SET(DP_CONFIG, 0, 622 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 623 624 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip setup scrambler */ 625 } 626 #endif 627 628 static void aux_initialize( 629 struct dce110_link_encoder *enc110) 630 { 631 struct dc_context *ctx = enc110->base.ctx; 632 enum hpd_source_id hpd_source = enc110->base.hpd_source; 633 uint32_t addr = AUX_REG(AUX_CONTROL); 634 uint32_t value = dm_read_reg(ctx, addr); 635 636 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); 637 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); 638 dm_write_reg(ctx, addr, value); 639 640 addr = AUX_REG(AUX_DPHY_RX_CONTROL0); 641 value = dm_read_reg(ctx, addr); 642 643 /* 1/4 window (the maximum allowed) */ 644 set_reg_field_value(value, 1, 645 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW); 646 dm_write_reg(ctx, addr, value); 647 648 } 649 650 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 651 bool exit_link_training_required) 652 { 653 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 654 655 if (exit_link_training_required) 656 REG_UPDATE(DP_DPHY_FAST_TRAINING, 657 DPHY_RX_FAST_TRAINING_CAPABLE, 1); 658 else { 659 REG_UPDATE(DP_DPHY_FAST_TRAINING, 660 DPHY_RX_FAST_TRAINING_CAPABLE, 0); 661 /*In DCE 11, we are able to pre-program a Force SR register 662 * to be able to trigger SR symbol after 5 idle patterns 663 * transmitted. Upon PSR Exit, DMCU can trigger 664 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to 665 * DPHY_LOAD_BS_COUNT_START and the internal counter 666 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be 667 * replaced by SR symbol once. 668 */ 669 670 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5); 671 } 672 } 673 674 void dce110_psr_program_secondary_packet(struct link_encoder *enc, 675 unsigned int sdp_transmit_line_num_deadline) 676 { 677 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 678 679 REG_UPDATE_2(DP_SEC_CNTL1, 680 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline, 681 DP_SEC_GSP0_PRIORITY, 1); 682 } 683 684 bool dce110_is_dig_enabled(struct link_encoder *enc) 685 { 686 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 687 uint32_t value; 688 689 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); 690 return value; 691 } 692 693 static void link_encoder_disable(struct dce110_link_encoder *enc110) 694 { 695 /* reset training pattern */ 696 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, 697 DPHY_TRAINING_PATTERN_SEL, 0); 698 699 /* reset training complete */ 700 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); 701 702 /* reset panel mode */ 703 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 704 } 705 706 static void hpd_initialize( 707 struct dce110_link_encoder *enc110) 708 { 709 /* Associate HPD with DIG_BE */ 710 enum hpd_source_id hpd_source = enc110->base.hpd_source; 711 712 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); 713 } 714 715 bool dce110_link_encoder_validate_dvi_output( 716 const struct dce110_link_encoder *enc110, 717 enum signal_type connector_signal, 718 enum signal_type signal, 719 const struct dc_crtc_timing *crtc_timing) 720 { 721 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; 722 723 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK) 724 max_pixel_clock *= 2; 725 726 /* This handles the case of HDMI downgrade to DVI we don't want to 727 * we don't want to cap the pixel clock if the DDI is not DVI. 728 */ 729 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK && 730 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 731 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock; 732 733 /* DVI only support RGB pixel encoding */ 734 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 735 return false; 736 737 /*connect DVI via adpater's HDMI connector*/ 738 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 739 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) && 740 signal != SIGNAL_TYPE_HDMI_TYPE_A && 741 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10)) 742 return false; 743 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) 744 return false; 745 746 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10)) 747 return false; 748 749 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */ 750 switch (crtc_timing->display_color_depth) { 751 case COLOR_DEPTH_666: 752 case COLOR_DEPTH_888: 753 break; 754 case COLOR_DEPTH_101010: 755 case COLOR_DEPTH_161616: 756 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK) 757 return false; 758 break; 759 default: 760 return false; 761 } 762 763 return true; 764 } 765 766 static bool dce110_link_encoder_validate_hdmi_output( 767 const struct dce110_link_encoder *enc110, 768 const struct dc_crtc_timing *crtc_timing, 769 int adjusted_pix_clk_khz) 770 { 771 enum dc_color_depth max_deep_color = 772 enc110->base.features.max_hdmi_deep_color; 773 774 if (max_deep_color < crtc_timing->display_color_depth) 775 return false; 776 777 if (crtc_timing->display_color_depth < COLOR_DEPTH_888) 778 return false; 779 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK) 780 return false; 781 782 if ((adjusted_pix_clk_khz == 0) || 783 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) 784 return false; 785 786 /* DCE11 HW does not support 420 */ 787 if (!enc110->base.features.hdmi_ycbcr420_supported && 788 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 789 return false; 790 791 if ((!enc110->base.features.flags.bits.HDMI_6GB_EN || 792 enc110->base.ctx->dc->debug.hdmi20_disable) && 793 adjusted_pix_clk_khz >= 300000) 794 return false; 795 if (enc110->base.ctx->dc->debug.hdmi20_disable && 796 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 797 return false; 798 return true; 799 } 800 801 bool dce110_link_encoder_validate_dp_output( 802 const struct dce110_link_encoder *enc110, 803 const struct dc_crtc_timing *crtc_timing) 804 { 805 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 806 return false; 807 808 return true; 809 } 810 811 void dce110_link_encoder_construct( 812 struct dce110_link_encoder *enc110, 813 const struct encoder_init_data *init_data, 814 const struct encoder_feature_support *enc_features, 815 const struct dce110_link_enc_registers *link_regs, 816 const struct dce110_link_enc_aux_registers *aux_regs, 817 const struct dce110_link_enc_hpd_registers *hpd_regs) 818 { 819 struct bp_encoder_cap_info bp_cap_info = {0}; 820 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 821 enum bp_result result = BP_RESULT_OK; 822 823 enc110->base.funcs = &dce110_lnk_enc_funcs; 824 enc110->base.ctx = init_data->ctx; 825 enc110->base.id = init_data->encoder; 826 827 enc110->base.hpd_source = init_data->hpd_source; 828 enc110->base.connector = init_data->connector; 829 830 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 831 832 enc110->base.features = *enc_features; 833 834 enc110->base.transmitter = init_data->transmitter; 835 836 /* set the flag to indicate whether driver poll the I2C data pin 837 * while doing the DP sink detect 838 */ 839 840 /* if (dal_adapter_service_is_feature_supported(as, 841 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 842 enc110->base.features.flags.bits. 843 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 844 845 enc110->base.output_signals = 846 SIGNAL_TYPE_DVI_SINGLE_LINK | 847 SIGNAL_TYPE_DVI_DUAL_LINK | 848 SIGNAL_TYPE_LVDS | 849 SIGNAL_TYPE_DISPLAY_PORT | 850 SIGNAL_TYPE_DISPLAY_PORT_MST | 851 SIGNAL_TYPE_EDP | 852 SIGNAL_TYPE_HDMI_TYPE_A; 853 854 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 855 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 856 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 857 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 858 * Prefer DIG assignment is decided by board design. 859 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 860 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 861 * By this, adding DIGG should not hurt DCE 8.0. 862 * This will let DCE 8.1 share DCE 8.0 as much as possible 863 */ 864 865 enc110->link_regs = link_regs; 866 enc110->aux_regs = aux_regs; 867 enc110->hpd_regs = hpd_regs; 868 869 switch (enc110->base.transmitter) { 870 case TRANSMITTER_UNIPHY_A: 871 enc110->base.preferred_engine = ENGINE_ID_DIGA; 872 break; 873 case TRANSMITTER_UNIPHY_B: 874 enc110->base.preferred_engine = ENGINE_ID_DIGB; 875 break; 876 case TRANSMITTER_UNIPHY_C: 877 enc110->base.preferred_engine = ENGINE_ID_DIGC; 878 break; 879 case TRANSMITTER_UNIPHY_D: 880 enc110->base.preferred_engine = ENGINE_ID_DIGD; 881 break; 882 case TRANSMITTER_UNIPHY_E: 883 enc110->base.preferred_engine = ENGINE_ID_DIGE; 884 break; 885 case TRANSMITTER_UNIPHY_F: 886 enc110->base.preferred_engine = ENGINE_ID_DIGF; 887 break; 888 case TRANSMITTER_UNIPHY_G: 889 enc110->base.preferred_engine = ENGINE_ID_DIGG; 890 break; 891 default: 892 ASSERT_CRITICAL(false); 893 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 894 } 895 896 /* default to one to mirror Windows behavior */ 897 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 898 899 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 900 enc110->base.id, &bp_cap_info); 901 902 /* Override features with DCE-specific values */ 903 if (BP_RESULT_OK == result) { 904 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 905 bp_cap_info.DP_HBR2_EN; 906 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 907 bp_cap_info.DP_HBR3_EN; 908 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 909 } else { 910 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 911 __func__, 912 result); 913 } 914 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 915 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 916 } 917 } 918 919 bool dce110_link_encoder_validate_output_with_stream( 920 struct link_encoder *enc, 921 const struct dc_stream_state *stream) 922 { 923 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 924 bool is_valid; 925 926 switch (stream->signal) { 927 case SIGNAL_TYPE_DVI_SINGLE_LINK: 928 case SIGNAL_TYPE_DVI_DUAL_LINK: 929 is_valid = dce110_link_encoder_validate_dvi_output( 930 enc110, 931 stream->link->connector_signal, 932 stream->signal, 933 &stream->timing); 934 break; 935 case SIGNAL_TYPE_HDMI_TYPE_A: 936 is_valid = dce110_link_encoder_validate_hdmi_output( 937 enc110, 938 &stream->timing, 939 stream->phy_pix_clk); 940 break; 941 case SIGNAL_TYPE_DISPLAY_PORT: 942 case SIGNAL_TYPE_DISPLAY_PORT_MST: 943 is_valid = dce110_link_encoder_validate_dp_output( 944 enc110, &stream->timing); 945 break; 946 case SIGNAL_TYPE_EDP: 947 case SIGNAL_TYPE_LVDS: 948 is_valid = 949 (stream->timing. 950 pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; 951 break; 952 case SIGNAL_TYPE_VIRTUAL: 953 is_valid = true; 954 break; 955 default: 956 is_valid = false; 957 break; 958 } 959 960 return is_valid; 961 } 962 963 void dce110_link_encoder_hw_init( 964 struct link_encoder *enc) 965 { 966 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 967 struct bp_transmitter_control cntl = { 0 }; 968 enum bp_result result; 969 970 cntl.action = TRANSMITTER_CONTROL_INIT; 971 cntl.engine_id = ENGINE_ID_UNKNOWN; 972 cntl.transmitter = enc110->base.transmitter; 973 cntl.connector_obj_id = enc110->base.connector; 974 cntl.lanes_number = LANE_COUNT_FOUR; 975 cntl.coherent = false; 976 cntl.hpd_sel = enc110->base.hpd_source; 977 978 if (enc110->base.connector.id == CONNECTOR_ID_EDP) 979 cntl.signal = SIGNAL_TYPE_EDP; 980 981 result = link_transmitter_control(enc110, &cntl); 982 983 if (result != BP_RESULT_OK) { 984 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 985 __func__); 986 BREAK_TO_DEBUGGER(); 987 return; 988 } 989 990 if (enc110->base.connector.id == CONNECTOR_ID_LVDS) { 991 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS; 992 993 result = link_transmitter_control(enc110, &cntl); 994 995 ASSERT(result == BP_RESULT_OK); 996 997 } 998 aux_initialize(enc110); 999 1000 /* reinitialize HPD. 1001 * hpd_initialize() will pass DIG_FE id to HW context. 1002 * All other routine within HW context will use fe_engine_offset 1003 * as DIG_FE id even caller pass DIG_FE id. 1004 * So this routine must be called first. */ 1005 hpd_initialize(enc110); 1006 } 1007 1008 void dce110_link_encoder_destroy(struct link_encoder **enc) 1009 { 1010 kfree(TO_DCE110_LINK_ENC(*enc)); 1011 *enc = NULL; 1012 } 1013 1014 void dce110_link_encoder_setup( 1015 struct link_encoder *enc, 1016 enum signal_type signal) 1017 { 1018 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1019 1020 switch (signal) { 1021 case SIGNAL_TYPE_EDP: 1022 case SIGNAL_TYPE_DISPLAY_PORT: 1023 /* DP SST */ 1024 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); 1025 break; 1026 case SIGNAL_TYPE_LVDS: 1027 /* LVDS */ 1028 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); 1029 break; 1030 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1031 case SIGNAL_TYPE_DVI_DUAL_LINK: 1032 /* TMDS-DVI */ 1033 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); 1034 break; 1035 case SIGNAL_TYPE_HDMI_TYPE_A: 1036 /* TMDS-HDMI */ 1037 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); 1038 break; 1039 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1040 /* DP MST */ 1041 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); 1042 break; 1043 default: 1044 ASSERT_CRITICAL(false); 1045 /* invalid mode ! */ 1046 break; 1047 } 1048 1049 } 1050 1051 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1052 void dce110_link_encoder_enable_tmds_output( 1053 struct link_encoder *enc, 1054 enum clock_source_id clock_source, 1055 enum dc_color_depth color_depth, 1056 enum signal_type signal, 1057 uint32_t pixel_clock) 1058 { 1059 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1060 struct bp_transmitter_control cntl = { 0 }; 1061 enum bp_result result; 1062 1063 /* Enable the PHY */ 1064 cntl.connector_obj_id = enc110->base.connector; 1065 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1066 cntl.engine_id = enc->preferred_engine; 1067 cntl.transmitter = enc110->base.transmitter; 1068 cntl.pll_id = clock_source; 1069 cntl.signal = signal; 1070 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK) 1071 cntl.lanes_number = 8; 1072 else 1073 cntl.lanes_number = 4; 1074 1075 cntl.hpd_sel = enc110->base.hpd_source; 1076 1077 cntl.pixel_clock = pixel_clock; 1078 cntl.color_depth = color_depth; 1079 1080 result = link_transmitter_control(enc110, &cntl); 1081 1082 if (result != BP_RESULT_OK) { 1083 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1084 __func__); 1085 BREAK_TO_DEBUGGER(); 1086 } 1087 } 1088 1089 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1090 void dce110_link_encoder_enable_lvds_output( 1091 struct link_encoder *enc, 1092 enum clock_source_id clock_source, 1093 uint32_t pixel_clock) 1094 { 1095 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1096 struct bp_transmitter_control cntl = { 0 }; 1097 enum bp_result result; 1098 1099 /* Enable the PHY */ 1100 cntl.connector_obj_id = enc110->base.connector; 1101 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1102 cntl.engine_id = enc->preferred_engine; 1103 cntl.transmitter = enc110->base.transmitter; 1104 cntl.pll_id = clock_source; 1105 cntl.signal = SIGNAL_TYPE_LVDS; 1106 cntl.lanes_number = 4; 1107 1108 cntl.hpd_sel = enc110->base.hpd_source; 1109 1110 cntl.pixel_clock = pixel_clock; 1111 1112 result = link_transmitter_control(enc110, &cntl); 1113 1114 if (result != BP_RESULT_OK) { 1115 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1116 __func__); 1117 BREAK_TO_DEBUGGER(); 1118 } 1119 } 1120 1121 /* enables DP PHY output */ 1122 void dce110_link_encoder_enable_dp_output( 1123 struct link_encoder *enc, 1124 const struct dc_link_settings *link_settings, 1125 enum clock_source_id clock_source) 1126 { 1127 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1128 struct bp_transmitter_control cntl = { 0 }; 1129 enum bp_result result; 1130 1131 /* Enable the PHY */ 1132 1133 /* number_of_lanes is used for pixel clock adjust, 1134 * but it's not passed to asic_control. 1135 * We need to set number of lanes manually. 1136 */ 1137 configure_encoder(enc110, link_settings); 1138 cntl.connector_obj_id = enc110->base.connector; 1139 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1140 cntl.engine_id = enc->preferred_engine; 1141 cntl.transmitter = enc110->base.transmitter; 1142 cntl.pll_id = clock_source; 1143 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1144 cntl.lanes_number = link_settings->lane_count; 1145 cntl.hpd_sel = enc110->base.hpd_source; 1146 cntl.pixel_clock = link_settings->link_rate 1147 * LINK_RATE_REF_FREQ_IN_KHZ; 1148 /* TODO: check if undefined works */ 1149 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1150 1151 result = link_transmitter_control(enc110, &cntl); 1152 1153 if (result != BP_RESULT_OK) { 1154 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1155 __func__); 1156 BREAK_TO_DEBUGGER(); 1157 } 1158 } 1159 1160 /* enables DP PHY output in MST mode */ 1161 void dce110_link_encoder_enable_dp_mst_output( 1162 struct link_encoder *enc, 1163 const struct dc_link_settings *link_settings, 1164 enum clock_source_id clock_source) 1165 { 1166 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1167 struct bp_transmitter_control cntl = { 0 }; 1168 enum bp_result result; 1169 1170 /* Enable the PHY */ 1171 1172 /* number_of_lanes is used for pixel clock adjust, 1173 * but it's not passed to asic_control. 1174 * We need to set number of lanes manually. 1175 */ 1176 configure_encoder(enc110, link_settings); 1177 1178 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1179 cntl.engine_id = ENGINE_ID_UNKNOWN; 1180 cntl.transmitter = enc110->base.transmitter; 1181 cntl.pll_id = clock_source; 1182 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1183 cntl.lanes_number = link_settings->lane_count; 1184 cntl.hpd_sel = enc110->base.hpd_source; 1185 cntl.pixel_clock = link_settings->link_rate 1186 * LINK_RATE_REF_FREQ_IN_KHZ; 1187 /* TODO: check if undefined works */ 1188 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1189 1190 result = link_transmitter_control(enc110, &cntl); 1191 1192 if (result != BP_RESULT_OK) { 1193 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1194 __func__); 1195 BREAK_TO_DEBUGGER(); 1196 } 1197 } 1198 1199 #if defined(CONFIG_DRM_AMD_DC_SI) 1200 /* enables DP PHY output */ 1201 static void dce60_link_encoder_enable_dp_output( 1202 struct link_encoder *enc, 1203 const struct dc_link_settings *link_settings, 1204 enum clock_source_id clock_source) 1205 { 1206 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1207 struct bp_transmitter_control cntl = { 0 }; 1208 enum bp_result result; 1209 1210 /* Enable the PHY */ 1211 1212 /* number_of_lanes is used for pixel clock adjust, 1213 * but it's not passed to asic_control. 1214 * We need to set number of lanes manually. 1215 */ 1216 dce60_configure_encoder(enc110, link_settings); 1217 cntl.connector_obj_id = enc110->base.connector; 1218 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1219 cntl.engine_id = enc->preferred_engine; 1220 cntl.transmitter = enc110->base.transmitter; 1221 cntl.pll_id = clock_source; 1222 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1223 cntl.lanes_number = link_settings->lane_count; 1224 cntl.hpd_sel = enc110->base.hpd_source; 1225 cntl.pixel_clock = link_settings->link_rate 1226 * LINK_RATE_REF_FREQ_IN_KHZ; 1227 /* TODO: check if undefined works */ 1228 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1229 1230 result = link_transmitter_control(enc110, &cntl); 1231 1232 if (result != BP_RESULT_OK) { 1233 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1234 __func__); 1235 BREAK_TO_DEBUGGER(); 1236 } 1237 } 1238 1239 /* enables DP PHY output in MST mode */ 1240 static void dce60_link_encoder_enable_dp_mst_output( 1241 struct link_encoder *enc, 1242 const struct dc_link_settings *link_settings, 1243 enum clock_source_id clock_source) 1244 { 1245 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1246 struct bp_transmitter_control cntl = { 0 }; 1247 enum bp_result result; 1248 1249 /* Enable the PHY */ 1250 1251 /* number_of_lanes is used for pixel clock adjust, 1252 * but it's not passed to asic_control. 1253 * We need to set number of lanes manually. 1254 */ 1255 dce60_configure_encoder(enc110, link_settings); 1256 1257 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1258 cntl.engine_id = ENGINE_ID_UNKNOWN; 1259 cntl.transmitter = enc110->base.transmitter; 1260 cntl.pll_id = clock_source; 1261 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1262 cntl.lanes_number = link_settings->lane_count; 1263 cntl.hpd_sel = enc110->base.hpd_source; 1264 cntl.pixel_clock = link_settings->link_rate 1265 * LINK_RATE_REF_FREQ_IN_KHZ; 1266 /* TODO: check if undefined works */ 1267 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1268 1269 result = link_transmitter_control(enc110, &cntl); 1270 1271 if (result != BP_RESULT_OK) { 1272 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1273 __func__); 1274 BREAK_TO_DEBUGGER(); 1275 } 1276 } 1277 #endif 1278 1279 /* 1280 * @brief 1281 * Disable transmitter and its encoder 1282 */ 1283 void dce110_link_encoder_disable_output( 1284 struct link_encoder *enc, 1285 enum signal_type signal) 1286 { 1287 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1288 struct bp_transmitter_control cntl = { 0 }; 1289 enum bp_result result; 1290 1291 if (!dce110_is_dig_enabled(enc)) { 1292 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ 1293 return; 1294 } 1295 /* Power-down RX and disable GPU PHY should be paired. 1296 * Disabling PHY without powering down RX may cause 1297 * symbol lock loss, on which we will get DP Sink interrupt. */ 1298 1299 /* There is a case for the DP active dongles 1300 * where we want to disable the PHY but keep RX powered, 1301 * for those we need to ignore DP Sink interrupt 1302 * by checking lane count that has been set 1303 * on the last do_enable_output(). */ 1304 1305 /* disable transmitter */ 1306 cntl.action = TRANSMITTER_CONTROL_DISABLE; 1307 cntl.transmitter = enc110->base.transmitter; 1308 cntl.hpd_sel = enc110->base.hpd_source; 1309 cntl.signal = signal; 1310 cntl.connector_obj_id = enc110->base.connector; 1311 1312 result = link_transmitter_control(enc110, &cntl); 1313 1314 if (result != BP_RESULT_OK) { 1315 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1316 __func__); 1317 BREAK_TO_DEBUGGER(); 1318 return; 1319 } 1320 1321 /* disable encoder */ 1322 if (dc_is_dp_signal(signal)) 1323 link_encoder_disable(enc110); 1324 } 1325 1326 void dce110_link_encoder_dp_set_lane_settings( 1327 struct link_encoder *enc, 1328 const struct link_training_settings *link_settings) 1329 { 1330 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1331 union dpcd_training_lane_set training_lane_set = { { 0 } }; 1332 int32_t lane = 0; 1333 struct bp_transmitter_control cntl = { 0 }; 1334 1335 if (!link_settings) { 1336 BREAK_TO_DEBUGGER(); 1337 return; 1338 } 1339 1340 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1341 cntl.transmitter = enc110->base.transmitter; 1342 cntl.connector_obj_id = enc110->base.connector; 1343 cntl.lanes_number = link_settings->link_settings.lane_count; 1344 cntl.hpd_sel = enc110->base.hpd_source; 1345 cntl.pixel_clock = link_settings->link_settings.link_rate * 1346 LINK_RATE_REF_FREQ_IN_KHZ; 1347 1348 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { 1349 /* translate lane settings */ 1350 1351 training_lane_set.bits.VOLTAGE_SWING_SET = 1352 link_settings->lane_settings[lane].VOLTAGE_SWING; 1353 training_lane_set.bits.PRE_EMPHASIS_SET = 1354 link_settings->lane_settings[lane].PRE_EMPHASIS; 1355 1356 /* post cursor 2 setting only applies to HBR2 link rate */ 1357 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { 1358 /* this is passed to VBIOS 1359 * to program post cursor 2 level */ 1360 1361 training_lane_set.bits.POST_CURSOR2_SET = 1362 link_settings->lane_settings[lane].POST_CURSOR2; 1363 } 1364 1365 cntl.lane_select = lane; 1366 cntl.lane_settings = training_lane_set.raw; 1367 1368 /* call VBIOS table to set voltage swing and pre-emphasis */ 1369 link_transmitter_control(enc110, &cntl); 1370 } 1371 } 1372 1373 /* set DP PHY test and training patterns */ 1374 void dce110_link_encoder_dp_set_phy_pattern( 1375 struct link_encoder *enc, 1376 const struct encoder_set_dp_phy_pattern_param *param) 1377 { 1378 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1379 1380 switch (param->dp_phy_pattern) { 1381 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1382 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1383 break; 1384 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1385 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1386 break; 1387 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1388 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1389 break; 1390 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1391 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1392 break; 1393 case DP_TEST_PATTERN_D102: 1394 set_dp_phy_pattern_d102(enc110); 1395 break; 1396 case DP_TEST_PATTERN_SYMBOL_ERROR: 1397 set_dp_phy_pattern_symbol_error(enc110); 1398 break; 1399 case DP_TEST_PATTERN_PRBS7: 1400 set_dp_phy_pattern_prbs7(enc110); 1401 break; 1402 case DP_TEST_PATTERN_80BIT_CUSTOM: 1403 set_dp_phy_pattern_80bit_custom( 1404 enc110, param->custom_pattern); 1405 break; 1406 case DP_TEST_PATTERN_CP2520_1: 1407 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1408 break; 1409 case DP_TEST_PATTERN_CP2520_2: 1410 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1411 break; 1412 case DP_TEST_PATTERN_CP2520_3: 1413 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1414 break; 1415 case DP_TEST_PATTERN_VIDEO_MODE: { 1416 set_dp_phy_pattern_passthrough_mode( 1417 enc110, param->dp_panel_mode); 1418 break; 1419 } 1420 1421 default: 1422 /* invalid phy pattern */ 1423 ASSERT_CRITICAL(false); 1424 break; 1425 } 1426 } 1427 1428 #if defined(CONFIG_DRM_AMD_DC_SI) 1429 /* set DP PHY test and training patterns */ 1430 static void dce60_link_encoder_dp_set_phy_pattern( 1431 struct link_encoder *enc, 1432 const struct encoder_set_dp_phy_pattern_param *param) 1433 { 1434 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1435 1436 switch (param->dp_phy_pattern) { 1437 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1438 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1439 break; 1440 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1441 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1442 break; 1443 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1444 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1445 break; 1446 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1447 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1448 break; 1449 case DP_TEST_PATTERN_D102: 1450 set_dp_phy_pattern_d102(enc110); 1451 break; 1452 case DP_TEST_PATTERN_SYMBOL_ERROR: 1453 set_dp_phy_pattern_symbol_error(enc110); 1454 break; 1455 case DP_TEST_PATTERN_PRBS7: 1456 set_dp_phy_pattern_prbs7(enc110); 1457 break; 1458 case DP_TEST_PATTERN_80BIT_CUSTOM: 1459 set_dp_phy_pattern_80bit_custom( 1460 enc110, param->custom_pattern); 1461 break; 1462 case DP_TEST_PATTERN_CP2520_1: 1463 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1464 break; 1465 case DP_TEST_PATTERN_CP2520_2: 1466 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1467 break; 1468 case DP_TEST_PATTERN_CP2520_3: 1469 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1470 break; 1471 case DP_TEST_PATTERN_VIDEO_MODE: { 1472 dce60_set_dp_phy_pattern_passthrough_mode( 1473 enc110, param->dp_panel_mode); 1474 break; 1475 } 1476 1477 default: 1478 /* invalid phy pattern */ 1479 ASSERT_CRITICAL(false); 1480 break; 1481 } 1482 } 1483 #endif 1484 1485 static void fill_stream_allocation_row_info( 1486 const struct link_mst_stream_allocation *stream_allocation, 1487 uint32_t *src, 1488 uint32_t *slots) 1489 { 1490 const struct stream_encoder *stream_enc = stream_allocation->stream_enc; 1491 1492 if (stream_enc) { 1493 *src = stream_enc->id; 1494 *slots = stream_allocation->slot_count; 1495 } else { 1496 *src = 0; 1497 *slots = 0; 1498 } 1499 } 1500 1501 /* programs DP MST VC payload allocation */ 1502 void dce110_link_encoder_update_mst_stream_allocation_table( 1503 struct link_encoder *enc, 1504 const struct link_mst_stream_allocation_table *table) 1505 { 1506 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1507 uint32_t value1 = 0; 1508 uint32_t value2 = 0; 1509 uint32_t slots = 0; 1510 uint32_t src = 0; 1511 uint32_t retries = 0; 1512 1513 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/ 1514 1515 /* --- Set MSE Stream Attribute - 1516 * Setup VC Payload Table on Tx Side, 1517 * Issue allocation change trigger 1518 * to commit payload on both tx and rx side */ 1519 1520 /* we should clean-up table each time */ 1521 1522 if (table->stream_count >= 1) { 1523 fill_stream_allocation_row_info( 1524 &table->stream_allocations[0], 1525 &src, 1526 &slots); 1527 } else { 1528 src = 0; 1529 slots = 0; 1530 } 1531 1532 REG_UPDATE_2(DP_MSE_SAT0, 1533 DP_MSE_SAT_SRC0, src, 1534 DP_MSE_SAT_SLOT_COUNT0, slots); 1535 1536 if (table->stream_count >= 2) { 1537 fill_stream_allocation_row_info( 1538 &table->stream_allocations[1], 1539 &src, 1540 &slots); 1541 } else { 1542 src = 0; 1543 slots = 0; 1544 } 1545 1546 REG_UPDATE_2(DP_MSE_SAT0, 1547 DP_MSE_SAT_SRC1, src, 1548 DP_MSE_SAT_SLOT_COUNT1, slots); 1549 1550 if (table->stream_count >= 3) { 1551 fill_stream_allocation_row_info( 1552 &table->stream_allocations[2], 1553 &src, 1554 &slots); 1555 } else { 1556 src = 0; 1557 slots = 0; 1558 } 1559 1560 REG_UPDATE_2(DP_MSE_SAT1, 1561 DP_MSE_SAT_SRC2, src, 1562 DP_MSE_SAT_SLOT_COUNT2, slots); 1563 1564 if (table->stream_count >= 4) { 1565 fill_stream_allocation_row_info( 1566 &table->stream_allocations[3], 1567 &src, 1568 &slots); 1569 } else { 1570 src = 0; 1571 slots = 0; 1572 } 1573 1574 REG_UPDATE_2(DP_MSE_SAT1, 1575 DP_MSE_SAT_SRC3, src, 1576 DP_MSE_SAT_SLOT_COUNT3, slots); 1577 1578 /* --- wait for transaction finish */ 1579 1580 /* send allocation change trigger (ACT) ? 1581 * this step first sends the ACT, 1582 * then double buffers the SAT into the hardware 1583 * making the new allocation active on the DP MST mode link */ 1584 1585 1586 /* DP_MSE_SAT_UPDATE: 1587 * 0 - No Action 1588 * 1 - Update SAT with trigger 1589 * 2 - Update SAT without trigger */ 1590 1591 REG_UPDATE(DP_MSE_SAT_UPDATE, 1592 DP_MSE_SAT_UPDATE, 1); 1593 1594 /* wait for update to complete 1595 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0) 1596 * then wait for the transmission 1597 * of at least 16 MTP headers on immediate local link. 1598 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0 1599 * a value of 1 indicates that DP MST mode 1600 * is in the 16 MTP keepout region after a VC has been added. 1601 * MST stream bandwidth (VC rate) can be configured 1602 * after this bit is cleared */ 1603 1604 do { 1605 udelay(10); 1606 1607 REG_READ(DP_MSE_SAT_UPDATE); 1608 1609 REG_GET(DP_MSE_SAT_UPDATE, 1610 DP_MSE_SAT_UPDATE, &value1); 1611 1612 REG_GET(DP_MSE_SAT_UPDATE, 1613 DP_MSE_16_MTP_KEEPOUT, &value2); 1614 1615 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */ 1616 if (!value1 && !value2) 1617 break; 1618 ++retries; 1619 } while (retries < DP_MST_UPDATE_MAX_RETRY); 1620 } 1621 1622 void dce110_link_encoder_connect_dig_be_to_fe( 1623 struct link_encoder *enc, 1624 enum engine_id engine, 1625 bool connect) 1626 { 1627 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1628 uint32_t field; 1629 1630 if (engine != ENGINE_ID_UNKNOWN) { 1631 1632 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); 1633 1634 if (connect) 1635 field |= get_frontend_source(engine); 1636 else 1637 field &= ~get_frontend_source(engine); 1638 1639 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); 1640 } 1641 } 1642 1643 void dce110_link_encoder_enable_hpd(struct link_encoder *enc) 1644 { 1645 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1646 struct dc_context *ctx = enc110->base.ctx; 1647 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1648 uint32_t hpd_enable = 0; 1649 uint32_t value = dm_read_reg(ctx, addr); 1650 1651 get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN); 1652 1653 if (hpd_enable == 0) 1654 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); 1655 } 1656 1657 void dce110_link_encoder_disable_hpd(struct link_encoder *enc) 1658 { 1659 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1660 struct dc_context *ctx = enc110->base.ctx; 1661 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1662 uint32_t value = dm_read_reg(ctx, addr); 1663 1664 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); 1665 } 1666 1667 void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc, 1668 struct dc_link_settings *link_settings) 1669 { 1670 /* Set Default link settings */ 1671 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, 1672 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0}; 1673 1674 /* Higher link settings based on feature supported */ 1675 if (enc->features.flags.bits.IS_HBR2_CAPABLE) 1676 max_link_cap.link_rate = LINK_RATE_HIGH2; 1677 1678 if (enc->features.flags.bits.IS_HBR3_CAPABLE) 1679 max_link_cap.link_rate = LINK_RATE_HIGH3; 1680 1681 *link_settings = max_link_cap; 1682 } 1683 1684 #if defined(CONFIG_DRM_AMD_DC_SI) 1685 static const struct link_encoder_funcs dce60_lnk_enc_funcs = { 1686 .validate_output_with_stream = 1687 dce110_link_encoder_validate_output_with_stream, 1688 .hw_init = dce110_link_encoder_hw_init, 1689 .setup = dce110_link_encoder_setup, 1690 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 1691 .enable_dp_output = dce60_link_encoder_enable_dp_output, 1692 .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, 1693 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 1694 .disable_output = dce110_link_encoder_disable_output, 1695 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 1696 .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, 1697 .update_mst_stream_allocation_table = 1698 dce110_link_encoder_update_mst_stream_allocation_table, 1699 .psr_program_dp_dphy_fast_training = 1700 dce110_psr_program_dp_dphy_fast_training, 1701 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 1702 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 1703 .enable_hpd = dce110_link_encoder_enable_hpd, 1704 .disable_hpd = dce110_link_encoder_disable_hpd, 1705 .is_dig_enabled = dce110_is_dig_enabled, 1706 .destroy = dce110_link_encoder_destroy, 1707 .get_max_link_cap = dce110_link_encoder_get_max_link_cap, 1708 .get_dig_frontend = dce110_get_dig_frontend 1709 }; 1710 1711 void dce60_link_encoder_construct( 1712 struct dce110_link_encoder *enc110, 1713 const struct encoder_init_data *init_data, 1714 const struct encoder_feature_support *enc_features, 1715 const struct dce110_link_enc_registers *link_regs, 1716 const struct dce110_link_enc_aux_registers *aux_regs, 1717 const struct dce110_link_enc_hpd_registers *hpd_regs) 1718 { 1719 struct bp_encoder_cap_info bp_cap_info = {0}; 1720 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 1721 enum bp_result result = BP_RESULT_OK; 1722 1723 enc110->base.funcs = &dce60_lnk_enc_funcs; 1724 enc110->base.ctx = init_data->ctx; 1725 enc110->base.id = init_data->encoder; 1726 1727 enc110->base.hpd_source = init_data->hpd_source; 1728 enc110->base.connector = init_data->connector; 1729 1730 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1731 1732 enc110->base.features = *enc_features; 1733 1734 enc110->base.transmitter = init_data->transmitter; 1735 1736 /* set the flag to indicate whether driver poll the I2C data pin 1737 * while doing the DP sink detect 1738 */ 1739 1740 /* if (dal_adapter_service_is_feature_supported(as, 1741 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 1742 enc110->base.features.flags.bits. 1743 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 1744 1745 enc110->base.output_signals = 1746 SIGNAL_TYPE_DVI_SINGLE_LINK | 1747 SIGNAL_TYPE_DVI_DUAL_LINK | 1748 SIGNAL_TYPE_LVDS | 1749 SIGNAL_TYPE_DISPLAY_PORT | 1750 SIGNAL_TYPE_DISPLAY_PORT_MST | 1751 SIGNAL_TYPE_EDP | 1752 SIGNAL_TYPE_HDMI_TYPE_A; 1753 1754 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 1755 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 1756 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 1757 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 1758 * Prefer DIG assignment is decided by board design. 1759 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 1760 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 1761 * By this, adding DIGG should not hurt DCE 8.0. 1762 * This will let DCE 8.1 share DCE 8.0 as much as possible 1763 */ 1764 1765 enc110->link_regs = link_regs; 1766 enc110->aux_regs = aux_regs; 1767 enc110->hpd_regs = hpd_regs; 1768 1769 switch (enc110->base.transmitter) { 1770 case TRANSMITTER_UNIPHY_A: 1771 enc110->base.preferred_engine = ENGINE_ID_DIGA; 1772 break; 1773 case TRANSMITTER_UNIPHY_B: 1774 enc110->base.preferred_engine = ENGINE_ID_DIGB; 1775 break; 1776 case TRANSMITTER_UNIPHY_C: 1777 enc110->base.preferred_engine = ENGINE_ID_DIGC; 1778 break; 1779 case TRANSMITTER_UNIPHY_D: 1780 enc110->base.preferred_engine = ENGINE_ID_DIGD; 1781 break; 1782 case TRANSMITTER_UNIPHY_E: 1783 enc110->base.preferred_engine = ENGINE_ID_DIGE; 1784 break; 1785 case TRANSMITTER_UNIPHY_F: 1786 enc110->base.preferred_engine = ENGINE_ID_DIGF; 1787 break; 1788 case TRANSMITTER_UNIPHY_G: 1789 enc110->base.preferred_engine = ENGINE_ID_DIGG; 1790 break; 1791 default: 1792 ASSERT_CRITICAL(false); 1793 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1794 } 1795 1796 /* default to one to mirror Windows behavior */ 1797 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 1798 1799 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 1800 enc110->base.id, &bp_cap_info); 1801 1802 /* Override features with DCE-specific values */ 1803 if (BP_RESULT_OK == result) { 1804 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 1805 bp_cap_info.DP_HBR2_EN; 1806 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 1807 bp_cap_info.DP_HBR3_EN; 1808 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 1809 } else { 1810 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 1811 __func__, 1812 result); 1813 } 1814 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 1815 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 1816 } 1817 } 1818 #endif 1819