1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 28 #include "core_types.h" 29 #include "link_encoder.h" 30 #include "dce_link_encoder.h" 31 #include "stream_encoder.h" 32 #include "i2caux_interface.h" 33 #include "dc_bios_types.h" 34 35 #include "gpio_service_interface.h" 36 37 #include "dce/dce_11_0_d.h" 38 #include "dce/dce_11_0_sh_mask.h" 39 #include "dce/dce_11_0_enum.h" 40 41 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 42 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa 43 #endif 44 45 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 46 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L 47 #endif 48 49 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 50 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L 51 #endif 52 53 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 54 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c 55 #endif 56 57 #define CTX \ 58 enc110->base.ctx 59 60 #define REG(reg)\ 61 (enc110->link_regs->reg) 62 63 #define AUX_REG(reg)\ 64 (enc110->aux_regs->reg) 65 66 #define HPD_REG(reg)\ 67 (enc110->hpd_regs->reg) 68 69 #define DEFAULT_AUX_MAX_DATA_SIZE 16 70 #define AUX_MAX_DEFER_WRITE_RETRY 20 71 /* 72 * @brief 73 * Trigger Source Select 74 * ASIC-dependent, actual values for register programming 75 */ 76 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0 77 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1 78 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2 79 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4 80 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08 81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10 82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 84 85 /* all values are in milliseconds */ 86 /* For eDP, after power-up/power/down, 87 * 300/500 msec max. delay from LCDVCC to black video generation */ 88 #define PANEL_POWER_UP_TIMEOUT 300 89 #define PANEL_POWER_DOWN_TIMEOUT 500 90 #define HPD_CHECK_INTERVAL 10 91 92 /* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */ 93 #define TMDS_MIN_PIXEL_CLOCK 25000 94 /* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */ 95 #define TMDS_MAX_PIXEL_CLOCK 165000 96 /* For current ASICs pixel clock - 600MHz */ 97 #define MAX_ENCODER_CLOCK 600000 98 99 enum { 100 DP_MST_UPDATE_MAX_RETRY = 50 101 }; 102 103 #define DIG_REG(reg)\ 104 (reg + enc110->offsets.dig) 105 106 #define DP_REG(reg)\ 107 (reg + enc110->offsets.dp) 108 109 static const struct link_encoder_funcs dce110_lnk_enc_funcs = { 110 .validate_output_with_stream = 111 dce110_link_encoder_validate_output_with_stream, 112 .hw_init = dce110_link_encoder_hw_init, 113 .setup = dce110_link_encoder_setup, 114 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 115 .enable_dp_output = dce110_link_encoder_enable_dp_output, 116 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, 117 .disable_output = dce110_link_encoder_disable_output, 118 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 119 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, 120 .update_mst_stream_allocation_table = 121 dce110_link_encoder_update_mst_stream_allocation_table, 122 .psr_program_dp_dphy_fast_training = 123 dce110_psr_program_dp_dphy_fast_training, 124 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 125 .backlight_control = dce110_link_encoder_edp_backlight_control, 126 .power_control = dce110_link_encoder_edp_power_control, 127 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 128 .enable_hpd = dce110_link_encoder_enable_hpd, 129 .disable_hpd = dce110_link_encoder_disable_hpd, 130 .destroy = dce110_link_encoder_destroy 131 }; 132 133 static enum bp_result link_transmitter_control( 134 struct dce110_link_encoder *enc110, 135 struct bp_transmitter_control *cntl) 136 { 137 enum bp_result result; 138 struct dc_bios *bp = enc110->base.ctx->dc_bios; 139 140 result = bp->funcs->transmitter_control(bp, cntl); 141 142 return result; 143 } 144 145 static void enable_phy_bypass_mode( 146 struct dce110_link_encoder *enc110, 147 bool enable) 148 { 149 /* This register resides in DP back end block; 150 * transmitter is used for the offset */ 151 152 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); 153 154 } 155 156 static void disable_prbs_symbols( 157 struct dce110_link_encoder *enc110, 158 bool disable) 159 { 160 /* This register resides in DP back end block; 161 * transmitter is used for the offset */ 162 163 REG_UPDATE_4(DP_DPHY_CNTL, 164 DPHY_ATEST_SEL_LANE0, disable, 165 DPHY_ATEST_SEL_LANE1, disable, 166 DPHY_ATEST_SEL_LANE2, disable, 167 DPHY_ATEST_SEL_LANE3, disable); 168 } 169 170 static void disable_prbs_mode( 171 struct dce110_link_encoder *enc110) 172 { 173 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); 174 } 175 176 static void program_pattern_symbols( 177 struct dce110_link_encoder *enc110, 178 uint16_t pattern_symbols[8]) 179 { 180 /* This register resides in DP back end block; 181 * transmitter is used for the offset */ 182 183 REG_SET_3(DP_DPHY_SYM0, 0, 184 DPHY_SYM1, pattern_symbols[0], 185 DPHY_SYM2, pattern_symbols[1], 186 DPHY_SYM3, pattern_symbols[2]); 187 188 /* This register resides in DP back end block; 189 * transmitter is used for the offset */ 190 191 REG_SET_3(DP_DPHY_SYM1, 0, 192 DPHY_SYM4, pattern_symbols[3], 193 DPHY_SYM5, pattern_symbols[4], 194 DPHY_SYM6, pattern_symbols[5]); 195 196 /* This register resides in DP back end block; 197 * transmitter is used for the offset */ 198 199 REG_SET_2(DP_DPHY_SYM2, 0, 200 DPHY_SYM7, pattern_symbols[6], 201 DPHY_SYM8, pattern_symbols[7]); 202 } 203 204 static void set_dp_phy_pattern_d102( 205 struct dce110_link_encoder *enc110) 206 { 207 /* Disable PHY Bypass mode to setup the test pattern */ 208 enable_phy_bypass_mode(enc110, false); 209 210 /* For 10-bit PRBS or debug symbols 211 * please use the following sequence: */ 212 213 /* Enable debug symbols on the lanes */ 214 215 disable_prbs_symbols(enc110, true); 216 217 /* Disable PRBS mode */ 218 disable_prbs_mode(enc110); 219 220 /* Program debug symbols to be output */ 221 { 222 uint16_t pattern_symbols[8] = { 223 0x2AA, 0x2AA, 0x2AA, 0x2AA, 224 0x2AA, 0x2AA, 0x2AA, 0x2AA 225 }; 226 227 program_pattern_symbols(enc110, pattern_symbols); 228 } 229 230 /* Enable phy bypass mode to enable the test pattern */ 231 232 enable_phy_bypass_mode(enc110, true); 233 } 234 235 static void set_link_training_complete( 236 struct dce110_link_encoder *enc110, 237 bool complete) 238 { 239 /* This register resides in DP back end block; 240 * transmitter is used for the offset */ 241 242 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); 243 244 } 245 246 void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 247 struct link_encoder *enc, 248 uint32_t index) 249 { 250 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 251 /* Write Training Pattern */ 252 253 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); 254 255 /* Set HW Register Training Complete to false */ 256 257 set_link_training_complete(enc110, false); 258 259 /* Disable PHY Bypass mode to output Training Pattern */ 260 261 enable_phy_bypass_mode(enc110, false); 262 263 /* Disable PRBS mode */ 264 disable_prbs_mode(enc110); 265 } 266 267 static void setup_panel_mode( 268 struct dce110_link_encoder *enc110, 269 enum dp_panel_mode panel_mode) 270 { 271 uint32_t value; 272 273 ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); 274 value = REG_READ(DP_DPHY_INTERNAL_CTRL); 275 276 switch (panel_mode) { 277 case DP_PANEL_MODE_EDP: 278 value = 0x1; 279 break; 280 case DP_PANEL_MODE_SPECIAL: 281 value = 0x11; 282 break; 283 default: 284 value = 0x0; 285 break; 286 } 287 288 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); 289 } 290 291 static void set_dp_phy_pattern_symbol_error( 292 struct dce110_link_encoder *enc110) 293 { 294 /* Disable PHY Bypass mode to setup the test pattern */ 295 enable_phy_bypass_mode(enc110, false); 296 297 /* program correct panel mode*/ 298 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 299 300 /* A PRBS23 pattern is used for most DP electrical measurements. */ 301 302 /* Enable PRBS symbols on the lanes */ 303 disable_prbs_symbols(enc110, false); 304 305 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */ 306 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 307 DPHY_PRBS_SEL, 1, 308 DPHY_PRBS_EN, 1); 309 310 /* Enable phy bypass mode to enable the test pattern */ 311 enable_phy_bypass_mode(enc110, true); 312 } 313 314 static void set_dp_phy_pattern_prbs7( 315 struct dce110_link_encoder *enc110) 316 { 317 /* Disable PHY Bypass mode to setup the test pattern */ 318 enable_phy_bypass_mode(enc110, false); 319 320 /* A PRBS7 pattern is used for most DP electrical measurements. */ 321 322 /* Enable PRBS symbols on the lanes */ 323 disable_prbs_symbols(enc110, false); 324 325 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */ 326 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 327 DPHY_PRBS_SEL, 0, 328 DPHY_PRBS_EN, 1); 329 330 /* Enable phy bypass mode to enable the test pattern */ 331 enable_phy_bypass_mode(enc110, true); 332 } 333 334 static void set_dp_phy_pattern_80bit_custom( 335 struct dce110_link_encoder *enc110, 336 const uint8_t *pattern) 337 { 338 /* Disable PHY Bypass mode to setup the test pattern */ 339 enable_phy_bypass_mode(enc110, false); 340 341 /* Enable debug symbols on the lanes */ 342 343 disable_prbs_symbols(enc110, true); 344 345 /* Enable PHY bypass mode to enable the test pattern */ 346 /* TODO is it really needed ? */ 347 348 enable_phy_bypass_mode(enc110, true); 349 350 /* Program 80 bit custom pattern */ 351 { 352 uint16_t pattern_symbols[8]; 353 354 pattern_symbols[0] = 355 ((pattern[1] & 0x03) << 8) | pattern[0]; 356 pattern_symbols[1] = 357 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f); 358 pattern_symbols[2] = 359 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f); 360 pattern_symbols[3] = 361 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03); 362 pattern_symbols[4] = 363 ((pattern[6] & 0x03) << 8) | pattern[5]; 364 pattern_symbols[5] = 365 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f); 366 pattern_symbols[6] = 367 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f); 368 pattern_symbols[7] = 369 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03); 370 371 program_pattern_symbols(enc110, pattern_symbols); 372 } 373 374 /* Enable phy bypass mode to enable the test pattern */ 375 376 enable_phy_bypass_mode(enc110, true); 377 } 378 379 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( 380 struct dce110_link_encoder *enc110, 381 unsigned int cp2520_pattern) 382 { 383 384 /* previously there is a register DP_HBR2_EYE_PATTERN 385 * that is enabled to get the pattern. 386 * But it does not work with the latest spec change, 387 * so we are programming the following registers manually. 388 * 389 * The following settings have been confirmed 390 * by Nick Chorney and Sandra Liu */ 391 392 /* Disable PHY Bypass mode to setup the test pattern */ 393 394 enable_phy_bypass_mode(enc110, false); 395 396 /* Setup DIG encoder in DP SST mode */ 397 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 398 399 /* ensure normal panel mode. */ 400 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 401 402 /* no vbid after BS (SR) 403 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 404 * 11000260 / 11000104 / 110000FC */ 405 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 406 DP_IDLE_BS_INTERVAL, 0xFC, 407 DP_VBID_DISABLE, 1, 408 DP_VID_ENHANCED_FRAME_MODE, 1); 409 410 /* swap every BS with SR */ 411 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); 412 413 /* select cp2520 patterns */ 414 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 415 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 416 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 417 else 418 /* pre-DCE11 can only generate CP2520 pattern 2 */ 419 ASSERT(cp2520_pattern == 2); 420 421 /* set link training complete */ 422 set_link_training_complete(enc110, true); 423 424 /* disable video stream */ 425 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 426 427 /* Disable PHY Bypass mode to setup the test pattern */ 428 enable_phy_bypass_mode(enc110, false); 429 } 430 431 static void set_dp_phy_pattern_passthrough_mode( 432 struct dce110_link_encoder *enc110, 433 enum dp_panel_mode panel_mode) 434 { 435 /* program correct panel mode */ 436 setup_panel_mode(enc110, panel_mode); 437 438 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT 439 * in case we were doing HBR2 compliance pattern before 440 */ 441 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 442 DP_IDLE_BS_INTERVAL, 0x2000, 443 DP_VBID_DISABLE, 0, 444 DP_VID_ENHANCED_FRAME_MODE, 1); 445 446 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); 447 448 /* set link training complete */ 449 set_link_training_complete(enc110, true); 450 451 /* Disable PHY Bypass mode to setup the test pattern */ 452 enable_phy_bypass_mode(enc110, false); 453 454 /* Disable PRBS mode */ 455 disable_prbs_mode(enc110); 456 } 457 458 /* return value is bit-vector */ 459 static uint8_t get_frontend_source( 460 enum engine_id engine) 461 { 462 switch (engine) { 463 case ENGINE_ID_DIGA: 464 return DCE110_DIG_FE_SOURCE_SELECT_DIGA; 465 case ENGINE_ID_DIGB: 466 return DCE110_DIG_FE_SOURCE_SELECT_DIGB; 467 case ENGINE_ID_DIGC: 468 return DCE110_DIG_FE_SOURCE_SELECT_DIGC; 469 case ENGINE_ID_DIGD: 470 return DCE110_DIG_FE_SOURCE_SELECT_DIGD; 471 case ENGINE_ID_DIGE: 472 return DCE110_DIG_FE_SOURCE_SELECT_DIGE; 473 case ENGINE_ID_DIGF: 474 return DCE110_DIG_FE_SOURCE_SELECT_DIGF; 475 case ENGINE_ID_DIGG: 476 return DCE110_DIG_FE_SOURCE_SELECT_DIGG; 477 default: 478 ASSERT_CRITICAL(false); 479 return DCE110_DIG_FE_SOURCE_SELECT_INVALID; 480 } 481 } 482 483 static void configure_encoder( 484 struct dce110_link_encoder *enc110, 485 const struct dc_link_settings *link_settings) 486 { 487 /* set number of lanes */ 488 489 REG_SET(DP_CONFIG, 0, 490 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 491 492 /* setup scrambler */ 493 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); 494 } 495 496 static bool is_panel_powered_on(struct dce110_link_encoder *enc110) 497 { 498 bool ret; 499 uint32_t value; 500 501 REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value); 502 ret = value; 503 504 return ret == 1; 505 } 506 507 508 /* TODO duplicate of dc_link.c version */ 509 static struct gpio *get_hpd_gpio(const struct link_encoder *enc) 510 { 511 enum bp_result bp_result; 512 struct dc_bios *dcb = enc->ctx->dc_bios; 513 struct graphics_object_hpd_info hpd_info; 514 struct gpio_pin_info pin_info; 515 516 if (dcb->funcs->get_hpd_info(dcb, enc->connector, &hpd_info) != BP_RESULT_OK) 517 return NULL; 518 519 bp_result = dcb->funcs->get_gpio_pin_info(dcb, 520 hpd_info.hpd_int_gpio_uid, &pin_info); 521 522 if (bp_result != BP_RESULT_OK) { 523 ASSERT(bp_result == BP_RESULT_NORECORD); 524 return NULL; 525 } 526 527 return dal_gpio_service_create_irq( 528 enc->ctx->gpio_service, 529 pin_info.offset, 530 pin_info.mask); 531 } 532 533 /* 534 * @brief 535 * eDP only. 536 */ 537 static void link_encoder_edp_wait_for_hpd_ready( 538 struct dce110_link_encoder *enc110, 539 bool power_up) 540 { 541 struct dc_context *ctx = enc110->base.ctx; 542 struct graphics_object_id connector = enc110->base.connector; 543 struct gpio *hpd; 544 bool edp_hpd_high = false; 545 uint32_t time_elapsed = 0; 546 uint32_t timeout = power_up ? 547 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 548 549 if (dal_graphics_object_id_get_connector_id(connector) != 550 CONNECTOR_ID_EDP) { 551 BREAK_TO_DEBUGGER(); 552 return; 553 } 554 555 if (!power_up) 556 /* from KV, we will not HPD low after turning off VCC - 557 * instead, we will check the SW timer in power_up(). */ 558 return; 559 560 /* when we power on/off the eDP panel, 561 * we need to wait until SENSE bit is high/low */ 562 563 /* obtain HPD */ 564 /* TODO what to do with this? */ 565 hpd = get_hpd_gpio(&enc110->base); 566 567 if (!hpd) { 568 BREAK_TO_DEBUGGER(); 569 return; 570 } 571 572 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 573 574 /* wait until timeout or panel detected */ 575 576 do { 577 uint32_t detected = 0; 578 579 dal_gpio_get_value(hpd, &detected); 580 581 if (!(detected ^ power_up)) { 582 edp_hpd_high = true; 583 break; 584 } 585 586 msleep(HPD_CHECK_INTERVAL); 587 588 time_elapsed += HPD_CHECK_INTERVAL; 589 } while (time_elapsed < timeout); 590 591 dal_gpio_close(hpd); 592 593 dal_gpio_destroy_irq(&hpd); 594 595 if (false == edp_hpd_high) { 596 dm_logger_write(ctx->logger, LOG_ERROR, 597 "%s: wait timed out!\n", __func__); 598 } 599 } 600 601 /* 602 * @brief 603 * eDP only. Control the power of the eDP panel. 604 */ 605 void dce110_link_encoder_edp_power_control( 606 struct link_encoder *enc, 607 bool power_up) 608 { 609 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 610 struct dc_context *ctx = enc110->base.ctx; 611 struct bp_transmitter_control cntl = { 0 }; 612 enum bp_result bp_result; 613 614 if (dal_graphics_object_id_get_connector_id(enc110->base.connector) != 615 CONNECTOR_ID_EDP) { 616 BREAK_TO_DEBUGGER(); 617 return; 618 } 619 620 if ((power_up && !is_panel_powered_on(enc110)) || 621 (!power_up && is_panel_powered_on(enc110))) { 622 623 /* Send VBIOS command to prompt eDP panel power */ 624 625 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 626 "%s: Panel Power action: %s\n", 627 __func__, (power_up ? "On":"Off")); 628 629 cntl.action = power_up ? 630 TRANSMITTER_CONTROL_POWER_ON : 631 TRANSMITTER_CONTROL_POWER_OFF; 632 cntl.transmitter = enc110->base.transmitter; 633 cntl.connector_obj_id = enc110->base.connector; 634 cntl.coherent = false; 635 cntl.lanes_number = LANE_COUNT_FOUR; 636 cntl.hpd_sel = enc110->base.hpd_source; 637 638 bp_result = link_transmitter_control(enc110, &cntl); 639 640 if (BP_RESULT_OK != bp_result) { 641 642 dm_logger_write(ctx->logger, LOG_ERROR, 643 "%s: Panel Power bp_result: %d\n", 644 __func__, bp_result); 645 } 646 } else { 647 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 648 "%s: Skipping Panel Power action: %s\n", 649 __func__, (power_up ? "On":"Off")); 650 } 651 652 link_encoder_edp_wait_for_hpd_ready(enc110, true); 653 } 654 655 static void aux_initialize( 656 struct dce110_link_encoder *enc110) 657 { 658 struct dc_context *ctx = enc110->base.ctx; 659 enum hpd_source_id hpd_source = enc110->base.hpd_source; 660 uint32_t addr = AUX_REG(AUX_CONTROL); 661 uint32_t value = dm_read_reg(ctx, addr); 662 663 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); 664 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); 665 dm_write_reg(ctx, addr, value); 666 667 addr = AUX_REG(AUX_DPHY_RX_CONTROL0); 668 value = dm_read_reg(ctx, addr); 669 670 /* 1/4 window (the maximum allowed) */ 671 set_reg_field_value(value, 1, 672 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW); 673 dm_write_reg(ctx, addr, value); 674 675 } 676 677 /*todo: cloned in stream enc, fix*/ 678 static bool is_panel_backlight_on(struct dce110_link_encoder *enc110) 679 { 680 uint32_t value; 681 682 REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value); 683 684 return value; 685 } 686 687 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 688 bool exit_link_training_required) 689 { 690 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 691 692 if (exit_link_training_required) 693 REG_UPDATE(DP_DPHY_FAST_TRAINING, 694 DPHY_RX_FAST_TRAINING_CAPABLE, 1); 695 else { 696 REG_UPDATE(DP_DPHY_FAST_TRAINING, 697 DPHY_RX_FAST_TRAINING_CAPABLE, 0); 698 /*In DCE 11, we are able to pre-program a Force SR register 699 * to be able to trigger SR symbol after 5 idle patterns 700 * transmitted. Upon PSR Exit, DMCU can trigger 701 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to 702 * DPHY_LOAD_BS_COUNT_START and the internal counter 703 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be 704 * replaced by SR symbol once. 705 */ 706 707 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5); 708 } 709 } 710 711 void dce110_psr_program_secondary_packet(struct link_encoder *enc, 712 unsigned int sdp_transmit_line_num_deadline) 713 { 714 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 715 716 REG_UPDATE_2(DP_SEC_CNTL1, 717 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline, 718 DP_SEC_GSP0_PRIORITY, 1); 719 } 720 721 /*todo: cloned in stream enc, fix*/ 722 /* 723 * @brief 724 * eDP only. Control the backlight of the eDP panel 725 */ 726 void dce110_link_encoder_edp_backlight_control( 727 struct link_encoder *enc, 728 bool enable) 729 { 730 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 731 struct dc_context *ctx = enc110->base.ctx; 732 struct bp_transmitter_control cntl = { 0 }; 733 734 if (dal_graphics_object_id_get_connector_id(enc110->base.connector) 735 != CONNECTOR_ID_EDP) { 736 BREAK_TO_DEBUGGER(); 737 return; 738 } 739 740 if (enable && is_panel_backlight_on(enc110)) { 741 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 742 "%s: panel already powered up. Do nothing.\n", 743 __func__); 744 return; 745 } 746 747 if (!enable && !is_panel_backlight_on(enc110)) { 748 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 749 "%s: panel already powered down. Do nothing.\n", 750 __func__); 751 return; 752 } 753 754 /* Send VBIOS command to control eDP panel backlight */ 755 756 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 757 "%s: backlight action: %s\n", 758 __func__, (enable ? "On":"Off")); 759 760 cntl.action = enable ? 761 TRANSMITTER_CONTROL_BACKLIGHT_ON : 762 TRANSMITTER_CONTROL_BACKLIGHT_OFF; 763 /*cntl.engine_id = ctx->engine;*/ 764 cntl.transmitter = enc110->base.transmitter; 765 cntl.connector_obj_id = enc110->base.connector; 766 /*todo: unhardcode*/ 767 cntl.lanes_number = LANE_COUNT_FOUR; 768 cntl.hpd_sel = enc110->base.hpd_source; 769 770 /* For eDP, the following delays might need to be considered 771 * after link training completed: 772 * idle period - min. accounts for required BS-Idle pattern, 773 * max. allows for source frame synchronization); 774 * 50 msec max. delay from valid video data from source 775 * to video on dislpay or backlight enable. 776 * 777 * Disable the delay for now. 778 * Enable it in the future if necessary. 779 */ 780 /* dc_service_sleep_in_milliseconds(50); */ 781 link_transmitter_control(enc110, &cntl); 782 } 783 784 static bool is_dig_enabled(const struct dce110_link_encoder *enc110) 785 { 786 uint32_t value; 787 788 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); 789 return value; 790 } 791 792 static void link_encoder_disable(struct dce110_link_encoder *enc110) 793 { 794 /* reset training pattern */ 795 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, 796 DPHY_TRAINING_PATTERN_SEL, 0); 797 798 /* reset training complete */ 799 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); 800 801 /* reset panel mode */ 802 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 803 } 804 805 static void hpd_initialize( 806 struct dce110_link_encoder *enc110) 807 { 808 /* Associate HPD with DIG_BE */ 809 enum hpd_source_id hpd_source = enc110->base.hpd_source; 810 811 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); 812 } 813 814 bool dce110_link_encoder_validate_dvi_output( 815 const struct dce110_link_encoder *enc110, 816 enum signal_type connector_signal, 817 enum signal_type signal, 818 const struct dc_crtc_timing *crtc_timing) 819 { 820 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; 821 822 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK) 823 max_pixel_clock *= 2; 824 825 /* This handles the case of HDMI downgrade to DVI we don't want to 826 * we don't want to cap the pixel clock if the DDI is not DVI. 827 */ 828 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK && 829 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 830 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock; 831 832 /* DVI only support RGB pixel encoding */ 833 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 834 return false; 835 836 /*connect DVI via adpater's HDMI connector*/ 837 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 838 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) && 839 signal != SIGNAL_TYPE_HDMI_TYPE_A && 840 crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK) 841 return false; 842 if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK) 843 return false; 844 845 if (crtc_timing->pix_clk_khz > max_pixel_clock) 846 return false; 847 848 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */ 849 switch (crtc_timing->display_color_depth) { 850 case COLOR_DEPTH_666: 851 case COLOR_DEPTH_888: 852 break; 853 case COLOR_DEPTH_101010: 854 case COLOR_DEPTH_161616: 855 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK) 856 return false; 857 break; 858 default: 859 return false; 860 } 861 862 return true; 863 } 864 865 static bool dce110_link_encoder_validate_hdmi_output( 866 const struct dce110_link_encoder *enc110, 867 const struct dc_crtc_timing *crtc_timing, 868 int adjusted_pix_clk_khz) 869 { 870 enum dc_color_depth max_deep_color = 871 enc110->base.features.max_hdmi_deep_color; 872 873 if (max_deep_color < crtc_timing->display_color_depth) 874 return false; 875 876 if (crtc_timing->display_color_depth < COLOR_DEPTH_888) 877 return false; 878 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK) 879 return false; 880 881 if ((adjusted_pix_clk_khz == 0) || 882 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) 883 return false; 884 885 /* DCE11 HW does not support 420 */ 886 if (!enc110->base.features.ycbcr420_supported && 887 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 888 return false; 889 890 return true; 891 } 892 893 bool dce110_link_encoder_validate_dp_output( 894 const struct dce110_link_encoder *enc110, 895 const struct dc_crtc_timing *crtc_timing) 896 { 897 /* default RGB only */ 898 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 899 return true; 900 901 if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE) 902 return true; 903 904 /* for DCE 8.x or later DP Y-only feature, 905 * we need ASIC cap + FeatureSupportDPYonly, not support 666 */ 906 if (crtc_timing->flags.Y_ONLY && 907 enc110->base.features.flags.bits.IS_YCBCR_CAPABLE && 908 crtc_timing->display_color_depth != COLOR_DEPTH_666) 909 return true; 910 911 return false; 912 } 913 914 bool dce110_link_encoder_construct( 915 struct dce110_link_encoder *enc110, 916 const struct encoder_init_data *init_data, 917 const struct encoder_feature_support *enc_features, 918 const struct dce110_link_enc_registers *link_regs, 919 const struct dce110_link_enc_aux_registers *aux_regs, 920 const struct dce110_link_enc_hpd_registers *hpd_regs) 921 { 922 struct bp_encoder_cap_info bp_cap_info = {0}; 923 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 924 925 enc110->base.funcs = &dce110_lnk_enc_funcs; 926 enc110->base.ctx = init_data->ctx; 927 enc110->base.id = init_data->encoder; 928 929 enc110->base.hpd_source = init_data->hpd_source; 930 enc110->base.connector = init_data->connector; 931 932 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 933 934 enc110->base.features = *enc_features; 935 936 enc110->base.transmitter = init_data->transmitter; 937 938 /* set the flag to indicate whether driver poll the I2C data pin 939 * while doing the DP sink detect 940 */ 941 942 /* if (dal_adapter_service_is_feature_supported(as, 943 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 944 enc110->base.features.flags.bits. 945 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 946 947 enc110->base.output_signals = 948 SIGNAL_TYPE_DVI_SINGLE_LINK | 949 SIGNAL_TYPE_DVI_DUAL_LINK | 950 SIGNAL_TYPE_LVDS | 951 SIGNAL_TYPE_DISPLAY_PORT | 952 SIGNAL_TYPE_DISPLAY_PORT_MST | 953 SIGNAL_TYPE_EDP | 954 SIGNAL_TYPE_HDMI_TYPE_A; 955 956 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 957 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 958 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 959 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 960 * Prefer DIG assignment is decided by board design. 961 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 962 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 963 * By this, adding DIGG should not hurt DCE 8.0. 964 * This will let DCE 8.1 share DCE 8.0 as much as possible 965 */ 966 967 enc110->link_regs = link_regs; 968 enc110->aux_regs = aux_regs; 969 enc110->hpd_regs = hpd_regs; 970 971 switch (enc110->base.transmitter) { 972 case TRANSMITTER_UNIPHY_A: 973 enc110->base.preferred_engine = ENGINE_ID_DIGA; 974 break; 975 case TRANSMITTER_UNIPHY_B: 976 enc110->base.preferred_engine = ENGINE_ID_DIGB; 977 break; 978 case TRANSMITTER_UNIPHY_C: 979 enc110->base.preferred_engine = ENGINE_ID_DIGC; 980 break; 981 case TRANSMITTER_UNIPHY_D: 982 enc110->base.preferred_engine = ENGINE_ID_DIGD; 983 break; 984 case TRANSMITTER_UNIPHY_E: 985 enc110->base.preferred_engine = ENGINE_ID_DIGE; 986 break; 987 case TRANSMITTER_UNIPHY_F: 988 enc110->base.preferred_engine = ENGINE_ID_DIGF; 989 break; 990 case TRANSMITTER_UNIPHY_G: 991 enc110->base.preferred_engine = ENGINE_ID_DIGG; 992 break; 993 default: 994 ASSERT_CRITICAL(false); 995 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 996 } 997 998 dm_logger_write(init_data->ctx->logger, LOG_I2C_AUX, 999 "Using channel: %s [%d]\n", 1000 DECODE_CHANNEL_ID(init_data->channel), 1001 init_data->channel); 1002 1003 /* Override features with DCE-specific values */ 1004 if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info( 1005 enc110->base.ctx->dc_bios, enc110->base.id, 1006 &bp_cap_info)) { 1007 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 1008 bp_cap_info.DP_HBR2_EN; 1009 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 1010 bp_cap_info.DP_HBR3_EN; 1011 } 1012 1013 return true; 1014 } 1015 1016 bool dce110_link_encoder_validate_output_with_stream( 1017 struct link_encoder *enc, 1018 const struct dc_stream_state *stream) 1019 { 1020 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1021 bool is_valid; 1022 1023 switch (stream->signal) { 1024 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1025 case SIGNAL_TYPE_DVI_DUAL_LINK: 1026 is_valid = dce110_link_encoder_validate_dvi_output( 1027 enc110, 1028 stream->sink->link->connector_signal, 1029 stream->signal, 1030 &stream->timing); 1031 break; 1032 case SIGNAL_TYPE_HDMI_TYPE_A: 1033 is_valid = dce110_link_encoder_validate_hdmi_output( 1034 enc110, 1035 &stream->timing, 1036 stream->phy_pix_clk); 1037 break; 1038 case SIGNAL_TYPE_DISPLAY_PORT: 1039 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1040 is_valid = dce110_link_encoder_validate_dp_output( 1041 enc110, &stream->timing); 1042 break; 1043 case SIGNAL_TYPE_EDP: 1044 is_valid = 1045 (stream->timing. 1046 pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; 1047 break; 1048 case SIGNAL_TYPE_VIRTUAL: 1049 is_valid = true; 1050 break; 1051 default: 1052 is_valid = false; 1053 break; 1054 } 1055 1056 return is_valid; 1057 } 1058 1059 void dce110_link_encoder_hw_init( 1060 struct link_encoder *enc) 1061 { 1062 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1063 struct dc_context *ctx = enc110->base.ctx; 1064 struct bp_transmitter_control cntl = { 0 }; 1065 enum bp_result result; 1066 1067 cntl.action = TRANSMITTER_CONTROL_INIT; 1068 cntl.engine_id = ENGINE_ID_UNKNOWN; 1069 cntl.transmitter = enc110->base.transmitter; 1070 cntl.connector_obj_id = enc110->base.connector; 1071 cntl.lanes_number = LANE_COUNT_FOUR; 1072 cntl.coherent = false; 1073 cntl.hpd_sel = enc110->base.hpd_source; 1074 1075 result = link_transmitter_control(enc110, &cntl); 1076 1077 if (result != BP_RESULT_OK) { 1078 dm_logger_write(ctx->logger, LOG_ERROR, 1079 "%s: Failed to execute VBIOS command table!\n", 1080 __func__); 1081 BREAK_TO_DEBUGGER(); 1082 return; 1083 } 1084 1085 if (enc110->base.connector.id == CONNECTOR_ID_LVDS) { 1086 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS; 1087 1088 result = link_transmitter_control(enc110, &cntl); 1089 1090 ASSERT(result == BP_RESULT_OK); 1091 1092 } else if (enc110->base.connector.id == CONNECTOR_ID_EDP) { 1093 enc->funcs->power_control(&enc110->base, true); 1094 } 1095 aux_initialize(enc110); 1096 1097 /* reinitialize HPD. 1098 * hpd_initialize() will pass DIG_FE id to HW context. 1099 * All other routine within HW context will use fe_engine_offset 1100 * as DIG_FE id even caller pass DIG_FE id. 1101 * So this routine must be called first. */ 1102 hpd_initialize(enc110); 1103 } 1104 1105 void dce110_link_encoder_destroy(struct link_encoder **enc) 1106 { 1107 dm_free(TO_DCE110_LINK_ENC(*enc)); 1108 *enc = NULL; 1109 } 1110 1111 void dce110_link_encoder_setup( 1112 struct link_encoder *enc, 1113 enum signal_type signal) 1114 { 1115 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1116 1117 switch (signal) { 1118 case SIGNAL_TYPE_EDP: 1119 case SIGNAL_TYPE_DISPLAY_PORT: 1120 /* DP SST */ 1121 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); 1122 break; 1123 case SIGNAL_TYPE_LVDS: 1124 /* LVDS */ 1125 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); 1126 break; 1127 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1128 case SIGNAL_TYPE_DVI_DUAL_LINK: 1129 /* TMDS-DVI */ 1130 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); 1131 break; 1132 case SIGNAL_TYPE_HDMI_TYPE_A: 1133 /* TMDS-HDMI */ 1134 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); 1135 break; 1136 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1137 /* DP MST */ 1138 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); 1139 break; 1140 default: 1141 ASSERT_CRITICAL(false); 1142 /* invalid mode ! */ 1143 break; 1144 } 1145 1146 } 1147 1148 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1149 void dce110_link_encoder_enable_tmds_output( 1150 struct link_encoder *enc, 1151 enum clock_source_id clock_source, 1152 enum dc_color_depth color_depth, 1153 bool hdmi, 1154 bool dual_link, 1155 uint32_t pixel_clock) 1156 { 1157 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1158 struct dc_context *ctx = enc110->base.ctx; 1159 struct bp_transmitter_control cntl = { 0 }; 1160 enum bp_result result; 1161 1162 /* Enable the PHY */ 1163 1164 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1165 cntl.engine_id = enc->preferred_engine; 1166 cntl.transmitter = enc110->base.transmitter; 1167 cntl.pll_id = clock_source; 1168 if (hdmi) { 1169 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1170 cntl.lanes_number = 4; 1171 } else if (dual_link) { 1172 cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1173 cntl.lanes_number = 8; 1174 } else { 1175 cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1176 cntl.lanes_number = 4; 1177 } 1178 cntl.hpd_sel = enc110->base.hpd_source; 1179 1180 cntl.pixel_clock = pixel_clock; 1181 cntl.color_depth = color_depth; 1182 1183 result = link_transmitter_control(enc110, &cntl); 1184 1185 if (result != BP_RESULT_OK) { 1186 dm_logger_write(ctx->logger, LOG_ERROR, 1187 "%s: Failed to execute VBIOS command table!\n", 1188 __func__); 1189 BREAK_TO_DEBUGGER(); 1190 } 1191 } 1192 1193 /* enables DP PHY output */ 1194 void dce110_link_encoder_enable_dp_output( 1195 struct link_encoder *enc, 1196 const struct dc_link_settings *link_settings, 1197 enum clock_source_id clock_source) 1198 { 1199 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1200 struct dc_context *ctx = enc110->base.ctx; 1201 struct bp_transmitter_control cntl = { 0 }; 1202 enum bp_result result; 1203 1204 /* Enable the PHY */ 1205 1206 /* number_of_lanes is used for pixel clock adjust, 1207 * but it's not passed to asic_control. 1208 * We need to set number of lanes manually. 1209 */ 1210 configure_encoder(enc110, link_settings); 1211 1212 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1213 cntl.engine_id = enc->preferred_engine; 1214 cntl.transmitter = enc110->base.transmitter; 1215 cntl.pll_id = clock_source; 1216 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1217 cntl.lanes_number = link_settings->lane_count; 1218 cntl.hpd_sel = enc110->base.hpd_source; 1219 cntl.pixel_clock = link_settings->link_rate 1220 * LINK_RATE_REF_FREQ_IN_KHZ; 1221 /* TODO: check if undefined works */ 1222 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1223 1224 result = link_transmitter_control(enc110, &cntl); 1225 1226 if (result != BP_RESULT_OK) { 1227 dm_logger_write(ctx->logger, LOG_ERROR, 1228 "%s: Failed to execute VBIOS command table!\n", 1229 __func__); 1230 BREAK_TO_DEBUGGER(); 1231 } 1232 } 1233 1234 /* enables DP PHY output in MST mode */ 1235 void dce110_link_encoder_enable_dp_mst_output( 1236 struct link_encoder *enc, 1237 const struct dc_link_settings *link_settings, 1238 enum clock_source_id clock_source) 1239 { 1240 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1241 struct dc_context *ctx = enc110->base.ctx; 1242 struct bp_transmitter_control cntl = { 0 }; 1243 enum bp_result result; 1244 1245 /* Enable the PHY */ 1246 1247 /* number_of_lanes is used for pixel clock adjust, 1248 * but it's not passed to asic_control. 1249 * We need to set number of lanes manually. 1250 */ 1251 configure_encoder(enc110, link_settings); 1252 1253 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1254 cntl.engine_id = ENGINE_ID_UNKNOWN; 1255 cntl.transmitter = enc110->base.transmitter; 1256 cntl.pll_id = clock_source; 1257 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1258 cntl.lanes_number = link_settings->lane_count; 1259 cntl.hpd_sel = enc110->base.hpd_source; 1260 cntl.pixel_clock = link_settings->link_rate 1261 * LINK_RATE_REF_FREQ_IN_KHZ; 1262 /* TODO: check if undefined works */ 1263 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1264 1265 result = link_transmitter_control(enc110, &cntl); 1266 1267 if (result != BP_RESULT_OK) { 1268 dm_logger_write(ctx->logger, LOG_ERROR, 1269 "%s: Failed to execute VBIOS command table!\n", 1270 __func__); 1271 BREAK_TO_DEBUGGER(); 1272 } 1273 } 1274 /* 1275 * @brief 1276 * Disable transmitter and its encoder 1277 */ 1278 void dce110_link_encoder_disable_output( 1279 struct link_encoder *enc, 1280 enum signal_type signal) 1281 { 1282 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1283 struct dc_context *ctx = enc110->base.ctx; 1284 struct bp_transmitter_control cntl = { 0 }; 1285 enum bp_result result; 1286 1287 if (!is_dig_enabled(enc110)) { 1288 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ 1289 return; 1290 } 1291 if (enc110->base.connector.id == CONNECTOR_ID_EDP) 1292 dce110_link_encoder_edp_backlight_control(enc, false); 1293 /* Power-down RX and disable GPU PHY should be paired. 1294 * Disabling PHY without powering down RX may cause 1295 * symbol lock loss, on which we will get DP Sink interrupt. */ 1296 1297 /* There is a case for the DP active dongles 1298 * where we want to disable the PHY but keep RX powered, 1299 * for those we need to ignore DP Sink interrupt 1300 * by checking lane count that has been set 1301 * on the last do_enable_output(). */ 1302 1303 /* disable transmitter */ 1304 cntl.action = TRANSMITTER_CONTROL_DISABLE; 1305 cntl.transmitter = enc110->base.transmitter; 1306 cntl.hpd_sel = enc110->base.hpd_source; 1307 cntl.signal = signal; 1308 cntl.connector_obj_id = enc110->base.connector; 1309 1310 result = link_transmitter_control(enc110, &cntl); 1311 1312 if (result != BP_RESULT_OK) { 1313 dm_logger_write(ctx->logger, LOG_ERROR, 1314 "%s: Failed to execute VBIOS command table!\n", 1315 __func__); 1316 BREAK_TO_DEBUGGER(); 1317 return; 1318 } 1319 1320 /* disable encoder */ 1321 if (dc_is_dp_signal(signal)) 1322 link_encoder_disable(enc110); 1323 1324 if (enc110->base.connector.id == CONNECTOR_ID_EDP) { 1325 /* power down eDP panel */ 1326 /* TODO: Power control cause regression, we should implement 1327 * it properly, for now just comment it. 1328 * 1329 * link_encoder_edp_wait_for_hpd_ready( 1330 link_enc, 1331 link_enc->connector, 1332 false); 1333 1334 * link_encoder_edp_power_control( 1335 link_enc, false); */ 1336 } 1337 } 1338 1339 void dce110_link_encoder_dp_set_lane_settings( 1340 struct link_encoder *enc, 1341 const struct link_training_settings *link_settings) 1342 { 1343 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1344 union dpcd_training_lane_set training_lane_set = { { 0 } }; 1345 int32_t lane = 0; 1346 struct bp_transmitter_control cntl = { 0 }; 1347 1348 if (!link_settings) { 1349 BREAK_TO_DEBUGGER(); 1350 return; 1351 } 1352 1353 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1354 cntl.transmitter = enc110->base.transmitter; 1355 cntl.connector_obj_id = enc110->base.connector; 1356 cntl.lanes_number = link_settings->link_settings.lane_count; 1357 cntl.hpd_sel = enc110->base.hpd_source; 1358 cntl.pixel_clock = link_settings->link_settings.link_rate * 1359 LINK_RATE_REF_FREQ_IN_KHZ; 1360 1361 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { 1362 /* translate lane settings */ 1363 1364 training_lane_set.bits.VOLTAGE_SWING_SET = 1365 link_settings->lane_settings[lane].VOLTAGE_SWING; 1366 training_lane_set.bits.PRE_EMPHASIS_SET = 1367 link_settings->lane_settings[lane].PRE_EMPHASIS; 1368 1369 /* post cursor 2 setting only applies to HBR2 link rate */ 1370 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { 1371 /* this is passed to VBIOS 1372 * to program post cursor 2 level */ 1373 1374 training_lane_set.bits.POST_CURSOR2_SET = 1375 link_settings->lane_settings[lane].POST_CURSOR2; 1376 } 1377 1378 cntl.lane_select = lane; 1379 cntl.lane_settings = training_lane_set.raw; 1380 1381 /* call VBIOS table to set voltage swing and pre-emphasis */ 1382 link_transmitter_control(enc110, &cntl); 1383 } 1384 } 1385 1386 /* set DP PHY test and training patterns */ 1387 void dce110_link_encoder_dp_set_phy_pattern( 1388 struct link_encoder *enc, 1389 const struct encoder_set_dp_phy_pattern_param *param) 1390 { 1391 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1392 1393 switch (param->dp_phy_pattern) { 1394 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1395 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1396 break; 1397 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1398 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1399 break; 1400 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1401 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1402 break; 1403 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1404 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1405 break; 1406 case DP_TEST_PATTERN_D102: 1407 set_dp_phy_pattern_d102(enc110); 1408 break; 1409 case DP_TEST_PATTERN_SYMBOL_ERROR: 1410 set_dp_phy_pattern_symbol_error(enc110); 1411 break; 1412 case DP_TEST_PATTERN_PRBS7: 1413 set_dp_phy_pattern_prbs7(enc110); 1414 break; 1415 case DP_TEST_PATTERN_80BIT_CUSTOM: 1416 set_dp_phy_pattern_80bit_custom( 1417 enc110, param->custom_pattern); 1418 break; 1419 case DP_TEST_PATTERN_CP2520_1: 1420 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1421 break; 1422 case DP_TEST_PATTERN_CP2520_2: 1423 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1424 break; 1425 case DP_TEST_PATTERN_CP2520_3: 1426 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1427 break; 1428 case DP_TEST_PATTERN_VIDEO_MODE: { 1429 set_dp_phy_pattern_passthrough_mode( 1430 enc110, param->dp_panel_mode); 1431 break; 1432 } 1433 1434 default: 1435 /* invalid phy pattern */ 1436 ASSERT_CRITICAL(false); 1437 break; 1438 } 1439 } 1440 1441 static void fill_stream_allocation_row_info( 1442 const struct link_mst_stream_allocation *stream_allocation, 1443 uint32_t *src, 1444 uint32_t *slots) 1445 { 1446 const struct stream_encoder *stream_enc = stream_allocation->stream_enc; 1447 1448 if (stream_enc) { 1449 *src = stream_enc->id; 1450 *slots = stream_allocation->slot_count; 1451 } else { 1452 *src = 0; 1453 *slots = 0; 1454 } 1455 } 1456 1457 /* programs DP MST VC payload allocation */ 1458 void dce110_link_encoder_update_mst_stream_allocation_table( 1459 struct link_encoder *enc, 1460 const struct link_mst_stream_allocation_table *table) 1461 { 1462 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1463 uint32_t value0 = 0; 1464 uint32_t value1 = 0; 1465 uint32_t value2 = 0; 1466 uint32_t slots = 0; 1467 uint32_t src = 0; 1468 uint32_t retries = 0; 1469 1470 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/ 1471 1472 /* --- Set MSE Stream Attribute - 1473 * Setup VC Payload Table on Tx Side, 1474 * Issue allocation change trigger 1475 * to commit payload on both tx and rx side */ 1476 1477 /* we should clean-up table each time */ 1478 1479 if (table->stream_count >= 1) { 1480 fill_stream_allocation_row_info( 1481 &table->stream_allocations[0], 1482 &src, 1483 &slots); 1484 } else { 1485 src = 0; 1486 slots = 0; 1487 } 1488 1489 REG_UPDATE_2(DP_MSE_SAT0, 1490 DP_MSE_SAT_SRC0, src, 1491 DP_MSE_SAT_SLOT_COUNT0, slots); 1492 1493 if (table->stream_count >= 2) { 1494 fill_stream_allocation_row_info( 1495 &table->stream_allocations[1], 1496 &src, 1497 &slots); 1498 } else { 1499 src = 0; 1500 slots = 0; 1501 } 1502 1503 REG_UPDATE_2(DP_MSE_SAT0, 1504 DP_MSE_SAT_SRC1, src, 1505 DP_MSE_SAT_SLOT_COUNT1, slots); 1506 1507 if (table->stream_count >= 3) { 1508 fill_stream_allocation_row_info( 1509 &table->stream_allocations[2], 1510 &src, 1511 &slots); 1512 } else { 1513 src = 0; 1514 slots = 0; 1515 } 1516 1517 REG_UPDATE_2(DP_MSE_SAT1, 1518 DP_MSE_SAT_SRC2, src, 1519 DP_MSE_SAT_SLOT_COUNT2, slots); 1520 1521 if (table->stream_count >= 4) { 1522 fill_stream_allocation_row_info( 1523 &table->stream_allocations[3], 1524 &src, 1525 &slots); 1526 } else { 1527 src = 0; 1528 slots = 0; 1529 } 1530 1531 REG_UPDATE_2(DP_MSE_SAT1, 1532 DP_MSE_SAT_SRC3, src, 1533 DP_MSE_SAT_SLOT_COUNT3, slots); 1534 1535 /* --- wait for transaction finish */ 1536 1537 /* send allocation change trigger (ACT) ? 1538 * this step first sends the ACT, 1539 * then double buffers the SAT into the hardware 1540 * making the new allocation active on the DP MST mode link */ 1541 1542 1543 /* DP_MSE_SAT_UPDATE: 1544 * 0 - No Action 1545 * 1 - Update SAT with trigger 1546 * 2 - Update SAT without trigger */ 1547 1548 REG_UPDATE(DP_MSE_SAT_UPDATE, 1549 DP_MSE_SAT_UPDATE, 1); 1550 1551 /* wait for update to complete 1552 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0) 1553 * then wait for the transmission 1554 * of at least 16 MTP headers on immediate local link. 1555 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0 1556 * a value of 1 indicates that DP MST mode 1557 * is in the 16 MTP keepout region after a VC has been added. 1558 * MST stream bandwidth (VC rate) can be configured 1559 * after this bit is cleared */ 1560 1561 do { 1562 udelay(10); 1563 1564 value0 = REG_READ(DP_MSE_SAT_UPDATE); 1565 1566 REG_GET(DP_MSE_SAT_UPDATE, 1567 DP_MSE_SAT_UPDATE, &value1); 1568 1569 REG_GET(DP_MSE_SAT_UPDATE, 1570 DP_MSE_16_MTP_KEEPOUT, &value2); 1571 1572 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */ 1573 if (!value1 && !value2) 1574 break; 1575 ++retries; 1576 } while (retries < DP_MST_UPDATE_MAX_RETRY); 1577 } 1578 1579 void dce110_link_encoder_connect_dig_be_to_fe( 1580 struct link_encoder *enc, 1581 enum engine_id engine, 1582 bool connect) 1583 { 1584 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1585 uint32_t field; 1586 1587 if (engine != ENGINE_ID_UNKNOWN) { 1588 1589 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); 1590 1591 if (connect) 1592 field |= get_frontend_source(engine); 1593 else 1594 field &= ~get_frontend_source(engine); 1595 1596 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); 1597 } 1598 } 1599 1600 void dce110_link_encoder_enable_hpd(struct link_encoder *enc) 1601 { 1602 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1603 struct dc_context *ctx = enc110->base.ctx; 1604 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1605 uint32_t hpd_enable = 0; 1606 uint32_t value = dm_read_reg(ctx, addr); 1607 1608 get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN); 1609 1610 if (hpd_enable == 0) 1611 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); 1612 } 1613 1614 void dce110_link_encoder_disable_hpd(struct link_encoder *enc) 1615 { 1616 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1617 struct dc_context *ctx = enc110->base.ctx; 1618 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1619 uint32_t value = dm_read_reg(ctx, addr); 1620 1621 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); 1622 } 1623