1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "reg_helper.h" 30 31 #include "core_types.h" 32 #include "link_encoder.h" 33 #include "dce_link_encoder.h" 34 #include "stream_encoder.h" 35 #include "i2caux_interface.h" 36 #include "dc_bios_types.h" 37 38 #include "gpio_service_interface.h" 39 40 #include "dce/dce_11_0_d.h" 41 #include "dce/dce_11_0_sh_mask.h" 42 #include "dce/dce_11_0_enum.h" 43 44 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 45 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa 46 #endif 47 48 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 49 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L 50 #endif 51 52 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 53 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L 54 #endif 55 56 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 57 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c 58 #endif 59 60 #define CTX \ 61 enc110->base.ctx 62 #define DC_LOGGER \ 63 enc110->base.ctx->logger 64 65 #define REG(reg)\ 66 (enc110->link_regs->reg) 67 68 #define AUX_REG(reg)\ 69 (enc110->aux_regs->reg) 70 71 #define HPD_REG(reg)\ 72 (enc110->hpd_regs->reg) 73 74 #define DEFAULT_AUX_MAX_DATA_SIZE 16 75 #define AUX_MAX_DEFER_WRITE_RETRY 20 76 /* 77 * @brief 78 * Trigger Source Select 79 * ASIC-dependent, actual values for register programming 80 */ 81 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0 82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1 83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2 84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4 85 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08 86 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10 87 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 88 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 89 90 enum { 91 DP_MST_UPDATE_MAX_RETRY = 50 92 }; 93 94 #define DIG_REG(reg)\ 95 (reg + enc110->offsets.dig) 96 97 #define DP_REG(reg)\ 98 (reg + enc110->offsets.dp) 99 100 static const struct link_encoder_funcs dce110_lnk_enc_funcs = { 101 .validate_output_with_stream = 102 dce110_link_encoder_validate_output_with_stream, 103 .hw_init = dce110_link_encoder_hw_init, 104 .setup = dce110_link_encoder_setup, 105 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 106 .enable_dp_output = dce110_link_encoder_enable_dp_output, 107 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, 108 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 109 .disable_output = dce110_link_encoder_disable_output, 110 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 111 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, 112 .update_mst_stream_allocation_table = 113 dce110_link_encoder_update_mst_stream_allocation_table, 114 .psr_program_dp_dphy_fast_training = 115 dce110_psr_program_dp_dphy_fast_training, 116 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 117 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 118 .enable_hpd = dce110_link_encoder_enable_hpd, 119 .disable_hpd = dce110_link_encoder_disable_hpd, 120 .is_dig_enabled = dce110_is_dig_enabled, 121 .destroy = dce110_link_encoder_destroy, 122 .get_max_link_cap = dce110_link_encoder_get_max_link_cap 123 }; 124 125 static enum bp_result link_transmitter_control( 126 struct dce110_link_encoder *enc110, 127 struct bp_transmitter_control *cntl) 128 { 129 enum bp_result result; 130 struct dc_bios *bp = enc110->base.ctx->dc_bios; 131 132 result = bp->funcs->transmitter_control(bp, cntl); 133 134 return result; 135 } 136 137 static void enable_phy_bypass_mode( 138 struct dce110_link_encoder *enc110, 139 bool enable) 140 { 141 /* This register resides in DP back end block; 142 * transmitter is used for the offset */ 143 144 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); 145 146 } 147 148 static void disable_prbs_symbols( 149 struct dce110_link_encoder *enc110, 150 bool disable) 151 { 152 /* This register resides in DP back end block; 153 * transmitter is used for the offset */ 154 155 REG_UPDATE_4(DP_DPHY_CNTL, 156 DPHY_ATEST_SEL_LANE0, disable, 157 DPHY_ATEST_SEL_LANE1, disable, 158 DPHY_ATEST_SEL_LANE2, disable, 159 DPHY_ATEST_SEL_LANE3, disable); 160 } 161 162 static void disable_prbs_mode( 163 struct dce110_link_encoder *enc110) 164 { 165 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); 166 } 167 168 static void program_pattern_symbols( 169 struct dce110_link_encoder *enc110, 170 uint16_t pattern_symbols[8]) 171 { 172 /* This register resides in DP back end block; 173 * transmitter is used for the offset */ 174 175 REG_SET_3(DP_DPHY_SYM0, 0, 176 DPHY_SYM1, pattern_symbols[0], 177 DPHY_SYM2, pattern_symbols[1], 178 DPHY_SYM3, pattern_symbols[2]); 179 180 /* This register resides in DP back end block; 181 * transmitter is used for the offset */ 182 183 REG_SET_3(DP_DPHY_SYM1, 0, 184 DPHY_SYM4, pattern_symbols[3], 185 DPHY_SYM5, pattern_symbols[4], 186 DPHY_SYM6, pattern_symbols[5]); 187 188 /* This register resides in DP back end block; 189 * transmitter is used for the offset */ 190 191 REG_SET_2(DP_DPHY_SYM2, 0, 192 DPHY_SYM7, pattern_symbols[6], 193 DPHY_SYM8, pattern_symbols[7]); 194 } 195 196 static void set_dp_phy_pattern_d102( 197 struct dce110_link_encoder *enc110) 198 { 199 /* Disable PHY Bypass mode to setup the test pattern */ 200 enable_phy_bypass_mode(enc110, false); 201 202 /* For 10-bit PRBS or debug symbols 203 * please use the following sequence: */ 204 205 /* Enable debug symbols on the lanes */ 206 207 disable_prbs_symbols(enc110, true); 208 209 /* Disable PRBS mode */ 210 disable_prbs_mode(enc110); 211 212 /* Program debug symbols to be output */ 213 { 214 uint16_t pattern_symbols[8] = { 215 0x2AA, 0x2AA, 0x2AA, 0x2AA, 216 0x2AA, 0x2AA, 0x2AA, 0x2AA 217 }; 218 219 program_pattern_symbols(enc110, pattern_symbols); 220 } 221 222 /* Enable phy bypass mode to enable the test pattern */ 223 224 enable_phy_bypass_mode(enc110, true); 225 } 226 227 static void set_link_training_complete( 228 struct dce110_link_encoder *enc110, 229 bool complete) 230 { 231 /* This register resides in DP back end block; 232 * transmitter is used for the offset */ 233 234 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); 235 236 } 237 238 void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 239 struct link_encoder *enc, 240 uint32_t index) 241 { 242 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 243 /* Write Training Pattern */ 244 245 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); 246 247 /* Set HW Register Training Complete to false */ 248 249 set_link_training_complete(enc110, false); 250 251 /* Disable PHY Bypass mode to output Training Pattern */ 252 253 enable_phy_bypass_mode(enc110, false); 254 255 /* Disable PRBS mode */ 256 disable_prbs_mode(enc110); 257 } 258 259 static void setup_panel_mode( 260 struct dce110_link_encoder *enc110, 261 enum dp_panel_mode panel_mode) 262 { 263 uint32_t value; 264 struct dc_context *ctx = enc110->base.ctx; 265 266 /* if psp set panel mode, dal should be program it */ 267 if (ctx->dc->caps.psp_setup_panel_mode) 268 return; 269 270 ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); 271 value = REG_READ(DP_DPHY_INTERNAL_CTRL); 272 273 switch (panel_mode) { 274 case DP_PANEL_MODE_EDP: 275 value = 0x1; 276 break; 277 case DP_PANEL_MODE_SPECIAL: 278 value = 0x11; 279 break; 280 default: 281 value = 0x0; 282 break; 283 } 284 285 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); 286 } 287 288 static void set_dp_phy_pattern_symbol_error( 289 struct dce110_link_encoder *enc110) 290 { 291 /* Disable PHY Bypass mode to setup the test pattern */ 292 enable_phy_bypass_mode(enc110, false); 293 294 /* program correct panel mode*/ 295 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 296 297 /* A PRBS23 pattern is used for most DP electrical measurements. */ 298 299 /* Enable PRBS symbols on the lanes */ 300 disable_prbs_symbols(enc110, false); 301 302 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */ 303 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 304 DPHY_PRBS_SEL, 1, 305 DPHY_PRBS_EN, 1); 306 307 /* Enable phy bypass mode to enable the test pattern */ 308 enable_phy_bypass_mode(enc110, true); 309 } 310 311 static void set_dp_phy_pattern_prbs7( 312 struct dce110_link_encoder *enc110) 313 { 314 /* Disable PHY Bypass mode to setup the test pattern */ 315 enable_phy_bypass_mode(enc110, false); 316 317 /* A PRBS7 pattern is used for most DP electrical measurements. */ 318 319 /* Enable PRBS symbols on the lanes */ 320 disable_prbs_symbols(enc110, false); 321 322 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */ 323 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 324 DPHY_PRBS_SEL, 0, 325 DPHY_PRBS_EN, 1); 326 327 /* Enable phy bypass mode to enable the test pattern */ 328 enable_phy_bypass_mode(enc110, true); 329 } 330 331 static void set_dp_phy_pattern_80bit_custom( 332 struct dce110_link_encoder *enc110, 333 const uint8_t *pattern) 334 { 335 /* Disable PHY Bypass mode to setup the test pattern */ 336 enable_phy_bypass_mode(enc110, false); 337 338 /* Enable debug symbols on the lanes */ 339 340 disable_prbs_symbols(enc110, true); 341 342 /* Enable PHY bypass mode to enable the test pattern */ 343 /* TODO is it really needed ? */ 344 345 enable_phy_bypass_mode(enc110, true); 346 347 /* Program 80 bit custom pattern */ 348 { 349 uint16_t pattern_symbols[8]; 350 351 pattern_symbols[0] = 352 ((pattern[1] & 0x03) << 8) | pattern[0]; 353 pattern_symbols[1] = 354 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f); 355 pattern_symbols[2] = 356 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f); 357 pattern_symbols[3] = 358 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03); 359 pattern_symbols[4] = 360 ((pattern[6] & 0x03) << 8) | pattern[5]; 361 pattern_symbols[5] = 362 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f); 363 pattern_symbols[6] = 364 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f); 365 pattern_symbols[7] = 366 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03); 367 368 program_pattern_symbols(enc110, pattern_symbols); 369 } 370 371 /* Enable phy bypass mode to enable the test pattern */ 372 373 enable_phy_bypass_mode(enc110, true); 374 } 375 376 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( 377 struct dce110_link_encoder *enc110, 378 unsigned int cp2520_pattern) 379 { 380 381 /* previously there is a register DP_HBR2_EYE_PATTERN 382 * that is enabled to get the pattern. 383 * But it does not work with the latest spec change, 384 * so we are programming the following registers manually. 385 * 386 * The following settings have been confirmed 387 * by Nick Chorney and Sandra Liu */ 388 389 /* Disable PHY Bypass mode to setup the test pattern */ 390 391 enable_phy_bypass_mode(enc110, false); 392 393 /* Setup DIG encoder in DP SST mode */ 394 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 395 396 /* ensure normal panel mode. */ 397 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 398 399 /* no vbid after BS (SR) 400 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 401 * 11000260 / 11000104 / 110000FC */ 402 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 403 DP_IDLE_BS_INTERVAL, 0xFC, 404 DP_VBID_DISABLE, 1, 405 DP_VID_ENHANCED_FRAME_MODE, 1); 406 407 /* swap every BS with SR */ 408 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); 409 410 /* select cp2520 patterns */ 411 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 412 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 413 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 414 else 415 /* pre-DCE11 can only generate CP2520 pattern 2 */ 416 ASSERT(cp2520_pattern == 2); 417 418 /* set link training complete */ 419 set_link_training_complete(enc110, true); 420 421 /* disable video stream */ 422 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 423 424 /* Disable PHY Bypass mode to setup the test pattern */ 425 enable_phy_bypass_mode(enc110, false); 426 } 427 428 static void set_dp_phy_pattern_passthrough_mode( 429 struct dce110_link_encoder *enc110, 430 enum dp_panel_mode panel_mode) 431 { 432 /* program correct panel mode */ 433 setup_panel_mode(enc110, panel_mode); 434 435 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT 436 * in case we were doing HBR2 compliance pattern before 437 */ 438 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 439 DP_IDLE_BS_INTERVAL, 0x2000, 440 DP_VBID_DISABLE, 0, 441 DP_VID_ENHANCED_FRAME_MODE, 1); 442 443 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); 444 445 /* set link training complete */ 446 set_link_training_complete(enc110, true); 447 448 /* Disable PHY Bypass mode to setup the test pattern */ 449 enable_phy_bypass_mode(enc110, false); 450 451 /* Disable PRBS mode */ 452 disable_prbs_mode(enc110); 453 } 454 455 /* return value is bit-vector */ 456 static uint8_t get_frontend_source( 457 enum engine_id engine) 458 { 459 switch (engine) { 460 case ENGINE_ID_DIGA: 461 return DCE110_DIG_FE_SOURCE_SELECT_DIGA; 462 case ENGINE_ID_DIGB: 463 return DCE110_DIG_FE_SOURCE_SELECT_DIGB; 464 case ENGINE_ID_DIGC: 465 return DCE110_DIG_FE_SOURCE_SELECT_DIGC; 466 case ENGINE_ID_DIGD: 467 return DCE110_DIG_FE_SOURCE_SELECT_DIGD; 468 case ENGINE_ID_DIGE: 469 return DCE110_DIG_FE_SOURCE_SELECT_DIGE; 470 case ENGINE_ID_DIGF: 471 return DCE110_DIG_FE_SOURCE_SELECT_DIGF; 472 case ENGINE_ID_DIGG: 473 return DCE110_DIG_FE_SOURCE_SELECT_DIGG; 474 default: 475 ASSERT_CRITICAL(false); 476 return DCE110_DIG_FE_SOURCE_SELECT_INVALID; 477 } 478 } 479 480 static void configure_encoder( 481 struct dce110_link_encoder *enc110, 482 const struct dc_link_settings *link_settings) 483 { 484 /* set number of lanes */ 485 486 REG_SET(DP_CONFIG, 0, 487 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 488 489 /* setup scrambler */ 490 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); 491 } 492 493 static void aux_initialize( 494 struct dce110_link_encoder *enc110) 495 { 496 struct dc_context *ctx = enc110->base.ctx; 497 enum hpd_source_id hpd_source = enc110->base.hpd_source; 498 uint32_t addr = AUX_REG(AUX_CONTROL); 499 uint32_t value = dm_read_reg(ctx, addr); 500 501 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); 502 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); 503 dm_write_reg(ctx, addr, value); 504 505 addr = AUX_REG(AUX_DPHY_RX_CONTROL0); 506 value = dm_read_reg(ctx, addr); 507 508 /* 1/4 window (the maximum allowed) */ 509 set_reg_field_value(value, 1, 510 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW); 511 dm_write_reg(ctx, addr, value); 512 513 } 514 515 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 516 bool exit_link_training_required) 517 { 518 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 519 520 if (exit_link_training_required) 521 REG_UPDATE(DP_DPHY_FAST_TRAINING, 522 DPHY_RX_FAST_TRAINING_CAPABLE, 1); 523 else { 524 REG_UPDATE(DP_DPHY_FAST_TRAINING, 525 DPHY_RX_FAST_TRAINING_CAPABLE, 0); 526 /*In DCE 11, we are able to pre-program a Force SR register 527 * to be able to trigger SR symbol after 5 idle patterns 528 * transmitted. Upon PSR Exit, DMCU can trigger 529 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to 530 * DPHY_LOAD_BS_COUNT_START and the internal counter 531 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be 532 * replaced by SR symbol once. 533 */ 534 535 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5); 536 } 537 } 538 539 void dce110_psr_program_secondary_packet(struct link_encoder *enc, 540 unsigned int sdp_transmit_line_num_deadline) 541 { 542 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 543 544 REG_UPDATE_2(DP_SEC_CNTL1, 545 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline, 546 DP_SEC_GSP0_PRIORITY, 1); 547 } 548 549 bool dce110_is_dig_enabled(struct link_encoder *enc) 550 { 551 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 552 uint32_t value; 553 554 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); 555 return value; 556 } 557 558 static void link_encoder_disable(struct dce110_link_encoder *enc110) 559 { 560 /* reset training pattern */ 561 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, 562 DPHY_TRAINING_PATTERN_SEL, 0); 563 564 /* reset training complete */ 565 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); 566 567 /* reset panel mode */ 568 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 569 } 570 571 static void hpd_initialize( 572 struct dce110_link_encoder *enc110) 573 { 574 /* Associate HPD with DIG_BE */ 575 enum hpd_source_id hpd_source = enc110->base.hpd_source; 576 577 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); 578 } 579 580 bool dce110_link_encoder_validate_dvi_output( 581 const struct dce110_link_encoder *enc110, 582 enum signal_type connector_signal, 583 enum signal_type signal, 584 const struct dc_crtc_timing *crtc_timing) 585 { 586 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; 587 588 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK) 589 max_pixel_clock *= 2; 590 591 /* This handles the case of HDMI downgrade to DVI we don't want to 592 * we don't want to cap the pixel clock if the DDI is not DVI. 593 */ 594 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK && 595 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 596 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock; 597 598 /* DVI only support RGB pixel encoding */ 599 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 600 return false; 601 602 /*connect DVI via adpater's HDMI connector*/ 603 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 604 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) && 605 signal != SIGNAL_TYPE_HDMI_TYPE_A && 606 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10)) 607 return false; 608 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) 609 return false; 610 611 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10)) 612 return false; 613 614 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */ 615 switch (crtc_timing->display_color_depth) { 616 case COLOR_DEPTH_666: 617 case COLOR_DEPTH_888: 618 break; 619 case COLOR_DEPTH_101010: 620 case COLOR_DEPTH_161616: 621 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK) 622 return false; 623 break; 624 default: 625 return false; 626 } 627 628 return true; 629 } 630 631 static bool dce110_link_encoder_validate_hdmi_output( 632 const struct dce110_link_encoder *enc110, 633 const struct dc_crtc_timing *crtc_timing, 634 int adjusted_pix_clk_khz) 635 { 636 enum dc_color_depth max_deep_color = 637 enc110->base.features.max_hdmi_deep_color; 638 639 if (max_deep_color < crtc_timing->display_color_depth) 640 return false; 641 642 if (crtc_timing->display_color_depth < COLOR_DEPTH_888) 643 return false; 644 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK) 645 return false; 646 647 if ((adjusted_pix_clk_khz == 0) || 648 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) 649 return false; 650 651 /* DCE11 HW does not support 420 */ 652 if (!enc110->base.features.hdmi_ycbcr420_supported && 653 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 654 return false; 655 656 if (!enc110->base.features.flags.bits.HDMI_6GB_EN && 657 adjusted_pix_clk_khz >= 300000) 658 return false; 659 if (enc110->base.ctx->dc->debug.hdmi20_disable && 660 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 661 return false; 662 return true; 663 } 664 665 bool dce110_link_encoder_validate_dp_output( 666 const struct dce110_link_encoder *enc110, 667 const struct dc_crtc_timing *crtc_timing) 668 { 669 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 670 return false; 671 672 return true; 673 } 674 675 void dce110_link_encoder_construct( 676 struct dce110_link_encoder *enc110, 677 const struct encoder_init_data *init_data, 678 const struct encoder_feature_support *enc_features, 679 const struct dce110_link_enc_registers *link_regs, 680 const struct dce110_link_enc_aux_registers *aux_regs, 681 const struct dce110_link_enc_hpd_registers *hpd_regs) 682 { 683 struct bp_encoder_cap_info bp_cap_info = {0}; 684 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 685 enum bp_result result = BP_RESULT_OK; 686 687 enc110->base.funcs = &dce110_lnk_enc_funcs; 688 enc110->base.ctx = init_data->ctx; 689 enc110->base.id = init_data->encoder; 690 691 enc110->base.hpd_source = init_data->hpd_source; 692 enc110->base.connector = init_data->connector; 693 694 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 695 696 enc110->base.features = *enc_features; 697 698 enc110->base.transmitter = init_data->transmitter; 699 700 /* set the flag to indicate whether driver poll the I2C data pin 701 * while doing the DP sink detect 702 */ 703 704 /* if (dal_adapter_service_is_feature_supported(as, 705 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 706 enc110->base.features.flags.bits. 707 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 708 709 enc110->base.output_signals = 710 SIGNAL_TYPE_DVI_SINGLE_LINK | 711 SIGNAL_TYPE_DVI_DUAL_LINK | 712 SIGNAL_TYPE_LVDS | 713 SIGNAL_TYPE_DISPLAY_PORT | 714 SIGNAL_TYPE_DISPLAY_PORT_MST | 715 SIGNAL_TYPE_EDP | 716 SIGNAL_TYPE_HDMI_TYPE_A; 717 718 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 719 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 720 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 721 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 722 * Prefer DIG assignment is decided by board design. 723 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 724 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 725 * By this, adding DIGG should not hurt DCE 8.0. 726 * This will let DCE 8.1 share DCE 8.0 as much as possible 727 */ 728 729 enc110->link_regs = link_regs; 730 enc110->aux_regs = aux_regs; 731 enc110->hpd_regs = hpd_regs; 732 733 switch (enc110->base.transmitter) { 734 case TRANSMITTER_UNIPHY_A: 735 enc110->base.preferred_engine = ENGINE_ID_DIGA; 736 break; 737 case TRANSMITTER_UNIPHY_B: 738 enc110->base.preferred_engine = ENGINE_ID_DIGB; 739 break; 740 case TRANSMITTER_UNIPHY_C: 741 enc110->base.preferred_engine = ENGINE_ID_DIGC; 742 break; 743 case TRANSMITTER_UNIPHY_D: 744 enc110->base.preferred_engine = ENGINE_ID_DIGD; 745 break; 746 case TRANSMITTER_UNIPHY_E: 747 enc110->base.preferred_engine = ENGINE_ID_DIGE; 748 break; 749 case TRANSMITTER_UNIPHY_F: 750 enc110->base.preferred_engine = ENGINE_ID_DIGF; 751 break; 752 case TRANSMITTER_UNIPHY_G: 753 enc110->base.preferred_engine = ENGINE_ID_DIGG; 754 break; 755 default: 756 ASSERT_CRITICAL(false); 757 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 758 } 759 760 /* default to one to mirror Windows behavior */ 761 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 762 763 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 764 enc110->base.id, &bp_cap_info); 765 766 /* Override features with DCE-specific values */ 767 if (BP_RESULT_OK == result) { 768 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 769 bp_cap_info.DP_HBR2_EN; 770 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 771 bp_cap_info.DP_HBR3_EN; 772 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 773 } else { 774 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 775 __func__, 776 result); 777 } 778 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 779 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 780 } 781 } 782 783 bool dce110_link_encoder_validate_output_with_stream( 784 struct link_encoder *enc, 785 const struct dc_stream_state *stream) 786 { 787 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 788 bool is_valid; 789 790 switch (stream->signal) { 791 case SIGNAL_TYPE_DVI_SINGLE_LINK: 792 case SIGNAL_TYPE_DVI_DUAL_LINK: 793 is_valid = dce110_link_encoder_validate_dvi_output( 794 enc110, 795 stream->link->connector_signal, 796 stream->signal, 797 &stream->timing); 798 break; 799 case SIGNAL_TYPE_HDMI_TYPE_A: 800 is_valid = dce110_link_encoder_validate_hdmi_output( 801 enc110, 802 &stream->timing, 803 stream->phy_pix_clk); 804 break; 805 case SIGNAL_TYPE_DISPLAY_PORT: 806 case SIGNAL_TYPE_DISPLAY_PORT_MST: 807 is_valid = dce110_link_encoder_validate_dp_output( 808 enc110, &stream->timing); 809 break; 810 case SIGNAL_TYPE_EDP: 811 case SIGNAL_TYPE_LVDS: 812 is_valid = 813 (stream->timing. 814 pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; 815 break; 816 case SIGNAL_TYPE_VIRTUAL: 817 is_valid = true; 818 break; 819 default: 820 is_valid = false; 821 break; 822 } 823 824 return is_valid; 825 } 826 827 void dce110_link_encoder_hw_init( 828 struct link_encoder *enc) 829 { 830 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 831 struct bp_transmitter_control cntl = { 0 }; 832 enum bp_result result; 833 834 cntl.action = TRANSMITTER_CONTROL_INIT; 835 cntl.engine_id = ENGINE_ID_UNKNOWN; 836 cntl.transmitter = enc110->base.transmitter; 837 cntl.connector_obj_id = enc110->base.connector; 838 cntl.lanes_number = LANE_COUNT_FOUR; 839 cntl.coherent = false; 840 cntl.hpd_sel = enc110->base.hpd_source; 841 842 if (enc110->base.connector.id == CONNECTOR_ID_EDP) 843 cntl.signal = SIGNAL_TYPE_EDP; 844 845 result = link_transmitter_control(enc110, &cntl); 846 847 if (result != BP_RESULT_OK) { 848 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 849 __func__); 850 BREAK_TO_DEBUGGER(); 851 return; 852 } 853 854 if (enc110->base.connector.id == CONNECTOR_ID_LVDS) { 855 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS; 856 857 result = link_transmitter_control(enc110, &cntl); 858 859 ASSERT(result == BP_RESULT_OK); 860 861 } 862 aux_initialize(enc110); 863 864 /* reinitialize HPD. 865 * hpd_initialize() will pass DIG_FE id to HW context. 866 * All other routine within HW context will use fe_engine_offset 867 * as DIG_FE id even caller pass DIG_FE id. 868 * So this routine must be called first. */ 869 hpd_initialize(enc110); 870 } 871 872 void dce110_link_encoder_destroy(struct link_encoder **enc) 873 { 874 kfree(TO_DCE110_LINK_ENC(*enc)); 875 *enc = NULL; 876 } 877 878 void dce110_link_encoder_setup( 879 struct link_encoder *enc, 880 enum signal_type signal) 881 { 882 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 883 884 switch (signal) { 885 case SIGNAL_TYPE_EDP: 886 case SIGNAL_TYPE_DISPLAY_PORT: 887 /* DP SST */ 888 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); 889 break; 890 case SIGNAL_TYPE_LVDS: 891 /* LVDS */ 892 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); 893 break; 894 case SIGNAL_TYPE_DVI_SINGLE_LINK: 895 case SIGNAL_TYPE_DVI_DUAL_LINK: 896 /* TMDS-DVI */ 897 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); 898 break; 899 case SIGNAL_TYPE_HDMI_TYPE_A: 900 /* TMDS-HDMI */ 901 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); 902 break; 903 case SIGNAL_TYPE_DISPLAY_PORT_MST: 904 /* DP MST */ 905 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); 906 break; 907 default: 908 ASSERT_CRITICAL(false); 909 /* invalid mode ! */ 910 break; 911 } 912 913 } 914 915 /* TODO: still need depth or just pass in adjusted pixel clock? */ 916 void dce110_link_encoder_enable_tmds_output( 917 struct link_encoder *enc, 918 enum clock_source_id clock_source, 919 enum dc_color_depth color_depth, 920 enum signal_type signal, 921 uint32_t pixel_clock) 922 { 923 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 924 struct bp_transmitter_control cntl = { 0 }; 925 enum bp_result result; 926 927 /* Enable the PHY */ 928 cntl.connector_obj_id = enc110->base.connector; 929 cntl.action = TRANSMITTER_CONTROL_ENABLE; 930 cntl.engine_id = enc->preferred_engine; 931 cntl.transmitter = enc110->base.transmitter; 932 cntl.pll_id = clock_source; 933 cntl.signal = signal; 934 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK) 935 cntl.lanes_number = 8; 936 else 937 cntl.lanes_number = 4; 938 939 cntl.hpd_sel = enc110->base.hpd_source; 940 941 cntl.pixel_clock = pixel_clock; 942 cntl.color_depth = color_depth; 943 944 result = link_transmitter_control(enc110, &cntl); 945 946 if (result != BP_RESULT_OK) { 947 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 948 __func__); 949 BREAK_TO_DEBUGGER(); 950 } 951 } 952 953 /* TODO: still need depth or just pass in adjusted pixel clock? */ 954 void dce110_link_encoder_enable_lvds_output( 955 struct link_encoder *enc, 956 enum clock_source_id clock_source, 957 uint32_t pixel_clock) 958 { 959 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 960 struct bp_transmitter_control cntl = { 0 }; 961 enum bp_result result; 962 963 /* Enable the PHY */ 964 cntl.connector_obj_id = enc110->base.connector; 965 cntl.action = TRANSMITTER_CONTROL_ENABLE; 966 cntl.engine_id = enc->preferred_engine; 967 cntl.transmitter = enc110->base.transmitter; 968 cntl.pll_id = clock_source; 969 cntl.signal = SIGNAL_TYPE_LVDS; 970 cntl.lanes_number = 4; 971 972 cntl.hpd_sel = enc110->base.hpd_source; 973 974 cntl.pixel_clock = pixel_clock; 975 976 result = link_transmitter_control(enc110, &cntl); 977 978 if (result != BP_RESULT_OK) { 979 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 980 __func__); 981 BREAK_TO_DEBUGGER(); 982 } 983 } 984 985 /* enables DP PHY output */ 986 void dce110_link_encoder_enable_dp_output( 987 struct link_encoder *enc, 988 const struct dc_link_settings *link_settings, 989 enum clock_source_id clock_source) 990 { 991 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 992 struct bp_transmitter_control cntl = { 0 }; 993 enum bp_result result; 994 995 /* Enable the PHY */ 996 997 /* number_of_lanes is used for pixel clock adjust, 998 * but it's not passed to asic_control. 999 * We need to set number of lanes manually. 1000 */ 1001 configure_encoder(enc110, link_settings); 1002 cntl.connector_obj_id = enc110->base.connector; 1003 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1004 cntl.engine_id = enc->preferred_engine; 1005 cntl.transmitter = enc110->base.transmitter; 1006 cntl.pll_id = clock_source; 1007 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1008 cntl.lanes_number = link_settings->lane_count; 1009 cntl.hpd_sel = enc110->base.hpd_source; 1010 cntl.pixel_clock = link_settings->link_rate 1011 * LINK_RATE_REF_FREQ_IN_KHZ; 1012 /* TODO: check if undefined works */ 1013 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1014 1015 result = link_transmitter_control(enc110, &cntl); 1016 1017 if (result != BP_RESULT_OK) { 1018 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1019 __func__); 1020 BREAK_TO_DEBUGGER(); 1021 } 1022 } 1023 1024 /* enables DP PHY output in MST mode */ 1025 void dce110_link_encoder_enable_dp_mst_output( 1026 struct link_encoder *enc, 1027 const struct dc_link_settings *link_settings, 1028 enum clock_source_id clock_source) 1029 { 1030 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1031 struct bp_transmitter_control cntl = { 0 }; 1032 enum bp_result result; 1033 1034 /* Enable the PHY */ 1035 1036 /* number_of_lanes is used for pixel clock adjust, 1037 * but it's not passed to asic_control. 1038 * We need to set number of lanes manually. 1039 */ 1040 configure_encoder(enc110, link_settings); 1041 1042 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1043 cntl.engine_id = ENGINE_ID_UNKNOWN; 1044 cntl.transmitter = enc110->base.transmitter; 1045 cntl.pll_id = clock_source; 1046 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1047 cntl.lanes_number = link_settings->lane_count; 1048 cntl.hpd_sel = enc110->base.hpd_source; 1049 cntl.pixel_clock = link_settings->link_rate 1050 * LINK_RATE_REF_FREQ_IN_KHZ; 1051 /* TODO: check if undefined works */ 1052 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1053 1054 result = link_transmitter_control(enc110, &cntl); 1055 1056 if (result != BP_RESULT_OK) { 1057 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1058 __func__); 1059 BREAK_TO_DEBUGGER(); 1060 } 1061 } 1062 /* 1063 * @brief 1064 * Disable transmitter and its encoder 1065 */ 1066 void dce110_link_encoder_disable_output( 1067 struct link_encoder *enc, 1068 enum signal_type signal) 1069 { 1070 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1071 struct bp_transmitter_control cntl = { 0 }; 1072 enum bp_result result; 1073 1074 if (!dce110_is_dig_enabled(enc)) { 1075 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ 1076 return; 1077 } 1078 /* Power-down RX and disable GPU PHY should be paired. 1079 * Disabling PHY without powering down RX may cause 1080 * symbol lock loss, on which we will get DP Sink interrupt. */ 1081 1082 /* There is a case for the DP active dongles 1083 * where we want to disable the PHY but keep RX powered, 1084 * for those we need to ignore DP Sink interrupt 1085 * by checking lane count that has been set 1086 * on the last do_enable_output(). */ 1087 1088 /* disable transmitter */ 1089 cntl.action = TRANSMITTER_CONTROL_DISABLE; 1090 cntl.transmitter = enc110->base.transmitter; 1091 cntl.hpd_sel = enc110->base.hpd_source; 1092 cntl.signal = signal; 1093 cntl.connector_obj_id = enc110->base.connector; 1094 1095 result = link_transmitter_control(enc110, &cntl); 1096 1097 if (result != BP_RESULT_OK) { 1098 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1099 __func__); 1100 BREAK_TO_DEBUGGER(); 1101 return; 1102 } 1103 1104 /* disable encoder */ 1105 if (dc_is_dp_signal(signal)) 1106 link_encoder_disable(enc110); 1107 } 1108 1109 void dce110_link_encoder_dp_set_lane_settings( 1110 struct link_encoder *enc, 1111 const struct link_training_settings *link_settings) 1112 { 1113 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1114 union dpcd_training_lane_set training_lane_set = { { 0 } }; 1115 int32_t lane = 0; 1116 struct bp_transmitter_control cntl = { 0 }; 1117 1118 if (!link_settings) { 1119 BREAK_TO_DEBUGGER(); 1120 return; 1121 } 1122 1123 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1124 cntl.transmitter = enc110->base.transmitter; 1125 cntl.connector_obj_id = enc110->base.connector; 1126 cntl.lanes_number = link_settings->link_settings.lane_count; 1127 cntl.hpd_sel = enc110->base.hpd_source; 1128 cntl.pixel_clock = link_settings->link_settings.link_rate * 1129 LINK_RATE_REF_FREQ_IN_KHZ; 1130 1131 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { 1132 /* translate lane settings */ 1133 1134 training_lane_set.bits.VOLTAGE_SWING_SET = 1135 link_settings->lane_settings[lane].VOLTAGE_SWING; 1136 training_lane_set.bits.PRE_EMPHASIS_SET = 1137 link_settings->lane_settings[lane].PRE_EMPHASIS; 1138 1139 /* post cursor 2 setting only applies to HBR2 link rate */ 1140 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { 1141 /* this is passed to VBIOS 1142 * to program post cursor 2 level */ 1143 1144 training_lane_set.bits.POST_CURSOR2_SET = 1145 link_settings->lane_settings[lane].POST_CURSOR2; 1146 } 1147 1148 cntl.lane_select = lane; 1149 cntl.lane_settings = training_lane_set.raw; 1150 1151 /* call VBIOS table to set voltage swing and pre-emphasis */ 1152 link_transmitter_control(enc110, &cntl); 1153 } 1154 } 1155 1156 /* set DP PHY test and training patterns */ 1157 void dce110_link_encoder_dp_set_phy_pattern( 1158 struct link_encoder *enc, 1159 const struct encoder_set_dp_phy_pattern_param *param) 1160 { 1161 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1162 1163 switch (param->dp_phy_pattern) { 1164 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1165 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1166 break; 1167 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1168 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1169 break; 1170 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1171 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1172 break; 1173 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1174 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1175 break; 1176 case DP_TEST_PATTERN_D102: 1177 set_dp_phy_pattern_d102(enc110); 1178 break; 1179 case DP_TEST_PATTERN_SYMBOL_ERROR: 1180 set_dp_phy_pattern_symbol_error(enc110); 1181 break; 1182 case DP_TEST_PATTERN_PRBS7: 1183 set_dp_phy_pattern_prbs7(enc110); 1184 break; 1185 case DP_TEST_PATTERN_80BIT_CUSTOM: 1186 set_dp_phy_pattern_80bit_custom( 1187 enc110, param->custom_pattern); 1188 break; 1189 case DP_TEST_PATTERN_CP2520_1: 1190 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1191 break; 1192 case DP_TEST_PATTERN_CP2520_2: 1193 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1194 break; 1195 case DP_TEST_PATTERN_CP2520_3: 1196 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1197 break; 1198 case DP_TEST_PATTERN_VIDEO_MODE: { 1199 set_dp_phy_pattern_passthrough_mode( 1200 enc110, param->dp_panel_mode); 1201 break; 1202 } 1203 1204 default: 1205 /* invalid phy pattern */ 1206 ASSERT_CRITICAL(false); 1207 break; 1208 } 1209 } 1210 1211 static void fill_stream_allocation_row_info( 1212 const struct link_mst_stream_allocation *stream_allocation, 1213 uint32_t *src, 1214 uint32_t *slots) 1215 { 1216 const struct stream_encoder *stream_enc = stream_allocation->stream_enc; 1217 1218 if (stream_enc) { 1219 *src = stream_enc->id; 1220 *slots = stream_allocation->slot_count; 1221 } else { 1222 *src = 0; 1223 *slots = 0; 1224 } 1225 } 1226 1227 /* programs DP MST VC payload allocation */ 1228 void dce110_link_encoder_update_mst_stream_allocation_table( 1229 struct link_encoder *enc, 1230 const struct link_mst_stream_allocation_table *table) 1231 { 1232 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1233 uint32_t value0 = 0; 1234 uint32_t value1 = 0; 1235 uint32_t value2 = 0; 1236 uint32_t slots = 0; 1237 uint32_t src = 0; 1238 uint32_t retries = 0; 1239 1240 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/ 1241 1242 /* --- Set MSE Stream Attribute - 1243 * Setup VC Payload Table on Tx Side, 1244 * Issue allocation change trigger 1245 * to commit payload on both tx and rx side */ 1246 1247 /* we should clean-up table each time */ 1248 1249 if (table->stream_count >= 1) { 1250 fill_stream_allocation_row_info( 1251 &table->stream_allocations[0], 1252 &src, 1253 &slots); 1254 } else { 1255 src = 0; 1256 slots = 0; 1257 } 1258 1259 REG_UPDATE_2(DP_MSE_SAT0, 1260 DP_MSE_SAT_SRC0, src, 1261 DP_MSE_SAT_SLOT_COUNT0, slots); 1262 1263 if (table->stream_count >= 2) { 1264 fill_stream_allocation_row_info( 1265 &table->stream_allocations[1], 1266 &src, 1267 &slots); 1268 } else { 1269 src = 0; 1270 slots = 0; 1271 } 1272 1273 REG_UPDATE_2(DP_MSE_SAT0, 1274 DP_MSE_SAT_SRC1, src, 1275 DP_MSE_SAT_SLOT_COUNT1, slots); 1276 1277 if (table->stream_count >= 3) { 1278 fill_stream_allocation_row_info( 1279 &table->stream_allocations[2], 1280 &src, 1281 &slots); 1282 } else { 1283 src = 0; 1284 slots = 0; 1285 } 1286 1287 REG_UPDATE_2(DP_MSE_SAT1, 1288 DP_MSE_SAT_SRC2, src, 1289 DP_MSE_SAT_SLOT_COUNT2, slots); 1290 1291 if (table->stream_count >= 4) { 1292 fill_stream_allocation_row_info( 1293 &table->stream_allocations[3], 1294 &src, 1295 &slots); 1296 } else { 1297 src = 0; 1298 slots = 0; 1299 } 1300 1301 REG_UPDATE_2(DP_MSE_SAT1, 1302 DP_MSE_SAT_SRC3, src, 1303 DP_MSE_SAT_SLOT_COUNT3, slots); 1304 1305 /* --- wait for transaction finish */ 1306 1307 /* send allocation change trigger (ACT) ? 1308 * this step first sends the ACT, 1309 * then double buffers the SAT into the hardware 1310 * making the new allocation active on the DP MST mode link */ 1311 1312 1313 /* DP_MSE_SAT_UPDATE: 1314 * 0 - No Action 1315 * 1 - Update SAT with trigger 1316 * 2 - Update SAT without trigger */ 1317 1318 REG_UPDATE(DP_MSE_SAT_UPDATE, 1319 DP_MSE_SAT_UPDATE, 1); 1320 1321 /* wait for update to complete 1322 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0) 1323 * then wait for the transmission 1324 * of at least 16 MTP headers on immediate local link. 1325 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0 1326 * a value of 1 indicates that DP MST mode 1327 * is in the 16 MTP keepout region after a VC has been added. 1328 * MST stream bandwidth (VC rate) can be configured 1329 * after this bit is cleared */ 1330 1331 do { 1332 udelay(10); 1333 1334 value0 = REG_READ(DP_MSE_SAT_UPDATE); 1335 1336 REG_GET(DP_MSE_SAT_UPDATE, 1337 DP_MSE_SAT_UPDATE, &value1); 1338 1339 REG_GET(DP_MSE_SAT_UPDATE, 1340 DP_MSE_16_MTP_KEEPOUT, &value2); 1341 1342 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */ 1343 if (!value1 && !value2) 1344 break; 1345 ++retries; 1346 } while (retries < DP_MST_UPDATE_MAX_RETRY); 1347 } 1348 1349 void dce110_link_encoder_connect_dig_be_to_fe( 1350 struct link_encoder *enc, 1351 enum engine_id engine, 1352 bool connect) 1353 { 1354 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1355 uint32_t field; 1356 1357 if (engine != ENGINE_ID_UNKNOWN) { 1358 1359 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); 1360 1361 if (connect) 1362 field |= get_frontend_source(engine); 1363 else 1364 field &= ~get_frontend_source(engine); 1365 1366 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); 1367 } 1368 } 1369 1370 void dce110_link_encoder_enable_hpd(struct link_encoder *enc) 1371 { 1372 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1373 struct dc_context *ctx = enc110->base.ctx; 1374 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1375 uint32_t hpd_enable = 0; 1376 uint32_t value = dm_read_reg(ctx, addr); 1377 1378 get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN); 1379 1380 if (hpd_enable == 0) 1381 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); 1382 } 1383 1384 void dce110_link_encoder_disable_hpd(struct link_encoder *enc) 1385 { 1386 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1387 struct dc_context *ctx = enc110->base.ctx; 1388 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1389 uint32_t value = dm_read_reg(ctx, addr); 1390 1391 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); 1392 } 1393 1394 void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc, 1395 struct dc_link_settings *link_settings) 1396 { 1397 /* Set Default link settings */ 1398 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, 1399 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0}; 1400 1401 /* Higher link settings based on feature supported */ 1402 if (enc->features.flags.bits.IS_HBR2_CAPABLE) 1403 max_link_cap.link_rate = LINK_RATE_HIGH2; 1404 1405 if (enc->features.flags.bits.IS_HBR3_CAPABLE) 1406 max_link_cap.link_rate = LINK_RATE_HIGH3; 1407 1408 *link_settings = max_link_cap; 1409 } 1410