1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce_ipp.h" 27 #include "reg_helper.h" 28 #include "dm_services.h" 29 30 #define REG(reg) \ 31 (ipp_dce->regs->reg) 32 33 #undef FN 34 #define FN(reg_name, field_name) \ 35 ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name 36 37 #define CTX \ 38 ipp_dce->base.ctx 39 40 static void dce_ipp_cursor_set_position( 41 struct input_pixel_processor *ipp, 42 const struct dc_cursor_position *position, 43 const struct dc_cursor_mi_param *param) 44 { 45 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 46 47 /* lock cursor registers */ 48 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); 49 50 /* Flag passed in structure differentiates cursor enable/disable. */ 51 /* Update if it differs from cached state. */ 52 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); 53 54 REG_SET_2(CUR_POSITION, 0, 55 CURSOR_X_POSITION, position->x, 56 CURSOR_Y_POSITION, position->y); 57 58 REG_SET_2(CUR_HOT_SPOT, 0, 59 CURSOR_HOT_SPOT_X, position->x_hotspot, 60 CURSOR_HOT_SPOT_Y, position->y_hotspot); 61 62 /* unlock cursor registers */ 63 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); 64 } 65 66 static void dce_ipp_cursor_set_attributes( 67 struct input_pixel_processor *ipp, 68 const struct dc_cursor_attributes *attributes) 69 { 70 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 71 int mode; 72 73 /* Lock cursor registers */ 74 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); 75 76 /* Program cursor control */ 77 switch (attributes->color_format) { 78 case CURSOR_MODE_MONO: 79 mode = 0; 80 break; 81 case CURSOR_MODE_COLOR_1BIT_AND: 82 mode = 1; 83 break; 84 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 85 mode = 2; 86 break; 87 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 88 mode = 3; 89 break; 90 default: 91 BREAK_TO_DEBUGGER(); /* unsupported */ 92 mode = 0; 93 } 94 95 REG_UPDATE_3(CUR_CONTROL, 96 CURSOR_MODE, mode, 97 CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, 98 CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); 99 100 if (attributes->color_format == CURSOR_MODE_MONO) { 101 REG_SET_3(CUR_COLOR1, 0, 102 CUR_COLOR1_BLUE, 0, 103 CUR_COLOR1_GREEN, 0, 104 CUR_COLOR1_RED, 0); 105 106 REG_SET_3(CUR_COLOR2, 0, 107 CUR_COLOR2_BLUE, 0xff, 108 CUR_COLOR2_GREEN, 0xff, 109 CUR_COLOR2_RED, 0xff); 110 } 111 112 /* 113 * Program cursor size -- NOTE: HW spec specifies that HW register 114 * stores size as (height - 1, width - 1) 115 */ 116 REG_SET_2(CUR_SIZE, 0, 117 CURSOR_WIDTH, attributes->width-1, 118 CURSOR_HEIGHT, attributes->height-1); 119 120 /* Program cursor surface address */ 121 /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor 122 * surface base address in byte. It is 4K byte aligned. 123 * The correct way to program cursor surface address is to first write 124 * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS 125 */ 126 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, 127 CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part); 128 129 REG_SET(CUR_SURFACE_ADDRESS, 0, 130 CURSOR_SURFACE_ADDRESS, attributes->address.low_part); 131 132 /* Unlock Cursor registers. */ 133 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); 134 } 135 136 static void dce_ipp_program_prescale( 137 struct input_pixel_processor *ipp, 138 struct ipp_prescale_params *params) 139 { 140 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 141 142 /* set to bypass mode first before change */ 143 REG_UPDATE(PRESCALE_GRPH_CONTROL, 144 GRPH_PRESCALE_BYPASS, 145 1); 146 147 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, 148 GRPH_PRESCALE_SCALE_R, params->scale, 149 GRPH_PRESCALE_BIAS_R, params->bias); 150 151 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, 152 GRPH_PRESCALE_SCALE_G, params->scale, 153 GRPH_PRESCALE_BIAS_G, params->bias); 154 155 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, 156 GRPH_PRESCALE_SCALE_B, params->scale, 157 GRPH_PRESCALE_BIAS_B, params->bias); 158 159 if (params->mode != IPP_PRESCALE_MODE_BYPASS) { 160 REG_UPDATE(PRESCALE_GRPH_CONTROL, 161 GRPH_PRESCALE_BYPASS, 0); 162 163 /* If prescale is in use, then legacy lut should be bypassed */ 164 REG_UPDATE(INPUT_GAMMA_CONTROL, 165 GRPH_INPUT_GAMMA_MODE, 1); 166 } 167 } 168 169 static void dce_ipp_program_input_lut( 170 struct input_pixel_processor *ipp, 171 const struct dc_gamma *gamma) 172 { 173 int i; 174 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 175 176 /* power on LUT memory */ 177 if (REG(DCFE_MEM_PWR_CTRL)) 178 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); 179 180 /* enable all */ 181 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); 182 183 /* 256 entry mode */ 184 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); 185 186 /* LUT-256, unsigned, integer, new u0.12 format */ 187 REG_SET_3(DC_LUT_CONTROL, 0, 188 DC_LUT_DATA_R_FORMAT, 3, 189 DC_LUT_DATA_G_FORMAT, 3, 190 DC_LUT_DATA_B_FORMAT, 3); 191 192 /* start from index 0 */ 193 REG_SET(DC_LUT_RW_INDEX, 0, 194 DC_LUT_RW_INDEX, 0); 195 196 for (i = 0; i < gamma->num_entries; i++) { 197 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, 198 dal_fixed31_32_round( 199 gamma->entries.red[i])); 200 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, 201 dal_fixed31_32_round( 202 gamma->entries.green[i])); 203 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, 204 dal_fixed31_32_round( 205 gamma->entries.blue[i])); 206 } 207 208 /* power off LUT memory */ 209 if (REG(DCFE_MEM_PWR_CTRL)) 210 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); 211 212 /* bypass prescale, enable legacy LUT */ 213 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 214 REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 215 } 216 217 static void dce_ipp_set_degamma( 218 struct input_pixel_processor *ipp, 219 enum ipp_degamma_mode mode) 220 { 221 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); 222 uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; 223 224 ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || 225 mode == IPP_DEGAMMA_MODE_HW_sRGB); 226 227 REG_SET_3(DEGAMMA_CONTROL, 0, 228 GRPH_DEGAMMA_MODE, degamma_type, 229 CURSOR_DEGAMMA_MODE, degamma_type, 230 CURSOR2_DEGAMMA_MODE, degamma_type); 231 } 232 233 static const struct ipp_funcs dce_ipp_funcs = { 234 .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes, 235 .ipp_cursor_set_position = dce_ipp_cursor_set_position, 236 .ipp_program_prescale = dce_ipp_program_prescale, 237 .ipp_program_input_lut = dce_ipp_program_input_lut, 238 .ipp_set_degamma = dce_ipp_set_degamma 239 }; 240 241 /*****************************************/ 242 /* Constructor, Destructor */ 243 /*****************************************/ 244 245 void dce_ipp_construct( 246 struct dce_ipp *ipp_dce, 247 struct dc_context *ctx, 248 int inst, 249 const struct dce_ipp_registers *regs, 250 const struct dce_ipp_shift *ipp_shift, 251 const struct dce_ipp_mask *ipp_mask) 252 { 253 ipp_dce->base.ctx = ctx; 254 ipp_dce->base.inst = inst; 255 ipp_dce->base.funcs = &dce_ipp_funcs; 256 257 ipp_dce->regs = regs; 258 ipp_dce->ipp_shift = ipp_shift; 259 ipp_dce->ipp_mask = ipp_mask; 260 } 261 262 void dce_ipp_destroy(struct input_pixel_processor **ipp) 263 { 264 dm_free(TO_DCE_IPP(*ipp)); 265 *ipp = NULL; 266 } 267