1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DCE_I2C_HW_H__ 27 #define __DCE_I2C_HW_H__ 28 29 enum dc_i2c_status { 30 DC_I2C_STATUS__DC_I2C_STATUS_IDLE, 31 DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW, 32 DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW, 33 DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY = 2, 34 }; 35 36 enum dc_i2c_arbitration { 37 DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL, 38 DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH 39 }; 40 41 enum i2c_channel_operation_result { 42 I2C_CHANNEL_OPERATION_SUCCEEDED, 43 I2C_CHANNEL_OPERATION_FAILED, 44 I2C_CHANNEL_OPERATION_NOT_GRANTED, 45 I2C_CHANNEL_OPERATION_IS_BUSY, 46 I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED, 47 I2C_CHANNEL_OPERATION_CHANNEL_IN_USE, 48 I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED, 49 I2C_CHANNEL_OPERATION_ENGINE_BUSY, 50 I2C_CHANNEL_OPERATION_TIMEOUT, 51 I2C_CHANNEL_OPERATION_NO_RESPONSE, 52 I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS, 53 I2C_CHANNEL_OPERATION_WRONG_PARAMETER, 54 I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES, 55 I2C_CHANNEL_OPERATION_NOT_STARTED 56 }; 57 58 59 enum dce_i2c_transaction_action { 60 DCE_I2C_TRANSACTION_ACTION_I2C_WRITE = 0x00, 61 DCE_I2C_TRANSACTION_ACTION_I2C_READ = 0x10, 62 DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20, 63 64 DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40, 65 DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT = 0x50, 66 DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60, 67 68 DCE_I2C_TRANSACTION_ACTION_DP_WRITE = 0x80, 69 DCE_I2C_TRANSACTION_ACTION_DP_READ = 0x90 70 }; 71 72 enum { 73 I2C_SETUP_TIME_LIMIT_DCE = 255, 74 I2C_SETUP_TIME_LIMIT_DCN = 3, 75 I2C_HW_BUFFER_SIZE_DCE100 = 538, 76 I2C_HW_BUFFER_SIZE_DCE = 144, 77 I2C_SEND_RESET_LENGTH_9 = 9, 78 I2C_SEND_RESET_LENGTH_10 = 10, 79 DEFAULT_I2C_HW_SPEED = 50, 80 DEFAULT_I2C_HW_SPEED_100KHZ = 100, 81 TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32, 82 }; 83 84 #define I2C_HW_ENGINE_COMMON_REG_LIST(id)\ 85 SRI(SETUP, DC_I2C_DDC, id),\ 86 SRI(SPEED, DC_I2C_DDC, id),\ 87 SRI(HW_STATUS, DC_I2C_DDC, id),\ 88 SR(DC_I2C_ARBITRATION),\ 89 SR(DC_I2C_CONTROL),\ 90 SR(DC_I2C_SW_STATUS),\ 91 SR(DC_I2C_TRANSACTION0),\ 92 SR(DC_I2C_TRANSACTION1),\ 93 SR(DC_I2C_TRANSACTION2),\ 94 SR(DC_I2C_TRANSACTION3),\ 95 SR(DC_I2C_DATA),\ 96 SR(MICROSECOND_TIME_BASE_DIV) 97 98 #define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id)\ 99 I2C_HW_ENGINE_COMMON_REG_LIST(id),\ 100 SR(DIO_MEM_PWR_CTRL),\ 101 SR(DIO_MEM_PWR_STATUS) 102 103 #define I2C_SF(reg_name, field_name, post_fix)\ 104 .field_name = reg_name ## __ ## field_name ## post_fix 105 106 #define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 107 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ 108 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\ 109 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\ 110 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\ 111 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\ 112 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\ 113 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\ 114 I2C_SF(DC_I2C_DDC1_HW_STATUS, DC_I2C_DDC1_HW_STATUS, mask_sh),\ 115 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, mask_sh),\ 116 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\ 117 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\ 118 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\ 119 I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\ 120 I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\ 121 I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\ 122 I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\ 123 I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\ 124 I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\ 125 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\ 126 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\ 127 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\ 128 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\ 129 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\ 130 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\ 131 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\ 132 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\ 133 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\ 134 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\ 135 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\ 136 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\ 137 I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\ 138 I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\ 139 I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\ 140 I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\ 141 I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\ 142 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh) 143 144 #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\ 145 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 146 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh) 147 148 struct dce_i2c_shift { 149 uint8_t DC_I2C_DDC1_ENABLE; 150 uint8_t DC_I2C_DDC1_TIME_LIMIT; 151 uint8_t DC_I2C_DDC1_DATA_DRIVE_EN; 152 uint8_t DC_I2C_DDC1_CLK_DRIVE_EN; 153 uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL; 154 uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY; 155 uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY; 156 uint8_t DC_I2C_DDC1_HW_STATUS; 157 uint8_t DC_I2C_SW_DONE_USING_I2C_REG; 158 uint8_t DC_I2C_SW_USE_I2C_REG_REQ; 159 uint8_t DC_I2C_NO_QUEUED_SW_GO; 160 uint8_t DC_I2C_SW_PRIORITY; 161 uint8_t DC_I2C_SOFT_RESET; 162 uint8_t DC_I2C_SW_STATUS_RESET; 163 uint8_t DC_I2C_GO; 164 uint8_t DC_I2C_SEND_RESET; 165 uint8_t DC_I2C_TRANSACTION_COUNT; 166 uint8_t DC_I2C_DDC_SELECT; 167 uint8_t DC_I2C_DDC1_PRESCALE; 168 uint8_t DC_I2C_DDC1_THRESHOLD; 169 uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL; 170 uint8_t DC_I2C_SW_STOPPED_ON_NACK; 171 uint8_t DC_I2C_SW_TIMEOUT; 172 uint8_t DC_I2C_SW_ABORTED; 173 uint8_t DC_I2C_SW_DONE; 174 uint8_t DC_I2C_SW_STATUS; 175 uint8_t DC_I2C_STOP_ON_NACK0; 176 uint8_t DC_I2C_START0; 177 uint8_t DC_I2C_RW0; 178 uint8_t DC_I2C_STOP0; 179 uint8_t DC_I2C_COUNT0; 180 uint8_t DC_I2C_DATA_RW; 181 uint8_t DC_I2C_DATA; 182 uint8_t DC_I2C_INDEX; 183 uint8_t DC_I2C_INDEX_WRITE; 184 uint8_t XTAL_REF_DIV; 185 uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH; 186 uint8_t DC_I2C_REG_RW_CNTL_STATUS; 187 uint8_t I2C_LIGHT_SLEEP_FORCE; 188 uint8_t I2C_MEM_PWR_STATE; 189 }; 190 191 struct dce_i2c_mask { 192 uint32_t DC_I2C_DDC1_ENABLE; 193 uint32_t DC_I2C_DDC1_TIME_LIMIT; 194 uint32_t DC_I2C_DDC1_DATA_DRIVE_EN; 195 uint32_t DC_I2C_DDC1_CLK_DRIVE_EN; 196 uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL; 197 uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY; 198 uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY; 199 uint32_t DC_I2C_DDC1_HW_STATUS; 200 uint32_t DC_I2C_SW_DONE_USING_I2C_REG; 201 uint32_t DC_I2C_SW_USE_I2C_REG_REQ; 202 uint32_t DC_I2C_NO_QUEUED_SW_GO; 203 uint32_t DC_I2C_SW_PRIORITY; 204 uint32_t DC_I2C_SOFT_RESET; 205 uint32_t DC_I2C_SW_STATUS_RESET; 206 uint32_t DC_I2C_GO; 207 uint32_t DC_I2C_SEND_RESET; 208 uint32_t DC_I2C_TRANSACTION_COUNT; 209 uint32_t DC_I2C_DDC_SELECT; 210 uint32_t DC_I2C_DDC1_PRESCALE; 211 uint32_t DC_I2C_DDC1_THRESHOLD; 212 uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL; 213 uint32_t DC_I2C_SW_STOPPED_ON_NACK; 214 uint32_t DC_I2C_SW_TIMEOUT; 215 uint32_t DC_I2C_SW_ABORTED; 216 uint32_t DC_I2C_SW_DONE; 217 uint32_t DC_I2C_SW_STATUS; 218 uint32_t DC_I2C_STOP_ON_NACK0; 219 uint32_t DC_I2C_START0; 220 uint32_t DC_I2C_RW0; 221 uint32_t DC_I2C_STOP0; 222 uint32_t DC_I2C_COUNT0; 223 uint32_t DC_I2C_DATA_RW; 224 uint32_t DC_I2C_DATA; 225 uint32_t DC_I2C_INDEX; 226 uint32_t DC_I2C_INDEX_WRITE; 227 uint32_t XTAL_REF_DIV; 228 uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH; 229 uint32_t DC_I2C_REG_RW_CNTL_STATUS; 230 uint32_t I2C_LIGHT_SLEEP_FORCE; 231 uint32_t I2C_MEM_PWR_STATE; 232 }; 233 234 #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\ 235 I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\ 236 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh) 237 238 #define I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh)\ 239 I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh),\ 240 I2C_SF(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh),\ 241 I2C_SF(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, mask_sh) 242 243 struct dce_i2c_registers { 244 uint32_t SETUP; 245 uint32_t SPEED; 246 uint32_t HW_STATUS; 247 uint32_t DC_I2C_ARBITRATION; 248 uint32_t DC_I2C_CONTROL; 249 uint32_t DC_I2C_SW_STATUS; 250 uint32_t DC_I2C_TRANSACTION0; 251 uint32_t DC_I2C_TRANSACTION1; 252 uint32_t DC_I2C_TRANSACTION2; 253 uint32_t DC_I2C_TRANSACTION3; 254 uint32_t DC_I2C_DATA; 255 uint32_t MICROSECOND_TIME_BASE_DIV; 256 uint32_t DIO_MEM_PWR_CTRL; 257 uint32_t DIO_MEM_PWR_STATUS; 258 }; 259 260 enum dce_i2c_transaction_address_space { 261 DCE_I2C_TRANSACTION_ADDRESS_SPACE_I2C = 1, 262 DCE_I2C_TRANSACTION_ADDRESS_SPACE_DPCD 263 }; 264 265 struct i2c_request_transaction_data { 266 enum dce_i2c_transaction_action action; 267 enum i2c_channel_operation_result status; 268 uint8_t address; 269 uint32_t length; 270 uint8_t *data; 271 }; 272 273 struct dce_i2c_hw { 274 struct ddc *ddc; 275 uint32_t engine_keep_power_up_count; 276 uint32_t transaction_count; 277 uint32_t buffer_used_bytes; 278 uint32_t buffer_used_write; 279 uint32_t reference_frequency; 280 uint32_t default_speed; 281 uint32_t engine_id; 282 uint32_t setup_limit; 283 uint32_t send_reset_length; 284 uint32_t buffer_size; 285 struct dc_context *ctx; 286 287 const struct dce_i2c_registers *regs; 288 const struct dce_i2c_shift *shifts; 289 const struct dce_i2c_mask *masks; 290 }; 291 292 void dce_i2c_hw_construct( 293 struct dce_i2c_hw *dce_i2c_hw, 294 struct dc_context *ctx, 295 uint32_t engine_id, 296 const struct dce_i2c_registers *regs, 297 const struct dce_i2c_shift *shifts, 298 const struct dce_i2c_mask *masks); 299 300 void dce100_i2c_hw_construct( 301 struct dce_i2c_hw *dce_i2c_hw, 302 struct dc_context *ctx, 303 uint32_t engine_id, 304 const struct dce_i2c_registers *regs, 305 const struct dce_i2c_shift *shifts, 306 const struct dce_i2c_mask *masks); 307 308 void dce112_i2c_hw_construct( 309 struct dce_i2c_hw *dce_i2c_hw, 310 struct dc_context *ctx, 311 uint32_t engine_id, 312 const struct dce_i2c_registers *regs, 313 const struct dce_i2c_shift *shifts, 314 const struct dce_i2c_mask *masks); 315 316 void dcn1_i2c_hw_construct( 317 struct dce_i2c_hw *dce_i2c_hw, 318 struct dc_context *ctx, 319 uint32_t engine_id, 320 const struct dce_i2c_registers *regs, 321 const struct dce_i2c_shift *shifts, 322 const struct dce_i2c_mask *masks); 323 324 void dcn2_i2c_hw_construct( 325 struct dce_i2c_hw *dce_i2c_hw, 326 struct dc_context *ctx, 327 uint32_t engine_id, 328 const struct dce_i2c_registers *regs, 329 const struct dce_i2c_shift *shifts, 330 const struct dce_i2c_mask *masks); 331 332 bool dce_i2c_submit_command_hw( 333 struct resource_pool *pool, 334 struct ddc *ddc, 335 struct i2c_command *cmd, 336 struct dce_i2c_hw *dce_i2c_hw); 337 338 struct dce_i2c_hw *acquire_i2c_hw_engine( 339 struct resource_pool *pool, 340 struct ddc *ddc); 341 342 #endif 343