1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "dc_types.h" 29 30 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 37 38 #define HWSEQ_DCEF_REG_LIST() \ 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 46 47 #define HWSEQ_BLND_REG_LIST() \ 48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 54 SRII(BLND_CONTROL, BLND, 0), \ 55 SRII(BLND_CONTROL, BLND, 1), \ 56 SRII(BLND_CONTROL, BLND, 2), \ 57 SRII(BLND_CONTROL, BLND, 3), \ 58 SRII(BLND_CONTROL, BLND, 4), \ 59 SRII(BLND_CONTROL, BLND, 5) 60 61 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ 62 SRII(PIXEL_RATE_CNTL, blk, inst), \ 63 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PIXEL_RATE_REG_LIST_201(blk) \ 74 SRII(PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PIXEL_RATE_CNTL, blk, 1) 76 77 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 80 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 81 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 82 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 83 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 84 85 #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \ 86 SRII(PIXEL_RATE_CNTL, blk, 0), \ 87 SRII(PIXEL_RATE_CNTL, blk, 1),\ 88 SRII(PIXEL_RATE_CNTL, blk, 2),\ 89 SRII(PIXEL_RATE_CNTL, blk, 3), \ 90 SRII(PIXEL_RATE_CNTL, blk, 4), \ 91 SRII(PIXEL_RATE_CNTL, blk, 5) 92 93 #define HWSEQ_PHYPLL_REG_LIST_3(blk) \ 94 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 95 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ 96 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ 97 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 98 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 99 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 100 101 #define HWSEQ_PHYPLL_REG_LIST_201(blk) \ 102 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 103 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1) 104 105 #define HWSEQ_DCE11_REG_LIST_BASE() \ 106 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 107 SR(DCFEV_CLOCK_CONTROL), \ 108 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 109 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 110 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 111 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 112 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 113 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 114 SRII(BLND_CONTROL, BLND, 0),\ 115 SRII(BLND_CONTROL, BLND, 1),\ 116 SR(BLNDV_CONTROL),\ 117 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 118 119 #if defined(CONFIG_DRM_AMD_DC_SI) 120 #define HWSEQ_DCE6_REG_LIST() \ 121 HWSEQ_DCEF_REG_LIST_DCE8(), \ 122 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 123 #endif 124 125 #define HWSEQ_DCE8_REG_LIST() \ 126 HWSEQ_DCEF_REG_LIST_DCE8(), \ 127 HWSEQ_BLND_REG_LIST(), \ 128 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 129 130 #define HWSEQ_DCE10_REG_LIST() \ 131 HWSEQ_DCEF_REG_LIST(), \ 132 HWSEQ_BLND_REG_LIST(), \ 133 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 134 135 #define HWSEQ_ST_REG_LIST() \ 136 HWSEQ_DCE11_REG_LIST_BASE(), \ 137 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 138 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 139 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 140 .BLND_CONTROL[2] = mmBLNDV_CONTROL 141 142 #define HWSEQ_CZ_REG_LIST() \ 143 HWSEQ_DCE11_REG_LIST_BASE(), \ 144 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 145 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 146 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 147 SRII(BLND_CONTROL, BLND, 2), \ 148 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 149 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 150 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 151 .BLND_CONTROL[3] = mmBLNDV_CONTROL 152 153 #define HWSEQ_DCE120_REG_LIST() \ 154 HWSEQ_DCE10_REG_LIST(), \ 155 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 156 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 157 SR(DCHUB_FB_LOCATION),\ 158 SR(DCHUB_AGP_BASE),\ 159 SR(DCHUB_AGP_BOT),\ 160 SR(DCHUB_AGP_TOP) 161 162 #define HWSEQ_VG20_REG_LIST() \ 163 HWSEQ_DCE120_REG_LIST(),\ 164 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 165 166 #define HWSEQ_DCE112_REG_LIST() \ 167 HWSEQ_DCE10_REG_LIST(), \ 168 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 169 HWSEQ_PHYPLL_REG_LIST(CRTC) 170 171 #define HWSEQ_DCN_REG_LIST()\ 172 SR(REFCLK_CNTL), \ 173 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 174 SR(DIO_MEM_PWR_CTRL), \ 175 SR(DCCG_GATE_DISABLE_CNTL), \ 176 SR(DCCG_GATE_DISABLE_CNTL2), \ 177 SR(DCFCLK_CNTL),\ 178 SR(DCFCLK_CNTL), \ 179 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 180 181 182 #define MMHUB_DCN_REG_LIST()\ 183 /* todo: get these from GVM instead of reading registers ourselves */\ 184 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 185 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 186 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 187 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 188 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 189 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 190 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 191 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 192 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 193 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 194 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 195 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 196 197 198 #define HWSEQ_DCN1_REG_LIST()\ 199 HWSEQ_DCN_REG_LIST(), \ 200 MMHUB_DCN_REG_LIST(), \ 201 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 202 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 203 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 204 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 205 SR(DCHUBBUB_SDPIF_FB_BASE),\ 206 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 207 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 208 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 209 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 210 SR(DOMAIN0_PG_CONFIG), \ 211 SR(DOMAIN1_PG_CONFIG), \ 212 SR(DOMAIN2_PG_CONFIG), \ 213 SR(DOMAIN3_PG_CONFIG), \ 214 SR(DOMAIN4_PG_CONFIG), \ 215 SR(DOMAIN5_PG_CONFIG), \ 216 SR(DOMAIN6_PG_CONFIG), \ 217 SR(DOMAIN7_PG_CONFIG), \ 218 SR(DOMAIN0_PG_STATUS), \ 219 SR(DOMAIN1_PG_STATUS), \ 220 SR(DOMAIN2_PG_STATUS), \ 221 SR(DOMAIN3_PG_STATUS), \ 222 SR(DOMAIN4_PG_STATUS), \ 223 SR(DOMAIN5_PG_STATUS), \ 224 SR(DOMAIN6_PG_STATUS), \ 225 SR(DOMAIN7_PG_STATUS), \ 226 SR(D1VGA_CONTROL), \ 227 SR(D2VGA_CONTROL), \ 228 SR(D3VGA_CONTROL), \ 229 SR(D4VGA_CONTROL), \ 230 SR(VGA_TEST_CONTROL), \ 231 SR(DC_IP_REQUEST_CNTL) 232 233 #define HWSEQ_DCN2_REG_LIST()\ 234 HWSEQ_DCN_REG_LIST(), \ 235 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 236 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 237 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 238 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 239 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 240 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ 241 SR(MICROSECOND_TIME_BASE_DIV), \ 242 SR(MILLISECOND_TIME_BASE_DIV), \ 243 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 244 SR(RBBMIF_TIMEOUT_DIS), \ 245 SR(RBBMIF_TIMEOUT_DIS_2), \ 246 SR(DCHUBBUB_CRC_CTRL), \ 247 SR(DPP_TOP0_DPP_CRC_CTRL), \ 248 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 249 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 250 SR(MPC_CRC_CTRL), \ 251 SR(MPC_CRC_RESULT_GB), \ 252 SR(MPC_CRC_RESULT_C), \ 253 SR(MPC_CRC_RESULT_AR), \ 254 SR(DOMAIN0_PG_CONFIG), \ 255 SR(DOMAIN1_PG_CONFIG), \ 256 SR(DOMAIN2_PG_CONFIG), \ 257 SR(DOMAIN3_PG_CONFIG), \ 258 SR(DOMAIN4_PG_CONFIG), \ 259 SR(DOMAIN5_PG_CONFIG), \ 260 SR(DOMAIN6_PG_CONFIG), \ 261 SR(DOMAIN7_PG_CONFIG), \ 262 SR(DOMAIN8_PG_CONFIG), \ 263 SR(DOMAIN9_PG_CONFIG), \ 264 /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ 265 /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ 266 SR(DOMAIN16_PG_CONFIG), \ 267 SR(DOMAIN17_PG_CONFIG), \ 268 SR(DOMAIN18_PG_CONFIG), \ 269 SR(DOMAIN19_PG_CONFIG), \ 270 SR(DOMAIN20_PG_CONFIG), \ 271 SR(DOMAIN21_PG_CONFIG), \ 272 SR(DOMAIN0_PG_STATUS), \ 273 SR(DOMAIN1_PG_STATUS), \ 274 SR(DOMAIN2_PG_STATUS), \ 275 SR(DOMAIN3_PG_STATUS), \ 276 SR(DOMAIN4_PG_STATUS), \ 277 SR(DOMAIN5_PG_STATUS), \ 278 SR(DOMAIN6_PG_STATUS), \ 279 SR(DOMAIN7_PG_STATUS), \ 280 SR(DOMAIN8_PG_STATUS), \ 281 SR(DOMAIN9_PG_STATUS), \ 282 SR(DOMAIN10_PG_STATUS), \ 283 SR(DOMAIN11_PG_STATUS), \ 284 SR(DOMAIN16_PG_STATUS), \ 285 SR(DOMAIN17_PG_STATUS), \ 286 SR(DOMAIN18_PG_STATUS), \ 287 SR(DOMAIN19_PG_STATUS), \ 288 SR(DOMAIN20_PG_STATUS), \ 289 SR(DOMAIN21_PG_STATUS), \ 290 SR(D1VGA_CONTROL), \ 291 SR(D2VGA_CONTROL), \ 292 SR(D3VGA_CONTROL), \ 293 SR(D4VGA_CONTROL), \ 294 SR(D5VGA_CONTROL), \ 295 SR(D6VGA_CONTROL), \ 296 SR(DC_IP_REQUEST_CNTL) 297 298 #define HWSEQ_DCN21_REG_LIST()\ 299 HWSEQ_DCN_REG_LIST(), \ 300 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 301 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 302 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 303 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 304 MMHUB_DCN_REG_LIST(), \ 305 SR(MICROSECOND_TIME_BASE_DIV), \ 306 SR(MILLISECOND_TIME_BASE_DIV), \ 307 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 308 SR(RBBMIF_TIMEOUT_DIS), \ 309 SR(RBBMIF_TIMEOUT_DIS_2), \ 310 SR(DCHUBBUB_CRC_CTRL), \ 311 SR(DPP_TOP0_DPP_CRC_CTRL), \ 312 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 313 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 314 SR(MPC_CRC_CTRL), \ 315 SR(MPC_CRC_RESULT_GB), \ 316 SR(MPC_CRC_RESULT_C), \ 317 SR(MPC_CRC_RESULT_AR), \ 318 SR(DOMAIN0_PG_CONFIG), \ 319 SR(DOMAIN1_PG_CONFIG), \ 320 SR(DOMAIN2_PG_CONFIG), \ 321 SR(DOMAIN3_PG_CONFIG), \ 322 SR(DOMAIN4_PG_CONFIG), \ 323 SR(DOMAIN5_PG_CONFIG), \ 324 SR(DOMAIN6_PG_CONFIG), \ 325 SR(DOMAIN7_PG_CONFIG), \ 326 SR(DOMAIN16_PG_CONFIG), \ 327 SR(DOMAIN17_PG_CONFIG), \ 328 SR(DOMAIN18_PG_CONFIG), \ 329 SR(DOMAIN0_PG_STATUS), \ 330 SR(DOMAIN1_PG_STATUS), \ 331 SR(DOMAIN2_PG_STATUS), \ 332 SR(DOMAIN3_PG_STATUS), \ 333 SR(DOMAIN4_PG_STATUS), \ 334 SR(DOMAIN5_PG_STATUS), \ 335 SR(DOMAIN6_PG_STATUS), \ 336 SR(DOMAIN7_PG_STATUS), \ 337 SR(DOMAIN16_PG_STATUS), \ 338 SR(DOMAIN17_PG_STATUS), \ 339 SR(DOMAIN18_PG_STATUS), \ 340 SR(D1VGA_CONTROL), \ 341 SR(D2VGA_CONTROL), \ 342 SR(D3VGA_CONTROL), \ 343 SR(D4VGA_CONTROL), \ 344 SR(D5VGA_CONTROL), \ 345 SR(D6VGA_CONTROL), \ 346 SR(DC_IP_REQUEST_CNTL) 347 348 #define HWSEQ_DCN201_REG_LIST()\ 349 HWSEQ_DCN_REG_LIST(), \ 350 HWSEQ_PIXEL_RATE_REG_LIST_201(OTG), \ 351 HWSEQ_PHYPLL_REG_LIST_201(OTG), \ 352 SR(MICROSECOND_TIME_BASE_DIV), \ 353 SR(MILLISECOND_TIME_BASE_DIV), \ 354 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 355 SR(RBBMIF_TIMEOUT_DIS), \ 356 SR(RBBMIF_TIMEOUT_DIS_2), \ 357 SR(DCHUBBUB_CRC_CTRL), \ 358 SR(DPP_TOP0_DPP_CRC_CTRL), \ 359 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 360 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 361 SR(MPC_CRC_CTRL), \ 362 SR(MPC_CRC_RESULT_GB), \ 363 SR(MPC_CRC_RESULT_C), \ 364 SR(MPC_CRC_RESULT_AR), \ 365 SR(AZALIA_AUDIO_DTO), \ 366 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 367 MMHUB_SR(MC_VM_FB_LOCATION_BASE), \ 368 MMHUB_SR(MC_VM_FB_LOCATION_TOP), \ 369 MMHUB_SR(MC_VM_FB_OFFSET) 370 371 #define HWSEQ_DCN30_REG_LIST()\ 372 HWSEQ_DCN2_REG_LIST(),\ 373 HWSEQ_DCN_REG_LIST(), \ 374 HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \ 375 HWSEQ_PHYPLL_REG_LIST_3(OTG), \ 376 SR(MICROSECOND_TIME_BASE_DIV), \ 377 SR(MILLISECOND_TIME_BASE_DIV), \ 378 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 379 SR(RBBMIF_TIMEOUT_DIS), \ 380 SR(RBBMIF_TIMEOUT_DIS_2), \ 381 SR(DCHUBBUB_CRC_CTRL), \ 382 SR(DPP_TOP0_DPP_CRC_CTRL), \ 383 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 384 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 385 SR(MPC_CRC_CTRL), \ 386 SR(MPC_CRC_RESULT_GB), \ 387 SR(MPC_CRC_RESULT_C), \ 388 SR(MPC_CRC_RESULT_AR), \ 389 SR(AZALIA_AUDIO_DTO), \ 390 SR(AZALIA_CONTROLLER_CLOCK_GATING) 391 392 #define HWSEQ_DCN301_REG_LIST()\ 393 SR(REFCLK_CNTL), \ 394 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 395 SR(DIO_MEM_PWR_CTRL), \ 396 SR(DCCG_GATE_DISABLE_CNTL), \ 397 SR(DCCG_GATE_DISABLE_CNTL2), \ 398 SR(DCFCLK_CNTL),\ 399 SR(DCFCLK_CNTL), \ 400 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 401 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 402 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 403 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 404 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 405 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 406 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 407 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 408 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 409 SR(MICROSECOND_TIME_BASE_DIV), \ 410 SR(MILLISECOND_TIME_BASE_DIV), \ 411 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 412 SR(RBBMIF_TIMEOUT_DIS), \ 413 SR(RBBMIF_TIMEOUT_DIS_2), \ 414 SR(DCHUBBUB_CRC_CTRL), \ 415 SR(DPP_TOP0_DPP_CRC_CTRL), \ 416 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 417 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 418 SR(MPC_CRC_CTRL), \ 419 SR(MPC_CRC_RESULT_GB), \ 420 SR(MPC_CRC_RESULT_C), \ 421 SR(MPC_CRC_RESULT_AR), \ 422 SR(DOMAIN0_PG_CONFIG), \ 423 SR(DOMAIN1_PG_CONFIG), \ 424 SR(DOMAIN2_PG_CONFIG), \ 425 SR(DOMAIN3_PG_CONFIG), \ 426 SR(DOMAIN4_PG_CONFIG), \ 427 SR(DOMAIN5_PG_CONFIG), \ 428 SR(DOMAIN6_PG_CONFIG), \ 429 SR(DOMAIN7_PG_CONFIG), \ 430 SR(DOMAIN16_PG_CONFIG), \ 431 SR(DOMAIN17_PG_CONFIG), \ 432 SR(DOMAIN18_PG_CONFIG), \ 433 SR(DOMAIN0_PG_STATUS), \ 434 SR(DOMAIN1_PG_STATUS), \ 435 SR(DOMAIN2_PG_STATUS), \ 436 SR(DOMAIN3_PG_STATUS), \ 437 SR(DOMAIN4_PG_STATUS), \ 438 SR(DOMAIN5_PG_STATUS), \ 439 SR(DOMAIN6_PG_STATUS), \ 440 SR(DOMAIN7_PG_STATUS), \ 441 SR(DOMAIN16_PG_STATUS), \ 442 SR(DOMAIN17_PG_STATUS), \ 443 SR(DOMAIN18_PG_STATUS), \ 444 SR(D1VGA_CONTROL), \ 445 SR(D2VGA_CONTROL), \ 446 SR(D3VGA_CONTROL), \ 447 SR(D4VGA_CONTROL), \ 448 SR(D5VGA_CONTROL), \ 449 SR(D6VGA_CONTROL), \ 450 SR(DC_IP_REQUEST_CNTL), \ 451 SR(AZALIA_AUDIO_DTO), \ 452 SR(AZALIA_CONTROLLER_CLOCK_GATING) 453 454 #define HWSEQ_DCN302_REG_LIST()\ 455 HWSEQ_DCN_REG_LIST(), \ 456 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 457 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 458 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 459 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 460 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 461 SR(MICROSECOND_TIME_BASE_DIV), \ 462 SR(MILLISECOND_TIME_BASE_DIV), \ 463 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 464 SR(RBBMIF_TIMEOUT_DIS), \ 465 SR(RBBMIF_TIMEOUT_DIS_2), \ 466 SR(DCHUBBUB_CRC_CTRL), \ 467 SR(DPP_TOP0_DPP_CRC_CTRL), \ 468 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 469 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 470 SR(MPC_CRC_CTRL), \ 471 SR(MPC_CRC_RESULT_GB), \ 472 SR(MPC_CRC_RESULT_C), \ 473 SR(MPC_CRC_RESULT_AR), \ 474 SR(DOMAIN0_PG_CONFIG), \ 475 SR(DOMAIN1_PG_CONFIG), \ 476 SR(DOMAIN2_PG_CONFIG), \ 477 SR(DOMAIN3_PG_CONFIG), \ 478 SR(DOMAIN4_PG_CONFIG), \ 479 SR(DOMAIN5_PG_CONFIG), \ 480 SR(DOMAIN6_PG_CONFIG), \ 481 SR(DOMAIN7_PG_CONFIG), \ 482 SR(DOMAIN8_PG_CONFIG), \ 483 SR(DOMAIN9_PG_CONFIG), \ 484 SR(DOMAIN16_PG_CONFIG), \ 485 SR(DOMAIN17_PG_CONFIG), \ 486 SR(DOMAIN18_PG_CONFIG), \ 487 SR(DOMAIN19_PG_CONFIG), \ 488 SR(DOMAIN20_PG_CONFIG), \ 489 SR(DOMAIN0_PG_STATUS), \ 490 SR(DOMAIN1_PG_STATUS), \ 491 SR(DOMAIN2_PG_STATUS), \ 492 SR(DOMAIN3_PG_STATUS), \ 493 SR(DOMAIN4_PG_STATUS), \ 494 SR(DOMAIN5_PG_STATUS), \ 495 SR(DOMAIN6_PG_STATUS), \ 496 SR(DOMAIN7_PG_STATUS), \ 497 SR(DOMAIN8_PG_STATUS), \ 498 SR(DOMAIN9_PG_STATUS), \ 499 SR(DOMAIN16_PG_STATUS), \ 500 SR(DOMAIN17_PG_STATUS), \ 501 SR(DOMAIN18_PG_STATUS), \ 502 SR(DOMAIN19_PG_STATUS), \ 503 SR(DOMAIN20_PG_STATUS), \ 504 SR(D1VGA_CONTROL), \ 505 SR(D2VGA_CONTROL), \ 506 SR(D3VGA_CONTROL), \ 507 SR(D4VGA_CONTROL), \ 508 SR(D5VGA_CONTROL), \ 509 SR(D6VGA_CONTROL), \ 510 SR(DC_IP_REQUEST_CNTL), \ 511 SR(AZALIA_AUDIO_DTO), \ 512 SR(AZALIA_CONTROLLER_CLOCK_GATING) 513 514 #define HWSEQ_DCN303_REG_LIST() \ 515 HWSEQ_DCN_REG_LIST(), \ 516 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 517 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 518 SR(MICROSECOND_TIME_BASE_DIV), \ 519 SR(MILLISECOND_TIME_BASE_DIV), \ 520 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 521 SR(RBBMIF_TIMEOUT_DIS), \ 522 SR(RBBMIF_TIMEOUT_DIS_2), \ 523 SR(DCHUBBUB_CRC_CTRL), \ 524 SR(DPP_TOP0_DPP_CRC_CTRL), \ 525 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 526 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 527 SR(MPC_CRC_CTRL), \ 528 SR(MPC_CRC_RESULT_GB), \ 529 SR(MPC_CRC_RESULT_C), \ 530 SR(MPC_CRC_RESULT_AR), \ 531 SR(D1VGA_CONTROL), \ 532 SR(D2VGA_CONTROL), \ 533 SR(D3VGA_CONTROL), \ 534 SR(D4VGA_CONTROL), \ 535 SR(D5VGA_CONTROL), \ 536 SR(D6VGA_CONTROL), \ 537 HWSEQ_PIXEL_RATE_REG_LIST_303(OTG), \ 538 HWSEQ_PHYPLL_REG_LIST_303(OTG), \ 539 SR(AZALIA_AUDIO_DTO), \ 540 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 541 SR(HPO_TOP_CLOCK_CONTROL) 542 543 #define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \ 544 SRII(PIXEL_RATE_CNTL, blk, 0), \ 545 SRII(PIXEL_RATE_CNTL, blk, 1),\ 546 SRII(PIXEL_RATE_CNTL, blk, 2),\ 547 SRII(PIXEL_RATE_CNTL, blk, 3), \ 548 SRII(PIXEL_RATE_CNTL, blk, 4) 549 550 #define HWSEQ_PHYPLL_REG_LIST_302(blk) \ 551 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 552 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ 553 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ 554 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 555 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4) 556 557 #define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \ 558 SRII(PIXEL_RATE_CNTL, blk, 0), \ 559 SRII(PIXEL_RATE_CNTL, blk, 1) 560 561 #define HWSEQ_PHYPLL_REG_LIST_303(blk) \ 562 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 563 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1) 564 565 struct dce_hwseq_registers { 566 uint32_t DCFE_CLOCK_CONTROL[6]; 567 uint32_t DCFEV_CLOCK_CONTROL; 568 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 569 uint32_t BLND_V_UPDATE_LOCK[6]; 570 uint32_t BLND_CONTROL[6]; 571 uint32_t BLNDV_CONTROL; 572 uint32_t CRTC_H_BLANK_START_END[6]; 573 uint32_t PIXEL_RATE_CNTL[6]; 574 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 575 /*DCHUB*/ 576 uint32_t DCHUB_FB_LOCATION; 577 uint32_t DCHUB_AGP_BASE; 578 uint32_t DCHUB_AGP_BOT; 579 uint32_t DCHUB_AGP_TOP; 580 581 uint32_t REFCLK_CNTL; 582 583 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 584 uint32_t DCHUBBUB_SDPIF_FB_BASE; 585 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 586 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 587 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 588 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 589 uint32_t DC_IP_REQUEST_CNTL; 590 uint32_t DOMAIN0_PG_CONFIG; 591 uint32_t DOMAIN1_PG_CONFIG; 592 uint32_t DOMAIN2_PG_CONFIG; 593 uint32_t DOMAIN3_PG_CONFIG; 594 uint32_t DOMAIN4_PG_CONFIG; 595 uint32_t DOMAIN5_PG_CONFIG; 596 uint32_t DOMAIN6_PG_CONFIG; 597 uint32_t DOMAIN7_PG_CONFIG; 598 uint32_t DOMAIN8_PG_CONFIG; 599 uint32_t DOMAIN9_PG_CONFIG; 600 uint32_t DOMAIN10_PG_CONFIG; 601 uint32_t DOMAIN11_PG_CONFIG; 602 uint32_t DOMAIN16_PG_CONFIG; 603 uint32_t DOMAIN17_PG_CONFIG; 604 uint32_t DOMAIN18_PG_CONFIG; 605 uint32_t DOMAIN19_PG_CONFIG; 606 uint32_t DOMAIN20_PG_CONFIG; 607 uint32_t DOMAIN21_PG_CONFIG; 608 uint32_t DOMAIN0_PG_STATUS; 609 uint32_t DOMAIN1_PG_STATUS; 610 uint32_t DOMAIN2_PG_STATUS; 611 uint32_t DOMAIN3_PG_STATUS; 612 uint32_t DOMAIN4_PG_STATUS; 613 uint32_t DOMAIN5_PG_STATUS; 614 uint32_t DOMAIN6_PG_STATUS; 615 uint32_t DOMAIN7_PG_STATUS; 616 uint32_t DOMAIN8_PG_STATUS; 617 uint32_t DOMAIN9_PG_STATUS; 618 uint32_t DOMAIN10_PG_STATUS; 619 uint32_t DOMAIN11_PG_STATUS; 620 uint32_t DOMAIN16_PG_STATUS; 621 uint32_t DOMAIN17_PG_STATUS; 622 uint32_t DOMAIN18_PG_STATUS; 623 uint32_t DOMAIN19_PG_STATUS; 624 uint32_t DOMAIN20_PG_STATUS; 625 uint32_t DOMAIN21_PG_STATUS; 626 uint32_t DIO_MEM_PWR_CTRL; 627 uint32_t DCCG_GATE_DISABLE_CNTL; 628 uint32_t DCCG_GATE_DISABLE_CNTL2; 629 uint32_t DCFCLK_CNTL; 630 uint32_t MICROSECOND_TIME_BASE_DIV; 631 uint32_t MILLISECOND_TIME_BASE_DIV; 632 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 633 uint32_t RBBMIF_TIMEOUT_DIS; 634 uint32_t RBBMIF_TIMEOUT_DIS_2; 635 uint32_t DCHUBBUB_CRC_CTRL; 636 uint32_t DPP_TOP0_DPP_CRC_CTRL; 637 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 638 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 639 uint32_t MPC_CRC_CTRL; 640 uint32_t MPC_CRC_RESULT_GB; 641 uint32_t MPC_CRC_RESULT_C; 642 uint32_t MPC_CRC_RESULT_AR; 643 uint32_t D1VGA_CONTROL; 644 uint32_t D2VGA_CONTROL; 645 uint32_t D3VGA_CONTROL; 646 uint32_t D4VGA_CONTROL; 647 uint32_t D5VGA_CONTROL; 648 uint32_t D6VGA_CONTROL; 649 uint32_t VGA_TEST_CONTROL; 650 /* MMHUB registers. read only. temporary hack */ 651 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 652 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 653 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 654 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 655 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 656 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 657 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 658 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 659 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 660 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 661 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 662 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 663 uint32_t MC_VM_XGMI_LFB_CNTL; 664 uint32_t AZALIA_AUDIO_DTO; 665 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 666 uint32_t HPO_TOP_CLOCK_CONTROL; 667 uint32_t ODM_MEM_PWR_CTRL3; 668 uint32_t DMU_MEM_PWR_CNTL; 669 uint32_t MMHUBBUB_MEM_PWR_CNTL; 670 uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; 671 uint32_t MC_VM_FB_LOCATION_BASE; 672 uint32_t MC_VM_FB_LOCATION_TOP; 673 uint32_t MC_VM_FB_OFFSET; 674 uint32_t HPO_TOP_HW_CONTROL; 675 }; 676 /* set field name */ 677 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 678 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 679 680 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 681 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 682 683 684 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 685 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 686 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 687 688 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 689 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 690 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 691 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 692 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 693 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 694 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 695 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 696 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 697 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 698 699 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 700 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 701 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 702 703 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 704 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 705 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 706 707 #if defined(CONFIG_DRM_AMD_DC_SI) 708 #define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\ 709 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 710 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 711 #endif 712 713 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 714 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 715 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 716 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 717 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 718 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 719 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 720 721 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 722 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 723 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 724 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 725 726 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 727 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 728 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 729 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 730 731 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 732 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 733 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 734 735 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 736 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 737 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 738 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 739 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 740 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 741 742 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 743 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 744 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 745 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 746 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 747 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) 748 749 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 750 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 751 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 752 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 753 754 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 755 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 756 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 757 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 758 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 759 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 760 761 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 762 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 763 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 764 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 765 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 766 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 767 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 768 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 769 /* todo: get these from GVM instead of reading registers ourselves */\ 770 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 771 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 772 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 773 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 774 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 775 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 776 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 777 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 778 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 779 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 780 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 781 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 782 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 783 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 784 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 785 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 786 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 787 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 788 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 789 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 790 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 791 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 792 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 793 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 794 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 795 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 796 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 797 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 798 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 799 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 800 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 801 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 802 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 803 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 804 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 805 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 806 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 807 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 808 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 809 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 810 811 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 812 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 813 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 814 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 815 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 816 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 817 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 818 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 819 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 820 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 821 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 822 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 823 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 824 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 825 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 826 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 827 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 828 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 829 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 830 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 831 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 832 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 833 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 834 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 835 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 836 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 837 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 838 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 839 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 840 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 841 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 842 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 843 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 844 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 845 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 846 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 847 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 848 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 849 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 850 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 851 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 852 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 853 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 854 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 855 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 856 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 857 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 858 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 859 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 860 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 861 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 862 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 863 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 864 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 865 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 866 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 867 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 868 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 869 870 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ 871 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 872 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 873 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 874 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 875 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 876 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 877 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 878 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 879 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 880 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 881 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 882 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 883 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 884 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 885 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 886 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 887 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 888 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 889 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 890 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 891 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 892 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 893 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 894 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 895 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 896 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 897 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 898 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 899 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 900 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 901 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 902 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 903 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 904 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 905 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 906 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 907 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 908 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 909 910 #define HWSEQ_DCN201_MASK_SH_LIST(mask_sh)\ 911 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 912 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 913 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 914 915 #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\ 916 HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \ 917 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 918 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 919 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 920 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 921 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 922 923 #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\ 924 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 925 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 926 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 927 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 928 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 929 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 930 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 931 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 932 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 933 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 934 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 935 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 936 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 937 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 938 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 939 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 940 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 941 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 942 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 943 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 944 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 945 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 946 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 947 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 948 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 949 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 950 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 951 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 952 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 953 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 954 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 955 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 956 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 957 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 958 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 959 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 960 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\ 961 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\ 962 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\ 963 HWS_SF(, PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh),\ 964 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 965 966 #define HWSEQ_DCN302_MASK_SH_LIST(mask_sh)\ 967 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 968 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 969 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 970 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 971 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 972 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 973 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 974 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 975 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 976 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 977 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 978 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 979 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 980 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 981 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 982 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 983 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 984 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 985 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 986 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 987 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 988 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 989 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 990 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 991 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 992 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 993 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 994 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 995 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 996 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 997 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 998 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 999 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 1000 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 1001 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 1002 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 1003 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 1004 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 1005 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 1006 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 1007 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 1008 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 1009 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 1010 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 1011 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 1012 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 1013 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 1014 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 1015 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 1016 1017 #define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) \ 1018 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 1019 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 1020 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 1021 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh) 1022 1023 #define HWSEQ_REG_FIELD_LIST(type) \ 1024 type DCFE_CLOCK_ENABLE; \ 1025 type DCFEV_CLOCK_ENABLE; \ 1026 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 1027 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 1028 type BLND_SCL_V_UPDATE_LOCK; \ 1029 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 1030 type BLND_BLND_V_UPDATE_LOCK; \ 1031 type BLND_V_UPDATE_LOCK_MODE; \ 1032 type BLND_FEEDTHROUGH_EN; \ 1033 type BLND_ALPHA_MODE; \ 1034 type BLND_MODE; \ 1035 type BLND_MULTIPLIED_MODE; \ 1036 type DP_DTO0_ENABLE; \ 1037 type PIXEL_RATE_SOURCE; \ 1038 type PHYPLL_PIXEL_RATE_SOURCE; \ 1039 type PIXEL_RATE_PLL_SOURCE; \ 1040 /* todo: get these from GVM instead of reading registers ourselves */\ 1041 type PAGE_DIRECTORY_ENTRY_HI32;\ 1042 type PAGE_DIRECTORY_ENTRY_LO32;\ 1043 type LOGICAL_PAGE_NUMBER_HI4;\ 1044 type LOGICAL_PAGE_NUMBER_LO32;\ 1045 type PHYSICAL_PAGE_ADDR_HI4;\ 1046 type PHYSICAL_PAGE_ADDR_LO32;\ 1047 type PHYSICAL_PAGE_NUMBER_MSB;\ 1048 type PHYSICAL_PAGE_NUMBER_LSB;\ 1049 type LOGICAL_ADDR; \ 1050 type PF_LFB_REGION;\ 1051 type PF_MAX_REGION;\ 1052 type ENABLE_L1_TLB;\ 1053 type SYSTEM_ACCESS_MODE; 1054 1055 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 1056 type HUBP_VTG_SEL; \ 1057 type HUBP_CLOCK_ENABLE; \ 1058 type DPP_CLOCK_ENABLE; \ 1059 type SDPIF_FB_BASE;\ 1060 type SDPIF_FB_OFFSET;\ 1061 type SDPIF_AGP_BASE;\ 1062 type SDPIF_AGP_BOT;\ 1063 type SDPIF_AGP_TOP;\ 1064 type FB_TOP;\ 1065 type FB_BASE;\ 1066 type FB_OFFSET;\ 1067 type AGP_BASE;\ 1068 type AGP_BOT;\ 1069 type AGP_TOP;\ 1070 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 1071 type OPP_PIPE_CLOCK_EN;\ 1072 type IP_REQUEST_EN; \ 1073 type DOMAIN0_POWER_FORCEON; \ 1074 type DOMAIN0_POWER_GATE; \ 1075 type DOMAIN1_POWER_FORCEON; \ 1076 type DOMAIN1_POWER_GATE; \ 1077 type DOMAIN2_POWER_FORCEON; \ 1078 type DOMAIN2_POWER_GATE; \ 1079 type DOMAIN3_POWER_FORCEON; \ 1080 type DOMAIN3_POWER_GATE; \ 1081 type DOMAIN4_POWER_FORCEON; \ 1082 type DOMAIN4_POWER_GATE; \ 1083 type DOMAIN5_POWER_FORCEON; \ 1084 type DOMAIN5_POWER_GATE; \ 1085 type DOMAIN6_POWER_FORCEON; \ 1086 type DOMAIN6_POWER_GATE; \ 1087 type DOMAIN7_POWER_FORCEON; \ 1088 type DOMAIN7_POWER_GATE; \ 1089 type DOMAIN8_POWER_FORCEON; \ 1090 type DOMAIN8_POWER_GATE; \ 1091 type DOMAIN9_POWER_FORCEON; \ 1092 type DOMAIN9_POWER_GATE; \ 1093 type DOMAIN10_POWER_FORCEON; \ 1094 type DOMAIN10_POWER_GATE; \ 1095 type DOMAIN11_POWER_FORCEON; \ 1096 type DOMAIN11_POWER_GATE; \ 1097 type DOMAIN16_POWER_FORCEON; \ 1098 type DOMAIN16_POWER_GATE; \ 1099 type DOMAIN17_POWER_FORCEON; \ 1100 type DOMAIN17_POWER_GATE; \ 1101 type DOMAIN18_POWER_FORCEON; \ 1102 type DOMAIN18_POWER_GATE; \ 1103 type DOMAIN19_POWER_FORCEON; \ 1104 type DOMAIN19_POWER_GATE; \ 1105 type DOMAIN20_POWER_FORCEON; \ 1106 type DOMAIN20_POWER_GATE; \ 1107 type DOMAIN21_POWER_FORCEON; \ 1108 type DOMAIN21_POWER_GATE; \ 1109 type DOMAIN0_PGFSM_PWR_STATUS; \ 1110 type DOMAIN1_PGFSM_PWR_STATUS; \ 1111 type DOMAIN2_PGFSM_PWR_STATUS; \ 1112 type DOMAIN3_PGFSM_PWR_STATUS; \ 1113 type DOMAIN4_PGFSM_PWR_STATUS; \ 1114 type DOMAIN5_PGFSM_PWR_STATUS; \ 1115 type DOMAIN6_PGFSM_PWR_STATUS; \ 1116 type DOMAIN7_PGFSM_PWR_STATUS; \ 1117 type DOMAIN8_PGFSM_PWR_STATUS; \ 1118 type DOMAIN9_PGFSM_PWR_STATUS; \ 1119 type DOMAIN10_PGFSM_PWR_STATUS; \ 1120 type DOMAIN11_PGFSM_PWR_STATUS; \ 1121 type DOMAIN16_PGFSM_PWR_STATUS; \ 1122 type DOMAIN17_PGFSM_PWR_STATUS; \ 1123 type DOMAIN18_PGFSM_PWR_STATUS; \ 1124 type DOMAIN19_PGFSM_PWR_STATUS; \ 1125 type DOMAIN20_PGFSM_PWR_STATUS; \ 1126 type DOMAIN21_PGFSM_PWR_STATUS; \ 1127 type DCFCLK_GATE_DIS; \ 1128 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 1129 type VGA_TEST_ENABLE; \ 1130 type VGA_TEST_RENDER_START; \ 1131 type D1VGA_MODE_ENABLE; \ 1132 type D2VGA_MODE_ENABLE; \ 1133 type D3VGA_MODE_ENABLE; \ 1134 type D4VGA_MODE_ENABLE; \ 1135 type AZALIA_AUDIO_DTO_MODULE; \ 1136 type ODM_MEM_UNASSIGNED_PWR_MODE; \ 1137 type ODM_MEM_VBLANK_PWR_MODE; \ 1138 type DMCU_ERAM_MEM_PWR_FORCE; \ 1139 type VGA_MEM_PWR_FORCE; 1140 1141 #define HWSEQ_DCN3_REG_FIELD_LIST(type) \ 1142 type HPO_HDMISTREAMCLK_GATE_DIS; 1143 1144 #define HWSEQ_DCN301_REG_FIELD_LIST(type) \ 1145 type PANEL_BLON;\ 1146 type PANEL_DIGON;\ 1147 type PANEL_DIGON_OVRD;\ 1148 type PANEL_PWRSEQ_TARGET_STATE_R; 1149 1150 #define HWSEQ_DCN31_REG_FIELD_LIST(type) \ 1151 type DOMAIN_POWER_FORCEON;\ 1152 type DOMAIN_POWER_GATE;\ 1153 type DOMAIN_PGFSM_PWR_STATUS;\ 1154 type HPO_HDMISTREAMCLK_G_GATE_DIS;\ 1155 type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;\ 1156 type I2C_LIGHT_SLEEP_FORCE;\ 1157 type HPO_IO_EN; 1158 1159 struct dce_hwseq_shift { 1160 HWSEQ_REG_FIELD_LIST(uint8_t) 1161 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 1162 HWSEQ_DCN3_REG_FIELD_LIST(uint8_t) 1163 HWSEQ_DCN301_REG_FIELD_LIST(uint8_t) 1164 HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) 1165 }; 1166 1167 struct dce_hwseq_mask { 1168 HWSEQ_REG_FIELD_LIST(uint32_t) 1169 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 1170 HWSEQ_DCN3_REG_FIELD_LIST(uint32_t) 1171 HWSEQ_DCN301_REG_FIELD_LIST(uint32_t) 1172 HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) 1173 }; 1174 1175 1176 enum blnd_mode { 1177 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 1178 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 1179 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 1180 }; 1181 1182 struct dce_hwseq; 1183 struct pipe_ctx; 1184 struct clock_source; 1185 1186 void dce_enable_fe_clock(struct dce_hwseq *hwss, 1187 unsigned int inst, bool enable); 1188 1189 void dce_pipe_control_lock(struct dc *dc, 1190 struct pipe_ctx *pipe, 1191 bool lock); 1192 1193 void dce_set_blender_mode(struct dce_hwseq *hws, 1194 unsigned int blnd_inst, enum blnd_mode mode); 1195 1196 #if defined(CONFIG_DRM_AMD_DC_SI) 1197 void dce60_pipe_control_lock(struct dc *dc, 1198 struct pipe_ctx *pipe, 1199 bool lock); 1200 #endif 1201 1202 void dce_clock_gating_power_up(struct dce_hwseq *hws, 1203 bool enable); 1204 1205 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 1206 struct clock_source *clk_src, 1207 unsigned int tg_inst); 1208 1209 bool dce_use_lut(enum surface_pixel_format format); 1210 #endif /*__DCE_HWSEQ_H__*/ 1211