1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "hw_sequencer.h" 29 30 #define BL_REG_LIST()\ 31 SR(LVTMA_PWRSEQ_CNTL), \ 32 SR(LVTMA_PWRSEQ_STATE) 33 34 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 35 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 37 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 38 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 39 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 40 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 41 42 #define HWSEQ_DCEF_REG_LIST() \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 45 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 46 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 47 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 48 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 50 51 #define HWSEQ_BLND_REG_LIST() \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 54 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 55 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 56 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 57 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 58 SRII(BLND_CONTROL, BLND, 0), \ 59 SRII(BLND_CONTROL, BLND, 1), \ 60 SRII(BLND_CONTROL, BLND, 2), \ 61 SRII(BLND_CONTROL, BLND, 3), \ 62 SRII(BLND_CONTROL, BLND, 4), \ 63 SRII(BLND_CONTROL, BLND, 5) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #define HWSEQ_DCE11_REG_LIST_BASE() \ 82 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 83 SR(DCFEV_CLOCK_CONTROL), \ 84 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 85 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 86 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 87 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 88 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 89 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 90 SRII(BLND_CONTROL, BLND, 0),\ 91 SRII(BLND_CONTROL, BLND, 1),\ 92 SR(BLNDV_CONTROL),\ 93 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 94 BL_REG_LIST() 95 96 #define HWSEQ_DCE8_REG_LIST() \ 97 HWSEQ_DCEF_REG_LIST_DCE8(), \ 98 HWSEQ_BLND_REG_LIST(), \ 99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 100 BL_REG_LIST() 101 102 #define HWSEQ_DCE10_REG_LIST() \ 103 HWSEQ_DCEF_REG_LIST(), \ 104 HWSEQ_BLND_REG_LIST(), \ 105 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 106 BL_REG_LIST() 107 108 #define HWSEQ_ST_REG_LIST() \ 109 HWSEQ_DCE11_REG_LIST_BASE(), \ 110 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 111 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 112 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 113 .BLND_CONTROL[2] = mmBLNDV_CONTROL 114 115 #define HWSEQ_CZ_REG_LIST() \ 116 HWSEQ_DCE11_REG_LIST_BASE(), \ 117 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 118 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 119 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 120 SRII(BLND_CONTROL, BLND, 2), \ 121 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 122 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 123 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 124 .BLND_CONTROL[3] = mmBLNDV_CONTROL 125 126 #define HWSEQ_DCE120_REG_LIST() \ 127 HWSEQ_DCE10_REG_LIST(), \ 128 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 129 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 130 SR(DCHUB_FB_LOCATION),\ 131 SR(DCHUB_AGP_BASE),\ 132 SR(DCHUB_AGP_BOT),\ 133 SR(DCHUB_AGP_TOP), \ 134 BL_REG_LIST() 135 136 #define HWSEQ_DCE112_REG_LIST() \ 137 HWSEQ_DCE10_REG_LIST(), \ 138 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 139 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 140 BL_REG_LIST() 141 142 #define HWSEQ_DCN_REG_LIST()\ 143 SR(REFCLK_CNTL), \ 144 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 145 SR(DIO_MEM_PWR_CTRL), \ 146 SR(DCCG_GATE_DISABLE_CNTL), \ 147 SR(DCCG_GATE_DISABLE_CNTL2), \ 148 SR(DCFCLK_CNTL),\ 149 SR(DCFCLK_CNTL), \ 150 /* todo: get these from GVM instead of reading registers ourselves */\ 151 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 152 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 153 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 154 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 155 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 156 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 157 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 158 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 159 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 160 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 161 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 162 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 163 164 #define HWSEQ_DCN1_REG_LIST()\ 165 HWSEQ_DCN_REG_LIST(), \ 166 HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ 167 HWSEQ_PHYPLL_REG_LIST(OTG), \ 168 SR(DCHUBBUB_SDPIF_FB_BASE),\ 169 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 170 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 171 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 172 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 173 SR(DOMAIN0_PG_CONFIG), \ 174 SR(DOMAIN1_PG_CONFIG), \ 175 SR(DOMAIN2_PG_CONFIG), \ 176 SR(DOMAIN3_PG_CONFIG), \ 177 SR(DOMAIN4_PG_CONFIG), \ 178 SR(DOMAIN5_PG_CONFIG), \ 179 SR(DOMAIN6_PG_CONFIG), \ 180 SR(DOMAIN7_PG_CONFIG), \ 181 SR(DOMAIN0_PG_STATUS), \ 182 SR(DOMAIN1_PG_STATUS), \ 183 SR(DOMAIN2_PG_STATUS), \ 184 SR(DOMAIN3_PG_STATUS), \ 185 SR(DOMAIN4_PG_STATUS), \ 186 SR(DOMAIN5_PG_STATUS), \ 187 SR(DOMAIN6_PG_STATUS), \ 188 SR(DOMAIN7_PG_STATUS), \ 189 SR(D1VGA_CONTROL), \ 190 SR(D2VGA_CONTROL), \ 191 SR(D3VGA_CONTROL), \ 192 SR(D4VGA_CONTROL), \ 193 SR(VGA_TEST_CONTROL), \ 194 SR(DC_IP_REQUEST_CNTL), \ 195 BL_REG_LIST() 196 197 struct dce_hwseq_registers { 198 199 /* Backlight registers */ 200 uint32_t LVTMA_PWRSEQ_CNTL; 201 uint32_t LVTMA_PWRSEQ_STATE; 202 203 uint32_t DCFE_CLOCK_CONTROL[6]; 204 uint32_t DCFEV_CLOCK_CONTROL; 205 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 206 uint32_t BLND_V_UPDATE_LOCK[6]; 207 uint32_t BLND_CONTROL[6]; 208 uint32_t BLNDV_CONTROL; 209 uint32_t CRTC_H_BLANK_START_END[6]; 210 uint32_t PIXEL_RATE_CNTL[6]; 211 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 212 /*DCHUB*/ 213 uint32_t DCHUB_FB_LOCATION; 214 uint32_t DCHUB_AGP_BASE; 215 uint32_t DCHUB_AGP_BOT; 216 uint32_t DCHUB_AGP_TOP; 217 218 uint32_t REFCLK_CNTL; 219 220 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 221 uint32_t DCHUBBUB_SDPIF_FB_BASE; 222 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 223 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 224 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 225 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 226 uint32_t DC_IP_REQUEST_CNTL; 227 uint32_t DOMAIN0_PG_CONFIG; 228 uint32_t DOMAIN1_PG_CONFIG; 229 uint32_t DOMAIN2_PG_CONFIG; 230 uint32_t DOMAIN3_PG_CONFIG; 231 uint32_t DOMAIN4_PG_CONFIG; 232 uint32_t DOMAIN5_PG_CONFIG; 233 uint32_t DOMAIN6_PG_CONFIG; 234 uint32_t DOMAIN7_PG_CONFIG; 235 uint32_t DOMAIN0_PG_STATUS; 236 uint32_t DOMAIN1_PG_STATUS; 237 uint32_t DOMAIN2_PG_STATUS; 238 uint32_t DOMAIN3_PG_STATUS; 239 uint32_t DOMAIN4_PG_STATUS; 240 uint32_t DOMAIN5_PG_STATUS; 241 uint32_t DOMAIN6_PG_STATUS; 242 uint32_t DOMAIN7_PG_STATUS; 243 uint32_t DIO_MEM_PWR_CTRL; 244 uint32_t DCCG_GATE_DISABLE_CNTL; 245 uint32_t DCCG_GATE_DISABLE_CNTL2; 246 uint32_t DCFCLK_CNTL; 247 uint32_t MICROSECOND_TIME_BASE_DIV; 248 uint32_t MILLISECOND_TIME_BASE_DIV; 249 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 250 uint32_t RBBMIF_TIMEOUT_DIS; 251 uint32_t RBBMIF_TIMEOUT_DIS_2; 252 uint32_t DCHUBBUB_CRC_CTRL; 253 uint32_t DPP_TOP0_DPP_CRC_CTRL; 254 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 255 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 256 uint32_t MPC_CRC_CTRL; 257 uint32_t MPC_CRC_RESULT_GB; 258 uint32_t MPC_CRC_RESULT_C; 259 uint32_t MPC_CRC_RESULT_AR; 260 uint32_t D1VGA_CONTROL; 261 uint32_t D2VGA_CONTROL; 262 uint32_t D3VGA_CONTROL; 263 uint32_t D4VGA_CONTROL; 264 uint32_t VGA_TEST_CONTROL; 265 /* MMHUB registers. read only. temporary hack */ 266 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 267 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 268 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 269 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 270 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 271 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 272 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 273 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 274 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 275 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 276 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 277 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 278 }; 279 /* set field name */ 280 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 281 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 282 283 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 284 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 285 286 287 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 288 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 289 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 290 291 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 292 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 293 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 294 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 295 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 296 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 297 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 298 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 299 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 300 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 301 302 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 303 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 304 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 305 306 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 307 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 308 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 309 310 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 311 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 312 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 313 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 314 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 315 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 316 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 317 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 318 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 319 320 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 321 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 322 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 323 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ 324 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 325 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 326 327 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 328 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 329 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 330 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 331 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ 332 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ 333 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 334 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 335 336 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 337 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 338 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 339 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 340 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 341 342 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 343 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 344 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 345 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 346 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 347 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ 348 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 349 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 350 351 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 352 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 353 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 354 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 355 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 356 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ 357 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 358 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 359 360 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 361 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 362 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 363 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 364 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh) 365 366 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 367 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 368 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 369 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 370 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 371 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 372 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 373 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 374 /* todo: get these from GVM instead of reading registers ourselves */\ 375 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 376 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 377 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 378 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 379 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 380 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 381 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 382 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 383 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 384 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 385 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 386 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 387 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 388 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 389 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 390 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 391 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 392 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 393 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 394 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 395 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 396 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 397 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 398 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 399 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 400 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 401 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 402 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 403 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 404 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 405 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 406 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 407 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 408 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 409 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 410 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 411 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 412 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 413 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 414 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ 415 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 416 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \ 417 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \ 418 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 419 420 #define HWSEQ_REG_FIELD_LIST(type) \ 421 type DCFE_CLOCK_ENABLE; \ 422 type DCFEV_CLOCK_ENABLE; \ 423 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 424 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 425 type BLND_SCL_V_UPDATE_LOCK; \ 426 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 427 type BLND_BLND_V_UPDATE_LOCK; \ 428 type BLND_V_UPDATE_LOCK_MODE; \ 429 type BLND_FEEDTHROUGH_EN; \ 430 type BLND_ALPHA_MODE; \ 431 type BLND_MODE; \ 432 type BLND_MULTIPLIED_MODE; \ 433 type DP_DTO0_ENABLE; \ 434 type PIXEL_RATE_SOURCE; \ 435 type PHYPLL_PIXEL_RATE_SOURCE; \ 436 type PIXEL_RATE_PLL_SOURCE; \ 437 /* todo: get these from GVM instead of reading registers ourselves */\ 438 type PAGE_DIRECTORY_ENTRY_HI32;\ 439 type PAGE_DIRECTORY_ENTRY_LO32;\ 440 type LOGICAL_PAGE_NUMBER_HI4;\ 441 type LOGICAL_PAGE_NUMBER_LO32;\ 442 type PHYSICAL_PAGE_ADDR_HI4;\ 443 type PHYSICAL_PAGE_ADDR_LO32;\ 444 type PHYSICAL_PAGE_NUMBER_MSB;\ 445 type PHYSICAL_PAGE_NUMBER_LSB;\ 446 type LOGICAL_ADDR; \ 447 type ENABLE_L1_TLB;\ 448 type SYSTEM_ACCESS_MODE;\ 449 type LVTMA_BLON;\ 450 type LVTMA_PWRSEQ_TARGET_STATE_R;\ 451 type LVTMA_DIGON;\ 452 type LVTMA_DIGON_OVRD; 453 454 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 455 type HUBP_VTG_SEL; \ 456 type HUBP_CLOCK_ENABLE; \ 457 type DPP_CLOCK_ENABLE; \ 458 type SDPIF_FB_BASE;\ 459 type SDPIF_FB_OFFSET;\ 460 type SDPIF_AGP_BASE;\ 461 type SDPIF_AGP_BOT;\ 462 type SDPIF_AGP_TOP;\ 463 type FB_TOP;\ 464 type FB_BASE;\ 465 type FB_OFFSET;\ 466 type AGP_BASE;\ 467 type AGP_BOT;\ 468 type AGP_TOP;\ 469 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 470 type OPP_PIPE_CLOCK_EN;\ 471 type IP_REQUEST_EN; \ 472 type DOMAIN0_POWER_FORCEON; \ 473 type DOMAIN0_POWER_GATE; \ 474 type DOMAIN1_POWER_FORCEON; \ 475 type DOMAIN1_POWER_GATE; \ 476 type DOMAIN2_POWER_FORCEON; \ 477 type DOMAIN2_POWER_GATE; \ 478 type DOMAIN3_POWER_FORCEON; \ 479 type DOMAIN3_POWER_GATE; \ 480 type DOMAIN4_POWER_FORCEON; \ 481 type DOMAIN4_POWER_GATE; \ 482 type DOMAIN5_POWER_FORCEON; \ 483 type DOMAIN5_POWER_GATE; \ 484 type DOMAIN6_POWER_FORCEON; \ 485 type DOMAIN6_POWER_GATE; \ 486 type DOMAIN7_POWER_FORCEON; \ 487 type DOMAIN7_POWER_GATE; \ 488 type DOMAIN0_PGFSM_PWR_STATUS; \ 489 type DOMAIN1_PGFSM_PWR_STATUS; \ 490 type DOMAIN2_PGFSM_PWR_STATUS; \ 491 type DOMAIN3_PGFSM_PWR_STATUS; \ 492 type DOMAIN4_PGFSM_PWR_STATUS; \ 493 type DOMAIN5_PGFSM_PWR_STATUS; \ 494 type DOMAIN6_PGFSM_PWR_STATUS; \ 495 type DOMAIN7_PGFSM_PWR_STATUS; \ 496 type DCFCLK_GATE_DIS; \ 497 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 498 type VGA_TEST_ENABLE; \ 499 type VGA_TEST_RENDER_START; \ 500 type D1VGA_MODE_ENABLE; \ 501 type D2VGA_MODE_ENABLE; \ 502 type D3VGA_MODE_ENABLE; \ 503 type D4VGA_MODE_ENABLE; 504 505 struct dce_hwseq_shift { 506 HWSEQ_REG_FIELD_LIST(uint8_t) 507 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 508 }; 509 510 struct dce_hwseq_mask { 511 HWSEQ_REG_FIELD_LIST(uint32_t) 512 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 513 }; 514 515 516 enum blnd_mode { 517 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 518 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 519 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 520 }; 521 522 void dce_enable_fe_clock(struct dce_hwseq *hwss, 523 unsigned int inst, bool enable); 524 525 void dce_pipe_control_lock(struct dc *dc, 526 struct pipe_ctx *pipe, 527 bool lock); 528 529 void dce_set_blender_mode(struct dce_hwseq *hws, 530 unsigned int blnd_inst, enum blnd_mode mode); 531 532 void dce_clock_gating_power_up(struct dce_hwseq *hws, 533 bool enable); 534 535 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 536 struct clock_source *clk_src, 537 unsigned int tg_inst); 538 539 bool dce_use_lut(enum surface_pixel_format format); 540 #endif /*__DCE_HWSEQ_H__*/ 541