1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "hw_sequencer.h" 29 30 #define BL_REG_LIST()\ 31 SR(LVTMA_PWRSEQ_CNTL), \ 32 SR(LVTMA_PWRSEQ_STATE) 33 34 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 35 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 37 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 38 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 39 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 40 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 41 42 #define HWSEQ_DCEF_REG_LIST() \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 45 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 46 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 47 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 48 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 50 51 #define HWSEQ_BLND_REG_LIST() \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 54 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 55 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 56 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 57 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 58 SRII(BLND_CONTROL, BLND, 0), \ 59 SRII(BLND_CONTROL, BLND, 1), \ 60 SRII(BLND_CONTROL, BLND, 2), \ 61 SRII(BLND_CONTROL, BLND, 3), \ 62 SRII(BLND_CONTROL, BLND, 4), \ 63 SRII(BLND_CONTROL, BLND, 5) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #define HWSEQ_DCE11_REG_LIST_BASE() \ 82 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 83 SR(DCFEV_CLOCK_CONTROL), \ 84 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 85 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 86 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 87 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 88 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 89 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 90 SRII(BLND_CONTROL, BLND, 0),\ 91 SRII(BLND_CONTROL, BLND, 1),\ 92 SR(BLNDV_CONTROL),\ 93 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 94 BL_REG_LIST() 95 96 #define HWSEQ_DCE8_REG_LIST() \ 97 HWSEQ_DCEF_REG_LIST_DCE8(), \ 98 HWSEQ_BLND_REG_LIST(), \ 99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 100 BL_REG_LIST() 101 102 #define HWSEQ_DCE10_REG_LIST() \ 103 HWSEQ_DCEF_REG_LIST(), \ 104 HWSEQ_BLND_REG_LIST(), \ 105 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 106 BL_REG_LIST() 107 108 #define HWSEQ_ST_REG_LIST() \ 109 HWSEQ_DCE11_REG_LIST_BASE(), \ 110 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 111 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 112 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 113 .BLND_CONTROL[2] = mmBLNDV_CONTROL 114 115 #define HWSEQ_CZ_REG_LIST() \ 116 HWSEQ_DCE11_REG_LIST_BASE(), \ 117 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 118 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 119 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 120 SRII(BLND_CONTROL, BLND, 2), \ 121 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 122 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 123 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 124 .BLND_CONTROL[3] = mmBLNDV_CONTROL 125 126 #define HWSEQ_DCE120_REG_LIST() \ 127 HWSEQ_DCE10_REG_LIST(), \ 128 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 129 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 130 SR(DCHUB_FB_LOCATION),\ 131 SR(DCHUB_AGP_BASE),\ 132 SR(DCHUB_AGP_BOT),\ 133 SR(DCHUB_AGP_TOP), \ 134 BL_REG_LIST() 135 136 #define HWSEQ_VG20_REG_LIST() \ 137 HWSEQ_DCE120_REG_LIST(),\ 138 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 139 140 #define HWSEQ_DCE112_REG_LIST() \ 141 HWSEQ_DCE10_REG_LIST(), \ 142 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 143 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 144 BL_REG_LIST() 145 146 #define HWSEQ_DCN_REG_LIST()\ 147 SR(REFCLK_CNTL), \ 148 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 149 SR(DIO_MEM_PWR_CTRL), \ 150 SR(DCCG_GATE_DISABLE_CNTL), \ 151 SR(DCCG_GATE_DISABLE_CNTL2), \ 152 SR(DCFCLK_CNTL),\ 153 SR(DCFCLK_CNTL), \ 154 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 155 /* todo: get these from GVM instead of reading registers ourselves */\ 156 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 157 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 158 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 159 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 160 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 161 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 162 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 163 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 164 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 165 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 166 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 167 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 168 169 #define HWSEQ_DCN1_REG_LIST()\ 170 HWSEQ_DCN_REG_LIST(), \ 171 HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ 172 HWSEQ_PHYPLL_REG_LIST(OTG), \ 173 SR(DCHUBBUB_SDPIF_FB_BASE),\ 174 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 175 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 176 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 177 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 178 SR(DOMAIN0_PG_CONFIG), \ 179 SR(DOMAIN1_PG_CONFIG), \ 180 SR(DOMAIN2_PG_CONFIG), \ 181 SR(DOMAIN3_PG_CONFIG), \ 182 SR(DOMAIN4_PG_CONFIG), \ 183 SR(DOMAIN5_PG_CONFIG), \ 184 SR(DOMAIN6_PG_CONFIG), \ 185 SR(DOMAIN7_PG_CONFIG), \ 186 SR(DOMAIN0_PG_STATUS), \ 187 SR(DOMAIN1_PG_STATUS), \ 188 SR(DOMAIN2_PG_STATUS), \ 189 SR(DOMAIN3_PG_STATUS), \ 190 SR(DOMAIN4_PG_STATUS), \ 191 SR(DOMAIN5_PG_STATUS), \ 192 SR(DOMAIN6_PG_STATUS), \ 193 SR(DOMAIN7_PG_STATUS), \ 194 SR(D1VGA_CONTROL), \ 195 SR(D2VGA_CONTROL), \ 196 SR(D3VGA_CONTROL), \ 197 SR(D4VGA_CONTROL), \ 198 SR(VGA_TEST_CONTROL), \ 199 SR(DC_IP_REQUEST_CNTL), \ 200 BL_REG_LIST() 201 202 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 203 #define HWSEQ_DCN2_REG_LIST()\ 204 HWSEQ_DCN_REG_LIST(), \ 205 HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ 206 HWSEQ_PHYPLL_REG_LIST(OTG), \ 207 SR(MICROSECOND_TIME_BASE_DIV), \ 208 SR(MILLISECOND_TIME_BASE_DIV), \ 209 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 210 SR(RBBMIF_TIMEOUT_DIS), \ 211 SR(RBBMIF_TIMEOUT_DIS_2), \ 212 SR(DCHUBBUB_CRC_CTRL), \ 213 SR(DPP_TOP0_DPP_CRC_CTRL), \ 214 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 215 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 216 SR(MPC_CRC_CTRL), \ 217 SR(MPC_CRC_RESULT_GB), \ 218 SR(MPC_CRC_RESULT_C), \ 219 SR(MPC_CRC_RESULT_AR), \ 220 SR(DOMAIN0_PG_CONFIG), \ 221 SR(DOMAIN1_PG_CONFIG), \ 222 SR(DOMAIN2_PG_CONFIG), \ 223 SR(DOMAIN3_PG_CONFIG), \ 224 SR(DOMAIN4_PG_CONFIG), \ 225 SR(DOMAIN5_PG_CONFIG), \ 226 SR(DOMAIN6_PG_CONFIG), \ 227 SR(DOMAIN7_PG_CONFIG), \ 228 SR(DOMAIN8_PG_CONFIG), \ 229 SR(DOMAIN9_PG_CONFIG), \ 230 SR(DOMAIN10_PG_CONFIG), \ 231 SR(DOMAIN11_PG_CONFIG), \ 232 SR(DOMAIN16_PG_CONFIG), \ 233 SR(DOMAIN17_PG_CONFIG), \ 234 SR(DOMAIN18_PG_CONFIG), \ 235 SR(DOMAIN19_PG_CONFIG), \ 236 SR(DOMAIN20_PG_CONFIG), \ 237 SR(DOMAIN21_PG_CONFIG), \ 238 SR(DOMAIN0_PG_STATUS), \ 239 SR(DOMAIN1_PG_STATUS), \ 240 SR(DOMAIN2_PG_STATUS), \ 241 SR(DOMAIN3_PG_STATUS), \ 242 SR(DOMAIN4_PG_STATUS), \ 243 SR(DOMAIN5_PG_STATUS), \ 244 SR(DOMAIN6_PG_STATUS), \ 245 SR(DOMAIN7_PG_STATUS), \ 246 SR(DOMAIN8_PG_STATUS), \ 247 SR(DOMAIN9_PG_STATUS), \ 248 SR(DOMAIN10_PG_STATUS), \ 249 SR(DOMAIN11_PG_STATUS), \ 250 SR(DOMAIN16_PG_STATUS), \ 251 SR(DOMAIN17_PG_STATUS), \ 252 SR(DOMAIN18_PG_STATUS), \ 253 SR(DOMAIN19_PG_STATUS), \ 254 SR(DOMAIN20_PG_STATUS), \ 255 SR(DOMAIN21_PG_STATUS), \ 256 SR(D1VGA_CONTROL), \ 257 SR(D2VGA_CONTROL), \ 258 SR(D3VGA_CONTROL), \ 259 SR(D4VGA_CONTROL), \ 260 SR(D5VGA_CONTROL), \ 261 SR(D6VGA_CONTROL), \ 262 SR(DC_IP_REQUEST_CNTL), \ 263 BL_REG_LIST() 264 #endif 265 266 struct dce_hwseq_registers { 267 268 /* Backlight registers */ 269 uint32_t LVTMA_PWRSEQ_CNTL; 270 uint32_t LVTMA_PWRSEQ_STATE; 271 272 uint32_t DCFE_CLOCK_CONTROL[6]; 273 uint32_t DCFEV_CLOCK_CONTROL; 274 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 275 uint32_t BLND_V_UPDATE_LOCK[6]; 276 uint32_t BLND_CONTROL[6]; 277 uint32_t BLNDV_CONTROL; 278 uint32_t CRTC_H_BLANK_START_END[6]; 279 uint32_t PIXEL_RATE_CNTL[6]; 280 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 281 /*DCHUB*/ 282 uint32_t DCHUB_FB_LOCATION; 283 uint32_t DCHUB_AGP_BASE; 284 uint32_t DCHUB_AGP_BOT; 285 uint32_t DCHUB_AGP_TOP; 286 287 uint32_t REFCLK_CNTL; 288 289 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 290 uint32_t DCHUBBUB_SDPIF_FB_BASE; 291 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 292 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 293 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 294 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 295 uint32_t DC_IP_REQUEST_CNTL; 296 uint32_t DOMAIN0_PG_CONFIG; 297 uint32_t DOMAIN1_PG_CONFIG; 298 uint32_t DOMAIN2_PG_CONFIG; 299 uint32_t DOMAIN3_PG_CONFIG; 300 uint32_t DOMAIN4_PG_CONFIG; 301 uint32_t DOMAIN5_PG_CONFIG; 302 uint32_t DOMAIN6_PG_CONFIG; 303 uint32_t DOMAIN7_PG_CONFIG; 304 uint32_t DOMAIN8_PG_CONFIG; 305 uint32_t DOMAIN9_PG_CONFIG; 306 uint32_t DOMAIN10_PG_CONFIG; 307 uint32_t DOMAIN11_PG_CONFIG; 308 uint32_t DOMAIN16_PG_CONFIG; 309 uint32_t DOMAIN17_PG_CONFIG; 310 uint32_t DOMAIN18_PG_CONFIG; 311 uint32_t DOMAIN19_PG_CONFIG; 312 uint32_t DOMAIN20_PG_CONFIG; 313 uint32_t DOMAIN21_PG_CONFIG; 314 uint32_t DOMAIN0_PG_STATUS; 315 uint32_t DOMAIN1_PG_STATUS; 316 uint32_t DOMAIN2_PG_STATUS; 317 uint32_t DOMAIN3_PG_STATUS; 318 uint32_t DOMAIN4_PG_STATUS; 319 uint32_t DOMAIN5_PG_STATUS; 320 uint32_t DOMAIN6_PG_STATUS; 321 uint32_t DOMAIN7_PG_STATUS; 322 uint32_t DOMAIN8_PG_STATUS; 323 uint32_t DOMAIN9_PG_STATUS; 324 uint32_t DOMAIN10_PG_STATUS; 325 uint32_t DOMAIN11_PG_STATUS; 326 uint32_t DOMAIN16_PG_STATUS; 327 uint32_t DOMAIN17_PG_STATUS; 328 uint32_t DOMAIN18_PG_STATUS; 329 uint32_t DOMAIN19_PG_STATUS; 330 uint32_t DOMAIN20_PG_STATUS; 331 uint32_t DOMAIN21_PG_STATUS; 332 uint32_t DIO_MEM_PWR_CTRL; 333 uint32_t DCCG_GATE_DISABLE_CNTL; 334 uint32_t DCCG_GATE_DISABLE_CNTL2; 335 uint32_t DCFCLK_CNTL; 336 uint32_t MICROSECOND_TIME_BASE_DIV; 337 uint32_t MILLISECOND_TIME_BASE_DIV; 338 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 339 uint32_t RBBMIF_TIMEOUT_DIS; 340 uint32_t RBBMIF_TIMEOUT_DIS_2; 341 uint32_t DCHUBBUB_CRC_CTRL; 342 uint32_t DPP_TOP0_DPP_CRC_CTRL; 343 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 344 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 345 uint32_t MPC_CRC_CTRL; 346 uint32_t MPC_CRC_RESULT_GB; 347 uint32_t MPC_CRC_RESULT_C; 348 uint32_t MPC_CRC_RESULT_AR; 349 uint32_t D1VGA_CONTROL; 350 uint32_t D2VGA_CONTROL; 351 uint32_t D3VGA_CONTROL; 352 uint32_t D4VGA_CONTROL; 353 uint32_t D5VGA_CONTROL; 354 uint32_t D6VGA_CONTROL; 355 uint32_t VGA_TEST_CONTROL; 356 /* MMHUB registers. read only. temporary hack */ 357 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 358 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 359 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 360 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 361 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 362 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 363 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 364 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 365 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 366 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 367 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 368 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 369 uint32_t MC_VM_XGMI_LFB_CNTL; 370 uint32_t AZALIA_AUDIO_DTO; 371 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 372 }; 373 /* set field name */ 374 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 375 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 376 377 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 378 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 379 380 381 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 382 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 383 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 384 385 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 386 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 387 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 388 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 389 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 390 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 391 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 392 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 393 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 394 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 395 396 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 397 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 398 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 399 400 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 401 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 402 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 403 404 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 405 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 406 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 407 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 408 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 409 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 410 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 411 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 412 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 413 414 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 415 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 416 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 417 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ 418 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 419 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 420 421 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 422 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 423 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 424 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 425 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ 426 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ 427 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 428 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 429 430 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 431 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 432 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 433 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 434 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 435 436 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 437 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 438 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 439 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 440 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 441 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ 442 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 443 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 444 445 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 446 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 447 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 448 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 449 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 450 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ 451 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 452 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 453 454 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 455 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 456 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 457 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 458 459 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 460 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 461 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 462 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 463 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 464 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 465 466 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 467 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 468 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 469 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 470 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 471 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 472 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 473 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 474 /* todo: get these from GVM instead of reading registers ourselves */\ 475 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 476 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 477 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 478 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 479 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 480 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 481 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 482 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 483 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 484 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 485 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 486 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 487 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 488 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 489 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 490 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 491 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 492 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 493 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 494 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 495 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 496 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 497 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 498 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 499 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 500 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 501 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 502 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 503 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 504 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 505 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 506 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 507 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 508 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 509 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 510 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 511 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 512 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 513 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 514 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ 515 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 516 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \ 517 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \ 518 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 519 520 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 521 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 522 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 523 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 524 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 525 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 526 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 527 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 528 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 529 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 530 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 531 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 532 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 533 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 534 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 535 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 536 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 537 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 538 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 539 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 540 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 541 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 542 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 543 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 544 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 545 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 546 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 547 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 548 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 549 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 550 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 551 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 552 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 553 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 554 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 555 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 556 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 557 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 558 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 559 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 560 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 561 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 562 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 563 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 564 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 565 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 566 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 567 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 568 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 569 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 570 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 571 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 572 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 573 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 574 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 575 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 576 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 577 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 578 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 579 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 580 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 581 #endif 582 583 #define HWSEQ_REG_FIELD_LIST(type) \ 584 type DCFE_CLOCK_ENABLE; \ 585 type DCFEV_CLOCK_ENABLE; \ 586 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 587 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 588 type BLND_SCL_V_UPDATE_LOCK; \ 589 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 590 type BLND_BLND_V_UPDATE_LOCK; \ 591 type BLND_V_UPDATE_LOCK_MODE; \ 592 type BLND_FEEDTHROUGH_EN; \ 593 type BLND_ALPHA_MODE; \ 594 type BLND_MODE; \ 595 type BLND_MULTIPLIED_MODE; \ 596 type DP_DTO0_ENABLE; \ 597 type PIXEL_RATE_SOURCE; \ 598 type PHYPLL_PIXEL_RATE_SOURCE; \ 599 type PIXEL_RATE_PLL_SOURCE; \ 600 /* todo: get these from GVM instead of reading registers ourselves */\ 601 type PAGE_DIRECTORY_ENTRY_HI32;\ 602 type PAGE_DIRECTORY_ENTRY_LO32;\ 603 type LOGICAL_PAGE_NUMBER_HI4;\ 604 type LOGICAL_PAGE_NUMBER_LO32;\ 605 type PHYSICAL_PAGE_ADDR_HI4;\ 606 type PHYSICAL_PAGE_ADDR_LO32;\ 607 type PHYSICAL_PAGE_NUMBER_MSB;\ 608 type PHYSICAL_PAGE_NUMBER_LSB;\ 609 type LOGICAL_ADDR; \ 610 type PF_LFB_REGION;\ 611 type PF_MAX_REGION;\ 612 type ENABLE_L1_TLB;\ 613 type SYSTEM_ACCESS_MODE;\ 614 type LVTMA_BLON;\ 615 type LVTMA_PWRSEQ_TARGET_STATE_R;\ 616 type LVTMA_DIGON;\ 617 type LVTMA_DIGON_OVRD; 618 619 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 620 type HUBP_VTG_SEL; \ 621 type HUBP_CLOCK_ENABLE; \ 622 type DPP_CLOCK_ENABLE; \ 623 type SDPIF_FB_BASE;\ 624 type SDPIF_FB_OFFSET;\ 625 type SDPIF_AGP_BASE;\ 626 type SDPIF_AGP_BOT;\ 627 type SDPIF_AGP_TOP;\ 628 type FB_TOP;\ 629 type FB_BASE;\ 630 type FB_OFFSET;\ 631 type AGP_BASE;\ 632 type AGP_BOT;\ 633 type AGP_TOP;\ 634 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 635 type OPP_PIPE_CLOCK_EN;\ 636 type IP_REQUEST_EN; \ 637 type DOMAIN0_POWER_FORCEON; \ 638 type DOMAIN0_POWER_GATE; \ 639 type DOMAIN1_POWER_FORCEON; \ 640 type DOMAIN1_POWER_GATE; \ 641 type DOMAIN2_POWER_FORCEON; \ 642 type DOMAIN2_POWER_GATE; \ 643 type DOMAIN3_POWER_FORCEON; \ 644 type DOMAIN3_POWER_GATE; \ 645 type DOMAIN4_POWER_FORCEON; \ 646 type DOMAIN4_POWER_GATE; \ 647 type DOMAIN5_POWER_FORCEON; \ 648 type DOMAIN5_POWER_GATE; \ 649 type DOMAIN6_POWER_FORCEON; \ 650 type DOMAIN6_POWER_GATE; \ 651 type DOMAIN7_POWER_FORCEON; \ 652 type DOMAIN7_POWER_GATE; \ 653 type DOMAIN8_POWER_FORCEON; \ 654 type DOMAIN8_POWER_GATE; \ 655 type DOMAIN9_POWER_FORCEON; \ 656 type DOMAIN9_POWER_GATE; \ 657 type DOMAIN10_POWER_FORCEON; \ 658 type DOMAIN10_POWER_GATE; \ 659 type DOMAIN11_POWER_FORCEON; \ 660 type DOMAIN11_POWER_GATE; \ 661 type DOMAIN16_POWER_FORCEON; \ 662 type DOMAIN16_POWER_GATE; \ 663 type DOMAIN17_POWER_FORCEON; \ 664 type DOMAIN17_POWER_GATE; \ 665 type DOMAIN18_POWER_FORCEON; \ 666 type DOMAIN18_POWER_GATE; \ 667 type DOMAIN19_POWER_FORCEON; \ 668 type DOMAIN19_POWER_GATE; \ 669 type DOMAIN20_POWER_FORCEON; \ 670 type DOMAIN20_POWER_GATE; \ 671 type DOMAIN21_POWER_FORCEON; \ 672 type DOMAIN21_POWER_GATE; \ 673 type DOMAIN0_PGFSM_PWR_STATUS; \ 674 type DOMAIN1_PGFSM_PWR_STATUS; \ 675 type DOMAIN2_PGFSM_PWR_STATUS; \ 676 type DOMAIN3_PGFSM_PWR_STATUS; \ 677 type DOMAIN4_PGFSM_PWR_STATUS; \ 678 type DOMAIN5_PGFSM_PWR_STATUS; \ 679 type DOMAIN6_PGFSM_PWR_STATUS; \ 680 type DOMAIN7_PGFSM_PWR_STATUS; \ 681 type DOMAIN8_PGFSM_PWR_STATUS; \ 682 type DOMAIN9_PGFSM_PWR_STATUS; \ 683 type DOMAIN10_PGFSM_PWR_STATUS; \ 684 type DOMAIN11_PGFSM_PWR_STATUS; \ 685 type DOMAIN16_PGFSM_PWR_STATUS; \ 686 type DOMAIN17_PGFSM_PWR_STATUS; \ 687 type DOMAIN18_PGFSM_PWR_STATUS; \ 688 type DOMAIN19_PGFSM_PWR_STATUS; \ 689 type DOMAIN20_PGFSM_PWR_STATUS; \ 690 type DOMAIN21_PGFSM_PWR_STATUS; \ 691 type DCFCLK_GATE_DIS; \ 692 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 693 type VGA_TEST_ENABLE; \ 694 type VGA_TEST_RENDER_START; \ 695 type D1VGA_MODE_ENABLE; \ 696 type D2VGA_MODE_ENABLE; \ 697 type D3VGA_MODE_ENABLE; \ 698 type D4VGA_MODE_ENABLE; \ 699 type AZALIA_AUDIO_DTO_MODULE; 700 701 struct dce_hwseq_shift { 702 HWSEQ_REG_FIELD_LIST(uint8_t) 703 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 704 }; 705 706 struct dce_hwseq_mask { 707 HWSEQ_REG_FIELD_LIST(uint32_t) 708 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 709 }; 710 711 712 enum blnd_mode { 713 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 714 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 715 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 716 }; 717 718 void dce_enable_fe_clock(struct dce_hwseq *hwss, 719 unsigned int inst, bool enable); 720 721 void dce_pipe_control_lock(struct dc *dc, 722 struct pipe_ctx *pipe, 723 bool lock); 724 725 void dce_set_blender_mode(struct dce_hwseq *hws, 726 unsigned int blnd_inst, enum blnd_mode mode); 727 728 void dce_clock_gating_power_up(struct dce_hwseq *hws, 729 bool enable); 730 731 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 732 struct clock_source *clk_src, 733 unsigned int tg_inst); 734 735 bool dce_use_lut(enum surface_pixel_format format); 736 #endif /*__DCE_HWSEQ_H__*/ 737