1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "hw_sequencer.h" 29 30 #define BL_REG_LIST()\ 31 SR(LVTMA_PWRSEQ_CNTL), \ 32 SR(LVTMA_PWRSEQ_STATE) 33 34 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 35 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 37 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 38 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 39 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 40 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 41 42 #define HWSEQ_DCEF_REG_LIST() \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 45 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 46 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 47 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 48 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 50 51 #define HWSEQ_BLND_REG_LIST() \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 54 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 55 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 56 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 57 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 58 SRII(BLND_CONTROL, BLND, 0), \ 59 SRII(BLND_CONTROL, BLND, 1), \ 60 SRII(BLND_CONTROL, BLND, 2), \ 61 SRII(BLND_CONTROL, BLND, 3), \ 62 SRII(BLND_CONTROL, BLND, 4), \ 63 SRII(BLND_CONTROL, BLND, 5) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #define HWSEQ_DCE11_REG_LIST_BASE() \ 82 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 83 SR(DCFEV_CLOCK_CONTROL), \ 84 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 85 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 86 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 87 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 88 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 89 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 90 SRII(BLND_CONTROL, BLND, 0),\ 91 SRII(BLND_CONTROL, BLND, 1),\ 92 SR(BLNDV_CONTROL),\ 93 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 94 BL_REG_LIST() 95 96 #define HWSEQ_DCE8_REG_LIST() \ 97 HWSEQ_DCEF_REG_LIST_DCE8(), \ 98 HWSEQ_BLND_REG_LIST(), \ 99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 100 BL_REG_LIST() 101 102 #define HWSEQ_DCE10_REG_LIST() \ 103 HWSEQ_DCEF_REG_LIST(), \ 104 HWSEQ_BLND_REG_LIST(), \ 105 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 106 BL_REG_LIST() 107 108 #define HWSEQ_ST_REG_LIST() \ 109 HWSEQ_DCE11_REG_LIST_BASE(), \ 110 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 111 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 112 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 113 .BLND_CONTROL[2] = mmBLNDV_CONTROL 114 115 #define HWSEQ_CZ_REG_LIST() \ 116 HWSEQ_DCE11_REG_LIST_BASE(), \ 117 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 118 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 119 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 120 SRII(BLND_CONTROL, BLND, 2), \ 121 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 122 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 123 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 124 .BLND_CONTROL[3] = mmBLNDV_CONTROL 125 126 #define HWSEQ_DCE120_REG_LIST() \ 127 HWSEQ_DCE10_REG_LIST(), \ 128 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 129 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 130 SR(DCHUB_FB_LOCATION),\ 131 SR(DCHUB_AGP_BASE),\ 132 SR(DCHUB_AGP_BOT),\ 133 SR(DCHUB_AGP_TOP), \ 134 BL_REG_LIST() 135 136 #define HWSEQ_DCE112_REG_LIST() \ 137 HWSEQ_DCE10_REG_LIST(), \ 138 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 139 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 140 BL_REG_LIST() 141 142 #define HWSEQ_DCN_REG_LIST()\ 143 SRII(DCHUBP_CNTL, HUBP, 0), \ 144 SRII(DCHUBP_CNTL, HUBP, 1), \ 145 SRII(DCHUBP_CNTL, HUBP, 2), \ 146 SRII(DCHUBP_CNTL, HUBP, 3), \ 147 SRII(HUBP_CLK_CNTL, HUBP, 0), \ 148 SRII(HUBP_CLK_CNTL, HUBP, 1), \ 149 SRII(HUBP_CLK_CNTL, HUBP, 2), \ 150 SRII(HUBP_CLK_CNTL, HUBP, 3), \ 151 SRII(DPP_CONTROL, DPP_TOP, 0), \ 152 SRII(DPP_CONTROL, DPP_TOP, 1), \ 153 SRII(DPP_CONTROL, DPP_TOP, 2), \ 154 SRII(DPP_CONTROL, DPP_TOP, 3), \ 155 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \ 156 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \ 157 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \ 158 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \ 159 SR(REFCLK_CNTL), \ 160 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 161 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ 162 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ 163 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 164 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ 165 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ 166 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 167 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ 168 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ 169 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 170 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\ 171 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ 172 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 173 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ 174 SR(DCHUBBUB_ARB_SAT_LEVEL),\ 175 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ 176 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 177 SR(DCHUBBUB_TEST_DEBUG_INDEX), \ 178 SR(DCHUBBUB_TEST_DEBUG_DATA), \ 179 SR(DIO_MEM_PWR_CTRL), \ 180 SR(DCCG_GATE_DISABLE_CNTL), \ 181 SR(DCCG_GATE_DISABLE_CNTL2), \ 182 SR(DCFCLK_CNTL),\ 183 SR(DCFCLK_CNTL), \ 184 /* todo: get these from GVM instead of reading registers ourselves */\ 185 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 186 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 187 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 188 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 189 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 190 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 191 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 192 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 193 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 194 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 195 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 196 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 197 198 #define HWSEQ_SR_WATERMARK_REG_LIST()\ 199 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ 200 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ 201 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ 202 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ 203 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ 204 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ 205 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ 206 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D) 207 208 #define HWSEQ_DCN1_REG_LIST()\ 209 HWSEQ_DCN_REG_LIST(), \ 210 HWSEQ_SR_WATERMARK_REG_LIST(), \ 211 HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ 212 HWSEQ_PHYPLL_REG_LIST(OTG), \ 213 SR(DCHUBBUB_SDPIF_FB_TOP),\ 214 SR(DCHUBBUB_SDPIF_FB_BASE),\ 215 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 216 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 217 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 218 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 219 SR(DOMAIN0_PG_CONFIG), \ 220 SR(DOMAIN1_PG_CONFIG), \ 221 SR(DOMAIN2_PG_CONFIG), \ 222 SR(DOMAIN3_PG_CONFIG), \ 223 SR(DOMAIN4_PG_CONFIG), \ 224 SR(DOMAIN5_PG_CONFIG), \ 225 SR(DOMAIN6_PG_CONFIG), \ 226 SR(DOMAIN7_PG_CONFIG), \ 227 SR(DOMAIN0_PG_STATUS), \ 228 SR(DOMAIN1_PG_STATUS), \ 229 SR(DOMAIN2_PG_STATUS), \ 230 SR(DOMAIN3_PG_STATUS), \ 231 SR(DOMAIN4_PG_STATUS), \ 232 SR(DOMAIN5_PG_STATUS), \ 233 SR(DOMAIN6_PG_STATUS), \ 234 SR(DOMAIN7_PG_STATUS), \ 235 SR(D1VGA_CONTROL), \ 236 SR(D2VGA_CONTROL), \ 237 SR(D3VGA_CONTROL), \ 238 SR(D4VGA_CONTROL), \ 239 SR(DC_IP_REQUEST_CNTL), \ 240 BL_REG_LIST() 241 242 struct dce_hwseq_registers { 243 244 /* Backlight registers */ 245 uint32_t LVTMA_PWRSEQ_CNTL; 246 uint32_t LVTMA_PWRSEQ_STATE; 247 248 uint32_t DCFE_CLOCK_CONTROL[6]; 249 uint32_t DCFEV_CLOCK_CONTROL; 250 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 251 uint32_t BLND_V_UPDATE_LOCK[6]; 252 uint32_t BLND_CONTROL[6]; 253 uint32_t BLNDV_CONTROL; 254 uint32_t CRTC_H_BLANK_START_END[6]; 255 uint32_t PIXEL_RATE_CNTL[6]; 256 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 257 /*DCHUB*/ 258 uint32_t DCHUB_FB_LOCATION; 259 uint32_t DCHUB_AGP_BASE; 260 uint32_t DCHUB_AGP_BOT; 261 uint32_t DCHUB_AGP_TOP; 262 263 uint32_t DCHUBP_CNTL[4]; 264 uint32_t HUBP_CLK_CNTL[4]; 265 uint32_t DPP_CONTROL[4]; 266 uint32_t OPP_PIPE_CONTROL[4]; 267 uint32_t REFCLK_CNTL; 268 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; 269 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; 270 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; 271 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; 272 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; 273 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; 274 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; 275 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; 276 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; 277 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; 278 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; 279 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; 280 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; 281 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; 282 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; 283 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; 284 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; 285 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; 286 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; 287 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; 288 uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; 289 uint32_t DCHUBBUB_ARB_SAT_LEVEL; 290 uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; 291 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 292 uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; 293 uint32_t DCHUBBUB_TEST_DEBUG_INDEX; 294 uint32_t DCHUBBUB_TEST_DEBUG_DATA; 295 uint32_t DCHUBBUB_SDPIF_FB_TOP; 296 uint32_t DCHUBBUB_SDPIF_FB_BASE; 297 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 298 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 299 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 300 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 301 uint32_t DC_IP_REQUEST_CNTL; 302 uint32_t DOMAIN0_PG_CONFIG; 303 uint32_t DOMAIN1_PG_CONFIG; 304 uint32_t DOMAIN2_PG_CONFIG; 305 uint32_t DOMAIN3_PG_CONFIG; 306 uint32_t DOMAIN4_PG_CONFIG; 307 uint32_t DOMAIN5_PG_CONFIG; 308 uint32_t DOMAIN6_PG_CONFIG; 309 uint32_t DOMAIN7_PG_CONFIG; 310 uint32_t DOMAIN0_PG_STATUS; 311 uint32_t DOMAIN1_PG_STATUS; 312 uint32_t DOMAIN2_PG_STATUS; 313 uint32_t DOMAIN3_PG_STATUS; 314 uint32_t DOMAIN4_PG_STATUS; 315 uint32_t DOMAIN5_PG_STATUS; 316 uint32_t DOMAIN6_PG_STATUS; 317 uint32_t DOMAIN7_PG_STATUS; 318 uint32_t DIO_MEM_PWR_CTRL; 319 uint32_t DCCG_GATE_DISABLE_CNTL; 320 uint32_t DCCG_GATE_DISABLE_CNTL2; 321 uint32_t DCFCLK_CNTL; 322 uint32_t MICROSECOND_TIME_BASE_DIV; 323 uint32_t MILLISECOND_TIME_BASE_DIV; 324 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 325 uint32_t RBBMIF_TIMEOUT_DIS; 326 uint32_t RBBMIF_TIMEOUT_DIS_2; 327 uint32_t DENTIST_DISPCLK_CNTL; 328 uint32_t DCHUBBUB_CRC_CTRL; 329 uint32_t DPP_TOP0_DPP_CRC_CTRL; 330 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 331 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 332 uint32_t MPC_CRC_CTRL; 333 uint32_t MPC_CRC_RESULT_GB; 334 uint32_t MPC_CRC_RESULT_C; 335 uint32_t MPC_CRC_RESULT_AR; 336 uint32_t D1VGA_CONTROL; 337 uint32_t D2VGA_CONTROL; 338 uint32_t D3VGA_CONTROL; 339 uint32_t D4VGA_CONTROL; 340 /* MMHUB registers. read only. temporary hack */ 341 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 342 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 343 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 344 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 345 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 346 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 347 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 348 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 349 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 350 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 351 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 352 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 353 }; 354 /* set field name */ 355 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 356 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 357 358 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 359 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 360 361 362 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 363 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 364 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 365 366 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 367 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 368 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 369 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 370 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 371 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 372 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 373 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 374 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 375 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 376 377 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 378 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 379 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 380 381 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 382 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 383 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 384 385 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 386 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 387 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 388 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 389 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 390 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 391 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 392 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 393 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 394 395 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 396 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 397 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 398 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ 399 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 400 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 401 402 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 403 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 404 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 405 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 406 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 407 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 408 409 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 410 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 411 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 412 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 413 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 414 415 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 416 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 417 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 418 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 419 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 420 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ 421 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 422 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 423 424 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 425 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 426 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 427 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 428 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 429 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ 430 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 431 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 432 433 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 434 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 435 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 436 HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \ 437 HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \ 438 HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ 439 HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\ 440 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 441 HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ 442 HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ 443 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ 444 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ 445 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ 446 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ 447 HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ 448 HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ 449 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh) 450 451 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 452 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 453 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 454 HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ 455 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 456 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 457 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 458 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 459 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 460 HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh), \ 461 /* todo: get these from GVM instead of reading registers ourselves */\ 462 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 463 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 464 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 465 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 466 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 467 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 468 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 469 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 470 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 471 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 472 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 473 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 474 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 475 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 476 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 477 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 478 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 479 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 480 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 481 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 482 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 483 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 484 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 485 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 486 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 487 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 488 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 489 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 490 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 491 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 492 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 493 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 494 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 495 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 496 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 497 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 498 499 #define HWSEQ_REG_FIELD_LIST(type) \ 500 type DCFE_CLOCK_ENABLE; \ 501 type DCFEV_CLOCK_ENABLE; \ 502 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 503 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 504 type BLND_SCL_V_UPDATE_LOCK; \ 505 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 506 type BLND_BLND_V_UPDATE_LOCK; \ 507 type BLND_V_UPDATE_LOCK_MODE; \ 508 type BLND_FEEDTHROUGH_EN; \ 509 type BLND_ALPHA_MODE; \ 510 type BLND_MODE; \ 511 type BLND_MULTIPLIED_MODE; \ 512 type DP_DTO0_ENABLE; \ 513 type PIXEL_RATE_SOURCE; \ 514 type PHYPLL_PIXEL_RATE_SOURCE; \ 515 type PIXEL_RATE_PLL_SOURCE; \ 516 /* todo: get these from GVM instead of reading registers ourselves */\ 517 type PAGE_DIRECTORY_ENTRY_HI32;\ 518 type PAGE_DIRECTORY_ENTRY_LO32;\ 519 type LOGICAL_PAGE_NUMBER_HI4;\ 520 type LOGICAL_PAGE_NUMBER_LO32;\ 521 type PHYSICAL_PAGE_ADDR_HI4;\ 522 type PHYSICAL_PAGE_ADDR_LO32;\ 523 type PHYSICAL_PAGE_NUMBER_MSB;\ 524 type PHYSICAL_PAGE_NUMBER_LSB;\ 525 type LOGICAL_ADDR; \ 526 type ENABLE_L1_TLB;\ 527 type SYSTEM_ACCESS_MODE;\ 528 type LVTMA_BLON;\ 529 type LVTMA_PWRSEQ_TARGET_STATE_R; 530 531 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 532 type HUBP_VTG_SEL; \ 533 type HUBP_CLOCK_ENABLE; \ 534 type DPP_CLOCK_ENABLE; \ 535 type DPPCLK_RATE_CONTROL; \ 536 type SDPIF_FB_TOP;\ 537 type SDPIF_FB_BASE;\ 538 type SDPIF_FB_OFFSET;\ 539 type SDPIF_AGP_BASE;\ 540 type SDPIF_AGP_BOT;\ 541 type SDPIF_AGP_TOP;\ 542 type FB_TOP;\ 543 type FB_BASE;\ 544 type FB_OFFSET;\ 545 type AGP_BASE;\ 546 type AGP_BOT;\ 547 type AGP_TOP;\ 548 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 549 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ 550 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ 551 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ 552 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ 553 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\ 554 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\ 555 type DCHUBBUB_ARB_SAT_LEVEL;\ 556 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ 557 type OPP_PIPE_CLOCK_EN;\ 558 type IP_REQUEST_EN; \ 559 type DOMAIN0_POWER_FORCEON; \ 560 type DOMAIN0_POWER_GATE; \ 561 type DOMAIN1_POWER_FORCEON; \ 562 type DOMAIN1_POWER_GATE; \ 563 type DOMAIN2_POWER_FORCEON; \ 564 type DOMAIN2_POWER_GATE; \ 565 type DOMAIN3_POWER_FORCEON; \ 566 type DOMAIN3_POWER_GATE; \ 567 type DOMAIN4_POWER_FORCEON; \ 568 type DOMAIN4_POWER_GATE; \ 569 type DOMAIN5_POWER_FORCEON; \ 570 type DOMAIN5_POWER_GATE; \ 571 type DOMAIN6_POWER_FORCEON; \ 572 type DOMAIN6_POWER_GATE; \ 573 type DOMAIN7_POWER_FORCEON; \ 574 type DOMAIN7_POWER_GATE; \ 575 type DOMAIN0_PGFSM_PWR_STATUS; \ 576 type DOMAIN1_PGFSM_PWR_STATUS; \ 577 type DOMAIN2_PGFSM_PWR_STATUS; \ 578 type DOMAIN3_PGFSM_PWR_STATUS; \ 579 type DOMAIN4_PGFSM_PWR_STATUS; \ 580 type DOMAIN5_PGFSM_PWR_STATUS; \ 581 type DOMAIN6_PGFSM_PWR_STATUS; \ 582 type DOMAIN7_PGFSM_PWR_STATUS; \ 583 type DCFCLK_GATE_DIS; \ 584 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 585 type DENTIST_DPPCLK_WDIVIDER; \ 586 type DENTIST_DISPCLK_WDIVIDER; 587 588 struct dce_hwseq_shift { 589 HWSEQ_REG_FIELD_LIST(uint8_t) 590 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 591 }; 592 593 struct dce_hwseq_mask { 594 HWSEQ_REG_FIELD_LIST(uint32_t) 595 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 596 }; 597 598 599 enum blnd_mode { 600 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 601 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 602 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 603 }; 604 605 void dce_enable_fe_clock(struct dce_hwseq *hwss, 606 unsigned int inst, bool enable); 607 608 void dce_pipe_control_lock(struct dc *dc, 609 struct pipe_ctx *pipe, 610 bool lock); 611 612 void dce_set_blender_mode(struct dce_hwseq *hws, 613 unsigned int blnd_inst, enum blnd_mode mode); 614 615 void dce_clock_gating_power_up(struct dce_hwseq *hws, 616 bool enable); 617 618 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 619 struct clock_source *clk_src, 620 unsigned int tg_inst); 621 622 bool dce_use_lut(const struct dc_plane_state *plane_state); 623 #endif /*__DCE_HWSEQ_H__*/ 624