1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "hw_sequencer.h" 29 30 #define BL_REG_LIST()\ 31 SR(LVTMA_PWRSEQ_CNTL), \ 32 SR(LVTMA_PWRSEQ_STATE) 33 34 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 35 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 37 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 38 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 39 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 40 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 41 42 #define HWSEQ_DCEF_REG_LIST() \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 45 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 46 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 47 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 48 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 50 51 #define HWSEQ_BLND_REG_LIST() \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 54 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 55 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 56 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 57 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 58 SRII(BLND_CONTROL, BLND, 0), \ 59 SRII(BLND_CONTROL, BLND, 1), \ 60 SRII(BLND_CONTROL, BLND, 2), \ 61 SRII(BLND_CONTROL, BLND, 3), \ 62 SRII(BLND_CONTROL, BLND, 4), \ 63 SRII(BLND_CONTROL, BLND, 5) 64 65 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ 66 SRII(PIXEL_RATE_CNTL, blk, inst), \ 67 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) 68 69 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 70 SRII(PIXEL_RATE_CNTL, blk, 0), \ 71 SRII(PIXEL_RATE_CNTL, blk, 1), \ 72 SRII(PIXEL_RATE_CNTL, blk, 2), \ 73 SRII(PIXEL_RATE_CNTL, blk, 3), \ 74 SRII(PIXEL_RATE_CNTL, blk, 4), \ 75 SRII(PIXEL_RATE_CNTL, blk, 5) 76 77 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 80 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 81 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 82 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 83 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 84 85 #define HWSEQ_DCE11_REG_LIST_BASE() \ 86 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 87 SR(DCFEV_CLOCK_CONTROL), \ 88 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 89 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 90 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 91 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 92 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 93 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 94 SRII(BLND_CONTROL, BLND, 0),\ 95 SRII(BLND_CONTROL, BLND, 1),\ 96 SR(BLNDV_CONTROL),\ 97 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 98 BL_REG_LIST() 99 100 #define HWSEQ_DCE8_REG_LIST() \ 101 HWSEQ_DCEF_REG_LIST_DCE8(), \ 102 HWSEQ_BLND_REG_LIST(), \ 103 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 104 BL_REG_LIST() 105 106 #define HWSEQ_DCE10_REG_LIST() \ 107 HWSEQ_DCEF_REG_LIST(), \ 108 HWSEQ_BLND_REG_LIST(), \ 109 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 110 BL_REG_LIST() 111 112 #define HWSEQ_ST_REG_LIST() \ 113 HWSEQ_DCE11_REG_LIST_BASE(), \ 114 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 115 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 116 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 117 .BLND_CONTROL[2] = mmBLNDV_CONTROL 118 119 #define HWSEQ_CZ_REG_LIST() \ 120 HWSEQ_DCE11_REG_LIST_BASE(), \ 121 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 122 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 123 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 124 SRII(BLND_CONTROL, BLND, 2), \ 125 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 126 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 127 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 128 .BLND_CONTROL[3] = mmBLNDV_CONTROL 129 130 #define HWSEQ_DCE120_REG_LIST() \ 131 HWSEQ_DCE10_REG_LIST(), \ 132 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 133 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 134 SR(DCHUB_FB_LOCATION),\ 135 SR(DCHUB_AGP_BASE),\ 136 SR(DCHUB_AGP_BOT),\ 137 SR(DCHUB_AGP_TOP), \ 138 BL_REG_LIST() 139 140 #define HWSEQ_VG20_REG_LIST() \ 141 HWSEQ_DCE120_REG_LIST(),\ 142 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 143 144 #define HWSEQ_DCE112_REG_LIST() \ 145 HWSEQ_DCE10_REG_LIST(), \ 146 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 147 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 148 BL_REG_LIST() 149 150 #define HWSEQ_DCN_REG_LIST()\ 151 SR(REFCLK_CNTL), \ 152 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 153 SR(DIO_MEM_PWR_CTRL), \ 154 SR(DCCG_GATE_DISABLE_CNTL), \ 155 SR(DCCG_GATE_DISABLE_CNTL2), \ 156 SR(DCFCLK_CNTL),\ 157 SR(DCFCLK_CNTL), \ 158 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 159 160 161 #define MMHUB_DCN_REG_LIST()\ 162 /* todo: get these from GVM instead of reading registers ourselves */\ 163 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 164 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 165 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 166 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 167 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 168 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 169 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 170 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 171 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 172 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 173 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 174 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 175 176 177 #define HWSEQ_DCN1_REG_LIST()\ 178 HWSEQ_DCN_REG_LIST(), \ 179 MMHUB_DCN_REG_LIST(), \ 180 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 181 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 182 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 183 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 184 SR(DCHUBBUB_SDPIF_FB_BASE),\ 185 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 186 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 187 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 188 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 189 SR(DOMAIN0_PG_CONFIG), \ 190 SR(DOMAIN1_PG_CONFIG), \ 191 SR(DOMAIN2_PG_CONFIG), \ 192 SR(DOMAIN3_PG_CONFIG), \ 193 SR(DOMAIN4_PG_CONFIG), \ 194 SR(DOMAIN5_PG_CONFIG), \ 195 SR(DOMAIN6_PG_CONFIG), \ 196 SR(DOMAIN7_PG_CONFIG), \ 197 SR(DOMAIN0_PG_STATUS), \ 198 SR(DOMAIN1_PG_STATUS), \ 199 SR(DOMAIN2_PG_STATUS), \ 200 SR(DOMAIN3_PG_STATUS), \ 201 SR(DOMAIN4_PG_STATUS), \ 202 SR(DOMAIN5_PG_STATUS), \ 203 SR(DOMAIN6_PG_STATUS), \ 204 SR(DOMAIN7_PG_STATUS), \ 205 SR(D1VGA_CONTROL), \ 206 SR(D2VGA_CONTROL), \ 207 SR(D3VGA_CONTROL), \ 208 SR(D4VGA_CONTROL), \ 209 SR(VGA_TEST_CONTROL), \ 210 SR(DC_IP_REQUEST_CNTL), \ 211 BL_REG_LIST() 212 213 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 214 #define HWSEQ_DCN2_REG_LIST()\ 215 HWSEQ_DCN_REG_LIST(), \ 216 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 217 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 218 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 219 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 220 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 221 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ 222 SR(MICROSECOND_TIME_BASE_DIV), \ 223 SR(MILLISECOND_TIME_BASE_DIV), \ 224 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 225 SR(RBBMIF_TIMEOUT_DIS), \ 226 SR(RBBMIF_TIMEOUT_DIS_2), \ 227 SR(DCHUBBUB_CRC_CTRL), \ 228 SR(DPP_TOP0_DPP_CRC_CTRL), \ 229 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 230 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 231 SR(MPC_CRC_CTRL), \ 232 SR(MPC_CRC_RESULT_GB), \ 233 SR(MPC_CRC_RESULT_C), \ 234 SR(MPC_CRC_RESULT_AR), \ 235 SR(DOMAIN0_PG_CONFIG), \ 236 SR(DOMAIN1_PG_CONFIG), \ 237 SR(DOMAIN2_PG_CONFIG), \ 238 SR(DOMAIN3_PG_CONFIG), \ 239 SR(DOMAIN4_PG_CONFIG), \ 240 SR(DOMAIN5_PG_CONFIG), \ 241 SR(DOMAIN6_PG_CONFIG), \ 242 SR(DOMAIN7_PG_CONFIG), \ 243 SR(DOMAIN8_PG_CONFIG), \ 244 SR(DOMAIN9_PG_CONFIG), \ 245 /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ 246 /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ 247 SR(DOMAIN16_PG_CONFIG), \ 248 SR(DOMAIN17_PG_CONFIG), \ 249 SR(DOMAIN18_PG_CONFIG), \ 250 SR(DOMAIN19_PG_CONFIG), \ 251 SR(DOMAIN20_PG_CONFIG), \ 252 SR(DOMAIN21_PG_CONFIG), \ 253 SR(DOMAIN0_PG_STATUS), \ 254 SR(DOMAIN1_PG_STATUS), \ 255 SR(DOMAIN2_PG_STATUS), \ 256 SR(DOMAIN3_PG_STATUS), \ 257 SR(DOMAIN4_PG_STATUS), \ 258 SR(DOMAIN5_PG_STATUS), \ 259 SR(DOMAIN6_PG_STATUS), \ 260 SR(DOMAIN7_PG_STATUS), \ 261 SR(DOMAIN8_PG_STATUS), \ 262 SR(DOMAIN9_PG_STATUS), \ 263 SR(DOMAIN10_PG_STATUS), \ 264 SR(DOMAIN11_PG_STATUS), \ 265 SR(DOMAIN16_PG_STATUS), \ 266 SR(DOMAIN17_PG_STATUS), \ 267 SR(DOMAIN18_PG_STATUS), \ 268 SR(DOMAIN19_PG_STATUS), \ 269 SR(DOMAIN20_PG_STATUS), \ 270 SR(DOMAIN21_PG_STATUS), \ 271 SR(D1VGA_CONTROL), \ 272 SR(D2VGA_CONTROL), \ 273 SR(D3VGA_CONTROL), \ 274 SR(D4VGA_CONTROL), \ 275 SR(D5VGA_CONTROL), \ 276 SR(D6VGA_CONTROL), \ 277 SR(DC_IP_REQUEST_CNTL), \ 278 BL_REG_LIST() 279 #endif 280 281 struct dce_hwseq_registers { 282 283 /* Backlight registers */ 284 uint32_t LVTMA_PWRSEQ_CNTL; 285 uint32_t LVTMA_PWRSEQ_STATE; 286 287 uint32_t DCFE_CLOCK_CONTROL[6]; 288 uint32_t DCFEV_CLOCK_CONTROL; 289 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 290 uint32_t BLND_V_UPDATE_LOCK[6]; 291 uint32_t BLND_CONTROL[6]; 292 uint32_t BLNDV_CONTROL; 293 uint32_t CRTC_H_BLANK_START_END[6]; 294 uint32_t PIXEL_RATE_CNTL[6]; 295 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 296 /*DCHUB*/ 297 uint32_t DCHUB_FB_LOCATION; 298 uint32_t DCHUB_AGP_BASE; 299 uint32_t DCHUB_AGP_BOT; 300 uint32_t DCHUB_AGP_TOP; 301 302 uint32_t REFCLK_CNTL; 303 304 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 305 uint32_t DCHUBBUB_SDPIF_FB_BASE; 306 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 307 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 308 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 309 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 310 uint32_t DC_IP_REQUEST_CNTL; 311 uint32_t DOMAIN0_PG_CONFIG; 312 uint32_t DOMAIN1_PG_CONFIG; 313 uint32_t DOMAIN2_PG_CONFIG; 314 uint32_t DOMAIN3_PG_CONFIG; 315 uint32_t DOMAIN4_PG_CONFIG; 316 uint32_t DOMAIN5_PG_CONFIG; 317 uint32_t DOMAIN6_PG_CONFIG; 318 uint32_t DOMAIN7_PG_CONFIG; 319 uint32_t DOMAIN8_PG_CONFIG; 320 uint32_t DOMAIN9_PG_CONFIG; 321 uint32_t DOMAIN10_PG_CONFIG; 322 uint32_t DOMAIN11_PG_CONFIG; 323 uint32_t DOMAIN16_PG_CONFIG; 324 uint32_t DOMAIN17_PG_CONFIG; 325 uint32_t DOMAIN18_PG_CONFIG; 326 uint32_t DOMAIN19_PG_CONFIG; 327 uint32_t DOMAIN20_PG_CONFIG; 328 uint32_t DOMAIN21_PG_CONFIG; 329 uint32_t DOMAIN0_PG_STATUS; 330 uint32_t DOMAIN1_PG_STATUS; 331 uint32_t DOMAIN2_PG_STATUS; 332 uint32_t DOMAIN3_PG_STATUS; 333 uint32_t DOMAIN4_PG_STATUS; 334 uint32_t DOMAIN5_PG_STATUS; 335 uint32_t DOMAIN6_PG_STATUS; 336 uint32_t DOMAIN7_PG_STATUS; 337 uint32_t DOMAIN8_PG_STATUS; 338 uint32_t DOMAIN9_PG_STATUS; 339 uint32_t DOMAIN10_PG_STATUS; 340 uint32_t DOMAIN11_PG_STATUS; 341 uint32_t DOMAIN16_PG_STATUS; 342 uint32_t DOMAIN17_PG_STATUS; 343 uint32_t DOMAIN18_PG_STATUS; 344 uint32_t DOMAIN19_PG_STATUS; 345 uint32_t DOMAIN20_PG_STATUS; 346 uint32_t DOMAIN21_PG_STATUS; 347 uint32_t DIO_MEM_PWR_CTRL; 348 uint32_t DCCG_GATE_DISABLE_CNTL; 349 uint32_t DCCG_GATE_DISABLE_CNTL2; 350 uint32_t DCFCLK_CNTL; 351 uint32_t MICROSECOND_TIME_BASE_DIV; 352 uint32_t MILLISECOND_TIME_BASE_DIV; 353 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 354 uint32_t RBBMIF_TIMEOUT_DIS; 355 uint32_t RBBMIF_TIMEOUT_DIS_2; 356 uint32_t DCHUBBUB_CRC_CTRL; 357 uint32_t DPP_TOP0_DPP_CRC_CTRL; 358 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 359 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 360 uint32_t MPC_CRC_CTRL; 361 uint32_t MPC_CRC_RESULT_GB; 362 uint32_t MPC_CRC_RESULT_C; 363 uint32_t MPC_CRC_RESULT_AR; 364 uint32_t D1VGA_CONTROL; 365 uint32_t D2VGA_CONTROL; 366 uint32_t D3VGA_CONTROL; 367 uint32_t D4VGA_CONTROL; 368 uint32_t D5VGA_CONTROL; 369 uint32_t D6VGA_CONTROL; 370 uint32_t VGA_TEST_CONTROL; 371 /* MMHUB registers. read only. temporary hack */ 372 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 373 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 374 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 375 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 376 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 377 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 378 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 379 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 380 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 381 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 382 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 383 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 384 uint32_t MC_VM_XGMI_LFB_CNTL; 385 uint32_t AZALIA_AUDIO_DTO; 386 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 387 }; 388 /* set field name */ 389 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 390 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 391 392 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 393 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 394 395 396 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 397 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 398 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 399 400 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 401 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 402 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 403 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 404 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 405 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 406 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 407 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 408 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 409 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 410 411 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 412 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 413 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 414 415 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 416 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 417 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 418 419 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 420 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 421 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 422 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 423 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 424 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 425 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 426 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 427 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 428 429 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 430 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 431 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 432 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ 433 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 434 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 435 436 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 437 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 438 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 439 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 440 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ 441 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ 442 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 443 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 444 445 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 446 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 447 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 448 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 449 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 450 451 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 452 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 453 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 454 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 455 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 456 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ 457 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 458 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 459 460 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 461 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 462 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 463 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 464 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 465 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ 466 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 467 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 468 469 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 470 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 471 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 472 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 473 474 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 475 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 476 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 477 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 478 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 479 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 480 481 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 482 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 483 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 484 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 485 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 486 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 487 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 488 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 489 /* todo: get these from GVM instead of reading registers ourselves */\ 490 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 491 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 492 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 493 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 494 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 495 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 496 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 497 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 498 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 499 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 500 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 501 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 502 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 503 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 504 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 505 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 506 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 507 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 508 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 509 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 510 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 511 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 512 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 513 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 514 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 515 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 516 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 517 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 518 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 519 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 520 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 521 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 522 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 523 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 524 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 525 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 526 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 527 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 528 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 529 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ 530 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 531 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \ 532 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \ 533 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 534 535 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 536 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 537 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 538 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 539 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 540 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 541 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 542 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 543 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 544 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 545 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 546 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 547 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 548 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 549 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 550 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 551 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 552 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 553 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 554 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 555 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 556 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 557 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 558 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 559 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 560 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 561 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 562 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 563 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 564 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 565 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 566 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 567 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 568 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 569 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 570 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 571 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 572 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 573 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 574 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 575 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 576 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 577 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 578 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 579 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 580 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 581 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 582 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 583 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 584 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 585 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 586 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 587 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 588 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 589 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 590 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 591 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 592 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 593 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 594 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 595 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 596 #endif 597 598 #define HWSEQ_REG_FIELD_LIST(type) \ 599 type DCFE_CLOCK_ENABLE; \ 600 type DCFEV_CLOCK_ENABLE; \ 601 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 602 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 603 type BLND_SCL_V_UPDATE_LOCK; \ 604 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 605 type BLND_BLND_V_UPDATE_LOCK; \ 606 type BLND_V_UPDATE_LOCK_MODE; \ 607 type BLND_FEEDTHROUGH_EN; \ 608 type BLND_ALPHA_MODE; \ 609 type BLND_MODE; \ 610 type BLND_MULTIPLIED_MODE; \ 611 type DP_DTO0_ENABLE; \ 612 type PIXEL_RATE_SOURCE; \ 613 type PHYPLL_PIXEL_RATE_SOURCE; \ 614 type PIXEL_RATE_PLL_SOURCE; \ 615 /* todo: get these from GVM instead of reading registers ourselves */\ 616 type PAGE_DIRECTORY_ENTRY_HI32;\ 617 type PAGE_DIRECTORY_ENTRY_LO32;\ 618 type LOGICAL_PAGE_NUMBER_HI4;\ 619 type LOGICAL_PAGE_NUMBER_LO32;\ 620 type PHYSICAL_PAGE_ADDR_HI4;\ 621 type PHYSICAL_PAGE_ADDR_LO32;\ 622 type PHYSICAL_PAGE_NUMBER_MSB;\ 623 type PHYSICAL_PAGE_NUMBER_LSB;\ 624 type LOGICAL_ADDR; \ 625 type PF_LFB_REGION;\ 626 type PF_MAX_REGION;\ 627 type ENABLE_L1_TLB;\ 628 type SYSTEM_ACCESS_MODE;\ 629 type LVTMA_BLON;\ 630 type LVTMA_PWRSEQ_TARGET_STATE_R;\ 631 type LVTMA_DIGON;\ 632 type LVTMA_DIGON_OVRD; 633 634 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 635 type HUBP_VTG_SEL; \ 636 type HUBP_CLOCK_ENABLE; \ 637 type DPP_CLOCK_ENABLE; \ 638 type SDPIF_FB_BASE;\ 639 type SDPIF_FB_OFFSET;\ 640 type SDPIF_AGP_BASE;\ 641 type SDPIF_AGP_BOT;\ 642 type SDPIF_AGP_TOP;\ 643 type FB_TOP;\ 644 type FB_BASE;\ 645 type FB_OFFSET;\ 646 type AGP_BASE;\ 647 type AGP_BOT;\ 648 type AGP_TOP;\ 649 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 650 type OPP_PIPE_CLOCK_EN;\ 651 type IP_REQUEST_EN; \ 652 type DOMAIN0_POWER_FORCEON; \ 653 type DOMAIN0_POWER_GATE; \ 654 type DOMAIN1_POWER_FORCEON; \ 655 type DOMAIN1_POWER_GATE; \ 656 type DOMAIN2_POWER_FORCEON; \ 657 type DOMAIN2_POWER_GATE; \ 658 type DOMAIN3_POWER_FORCEON; \ 659 type DOMAIN3_POWER_GATE; \ 660 type DOMAIN4_POWER_FORCEON; \ 661 type DOMAIN4_POWER_GATE; \ 662 type DOMAIN5_POWER_FORCEON; \ 663 type DOMAIN5_POWER_GATE; \ 664 type DOMAIN6_POWER_FORCEON; \ 665 type DOMAIN6_POWER_GATE; \ 666 type DOMAIN7_POWER_FORCEON; \ 667 type DOMAIN7_POWER_GATE; \ 668 type DOMAIN8_POWER_FORCEON; \ 669 type DOMAIN8_POWER_GATE; \ 670 type DOMAIN9_POWER_FORCEON; \ 671 type DOMAIN9_POWER_GATE; \ 672 type DOMAIN10_POWER_FORCEON; \ 673 type DOMAIN10_POWER_GATE; \ 674 type DOMAIN11_POWER_FORCEON; \ 675 type DOMAIN11_POWER_GATE; \ 676 type DOMAIN16_POWER_FORCEON; \ 677 type DOMAIN16_POWER_GATE; \ 678 type DOMAIN17_POWER_FORCEON; \ 679 type DOMAIN17_POWER_GATE; \ 680 type DOMAIN18_POWER_FORCEON; \ 681 type DOMAIN18_POWER_GATE; \ 682 type DOMAIN19_POWER_FORCEON; \ 683 type DOMAIN19_POWER_GATE; \ 684 type DOMAIN20_POWER_FORCEON; \ 685 type DOMAIN20_POWER_GATE; \ 686 type DOMAIN21_POWER_FORCEON; \ 687 type DOMAIN21_POWER_GATE; \ 688 type DOMAIN0_PGFSM_PWR_STATUS; \ 689 type DOMAIN1_PGFSM_PWR_STATUS; \ 690 type DOMAIN2_PGFSM_PWR_STATUS; \ 691 type DOMAIN3_PGFSM_PWR_STATUS; \ 692 type DOMAIN4_PGFSM_PWR_STATUS; \ 693 type DOMAIN5_PGFSM_PWR_STATUS; \ 694 type DOMAIN6_PGFSM_PWR_STATUS; \ 695 type DOMAIN7_PGFSM_PWR_STATUS; \ 696 type DOMAIN8_PGFSM_PWR_STATUS; \ 697 type DOMAIN9_PGFSM_PWR_STATUS; \ 698 type DOMAIN10_PGFSM_PWR_STATUS; \ 699 type DOMAIN11_PGFSM_PWR_STATUS; \ 700 type DOMAIN16_PGFSM_PWR_STATUS; \ 701 type DOMAIN17_PGFSM_PWR_STATUS; \ 702 type DOMAIN18_PGFSM_PWR_STATUS; \ 703 type DOMAIN19_PGFSM_PWR_STATUS; \ 704 type DOMAIN20_PGFSM_PWR_STATUS; \ 705 type DOMAIN21_PGFSM_PWR_STATUS; \ 706 type DCFCLK_GATE_DIS; \ 707 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 708 type VGA_TEST_ENABLE; \ 709 type VGA_TEST_RENDER_START; \ 710 type D1VGA_MODE_ENABLE; \ 711 type D2VGA_MODE_ENABLE; \ 712 type D3VGA_MODE_ENABLE; \ 713 type D4VGA_MODE_ENABLE; \ 714 type AZALIA_AUDIO_DTO_MODULE;\ 715 type HPO_HDMISTREAMCLK_GATE_DIS; 716 717 struct dce_hwseq_shift { 718 HWSEQ_REG_FIELD_LIST(uint8_t) 719 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 720 }; 721 722 struct dce_hwseq_mask { 723 HWSEQ_REG_FIELD_LIST(uint32_t) 724 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 725 }; 726 727 728 enum blnd_mode { 729 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 730 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 731 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 732 }; 733 734 void dce_enable_fe_clock(struct dce_hwseq *hwss, 735 unsigned int inst, bool enable); 736 737 void dce_pipe_control_lock(struct dc *dc, 738 struct pipe_ctx *pipe, 739 bool lock); 740 741 void dce_set_blender_mode(struct dce_hwseq *hws, 742 unsigned int blnd_inst, enum blnd_mode mode); 743 744 void dce_clock_gating_power_up(struct dce_hwseq *hws, 745 bool enable); 746 747 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 748 struct clock_source *clk_src, 749 unsigned int tg_inst); 750 751 bool dce_use_lut(enum surface_pixel_format format); 752 #endif /*__DCE_HWSEQ_H__*/ 753