1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "hw_sequencer.h" 29 30 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 37 38 #define HWSEQ_DCEF_REG_LIST() \ 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 46 47 #define HWSEQ_BLND_REG_LIST() \ 48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 54 SRII(BLND_CONTROL, BLND, 0), \ 55 SRII(BLND_CONTROL, BLND, 1), \ 56 SRII(BLND_CONTROL, BLND, 2), \ 57 SRII(BLND_CONTROL, BLND, 3), \ 58 SRII(BLND_CONTROL, BLND, 4), \ 59 SRII(BLND_CONTROL, BLND, 5) 60 61 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 62 SRII(PIXEL_RATE_CNTL, blk, 0), \ 63 SRII(PIXEL_RATE_CNTL, blk, 1), \ 64 SRII(PIXEL_RATE_CNTL, blk, 2), \ 65 SRII(PIXEL_RATE_CNTL, blk, 3), \ 66 SRII(PIXEL_RATE_CNTL, blk, 4), \ 67 SRII(PIXEL_RATE_CNTL, blk, 5) 68 69 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 70 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 71 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 72 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 73 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 76 77 #define HWSEQ_DCE11_REG_LIST_BASE() \ 78 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 79 SR(DCFEV_CLOCK_CONTROL), \ 80 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 81 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 82 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 83 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 84 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 85 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 86 SRII(BLND_CONTROL, BLND, 0),\ 87 SRII(BLND_CONTROL, BLND, 1),\ 88 SR(BLNDV_CONTROL),\ 89 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 90 91 #define HWSEQ_DCE8_REG_LIST() \ 92 HWSEQ_DCEF_REG_LIST_DCE8(), \ 93 HWSEQ_BLND_REG_LIST(), \ 94 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 95 96 #define HWSEQ_DCE10_REG_LIST() \ 97 HWSEQ_DCEF_REG_LIST(), \ 98 HWSEQ_BLND_REG_LIST(), \ 99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 100 101 #define HWSEQ_ST_REG_LIST() \ 102 HWSEQ_DCE11_REG_LIST_BASE(), \ 103 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 104 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 105 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 106 .BLND_CONTROL[2] = mmBLNDV_CONTROL, 107 108 #define HWSEQ_CZ_REG_LIST() \ 109 HWSEQ_DCE11_REG_LIST_BASE(), \ 110 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 111 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 112 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 113 SRII(BLND_CONTROL, BLND, 2), \ 114 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 115 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 116 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 117 .BLND_CONTROL[3] = mmBLNDV_CONTROL 118 119 #define HWSEQ_DCE112_REG_LIST() \ 120 HWSEQ_DCE10_REG_LIST(), \ 121 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 122 HWSEQ_PHYPLL_REG_LIST(CRTC) 123 124 struct dce_hwseq_registers { 125 uint32_t DCFE_CLOCK_CONTROL[6]; 126 uint32_t DCFEV_CLOCK_CONTROL; 127 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 128 uint32_t BLND_V_UPDATE_LOCK[6]; 129 uint32_t BLND_CONTROL[6]; 130 uint32_t BLNDV_CONTROL; 131 132 uint32_t CRTC_H_BLANK_START_END[6]; 133 uint32_t PIXEL_RATE_CNTL[6]; 134 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 135 }; 136 /* set field name */ 137 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 138 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 139 140 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 141 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 142 143 144 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 145 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 146 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 147 148 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 149 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 150 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 151 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 152 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 153 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 154 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 155 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 156 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 157 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 158 159 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 160 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 161 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 162 163 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 164 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 165 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 166 167 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 168 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 169 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 170 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 171 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 172 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 173 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 174 175 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 176 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 177 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 178 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 179 180 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 181 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 182 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 183 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 184 185 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 186 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 187 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 188 189 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 190 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 191 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 192 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 193 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 194 195 #define HWSEQ_REG_FIED_LIST(type) \ 196 type DCFE_CLOCK_ENABLE; \ 197 type DCFEV_CLOCK_ENABLE; \ 198 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 199 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 200 type BLND_SCL_V_UPDATE_LOCK; \ 201 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 202 type BLND_BLND_V_UPDATE_LOCK; \ 203 type BLND_V_UPDATE_LOCK_MODE; \ 204 type BLND_FEEDTHROUGH_EN; \ 205 type BLND_ALPHA_MODE; \ 206 type BLND_MODE; \ 207 type BLND_MULTIPLIED_MODE; \ 208 type DP_DTO0_ENABLE; \ 209 type PIXEL_RATE_SOURCE; \ 210 type PHYPLL_PIXEL_RATE_SOURCE; \ 211 type PIXEL_RATE_PLL_SOURCE; \ 212 213 struct dce_hwseq_shift { 214 HWSEQ_REG_FIED_LIST(uint8_t) 215 }; 216 217 struct dce_hwseq_mask { 218 HWSEQ_REG_FIED_LIST(uint32_t) 219 }; 220 221 222 enum blnd_mode { 223 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 224 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 225 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 226 }; 227 228 void dce_enable_fe_clock(struct dce_hwseq *hwss, 229 unsigned int inst, bool enable); 230 231 void dce_pipe_control_lock(struct core_dc *dc, 232 struct pipe_ctx *pipe, 233 bool lock); 234 235 void dce_set_blender_mode(struct dce_hwseq *hws, 236 unsigned int blnd_inst, enum blnd_mode mode); 237 238 void dce_clock_gating_power_up(struct dce_hwseq *hws, 239 bool enable); 240 241 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 242 struct clock_source *clk_src, 243 unsigned int tg_inst); 244 #endif /*__DCE_HWSEQ_H__*/ 245