1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "hw_sequencer.h" 29 30 #define BL_REG_LIST()\ 31 SR(LVTMA_PWRSEQ_CNTL), \ 32 SR(LVTMA_PWRSEQ_STATE) 33 34 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 35 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 37 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 38 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 39 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 40 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 41 42 #define HWSEQ_DCEF_REG_LIST() \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 45 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 46 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 47 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 48 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 50 51 #define HWSEQ_BLND_REG_LIST() \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 54 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 55 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 56 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 57 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 58 SRII(BLND_CONTROL, BLND, 0), \ 59 SRII(BLND_CONTROL, BLND, 1), \ 60 SRII(BLND_CONTROL, BLND, 2), \ 61 SRII(BLND_CONTROL, BLND, 3), \ 62 SRII(BLND_CONTROL, BLND, 4), \ 63 SRII(BLND_CONTROL, BLND, 5) 64 65 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ 66 SRII(PIXEL_RATE_CNTL, blk, inst), \ 67 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) 68 69 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 70 SRII(PIXEL_RATE_CNTL, blk, 0), \ 71 SRII(PIXEL_RATE_CNTL, blk, 1), \ 72 SRII(PIXEL_RATE_CNTL, blk, 2), \ 73 SRII(PIXEL_RATE_CNTL, blk, 3), \ 74 SRII(PIXEL_RATE_CNTL, blk, 4), \ 75 SRII(PIXEL_RATE_CNTL, blk, 5) 76 77 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 80 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 81 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 82 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 83 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 84 85 #define HWSEQ_DCE11_REG_LIST_BASE() \ 86 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 87 SR(DCFEV_CLOCK_CONTROL), \ 88 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 89 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 90 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 91 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 92 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 93 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 94 SRII(BLND_CONTROL, BLND, 0),\ 95 SRII(BLND_CONTROL, BLND, 1),\ 96 SR(BLNDV_CONTROL),\ 97 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 98 BL_REG_LIST() 99 100 #define HWSEQ_DCE8_REG_LIST() \ 101 HWSEQ_DCEF_REG_LIST_DCE8(), \ 102 HWSEQ_BLND_REG_LIST(), \ 103 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 104 BL_REG_LIST() 105 106 #define HWSEQ_DCE10_REG_LIST() \ 107 HWSEQ_DCEF_REG_LIST(), \ 108 HWSEQ_BLND_REG_LIST(), \ 109 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 110 BL_REG_LIST() 111 112 #define HWSEQ_ST_REG_LIST() \ 113 HWSEQ_DCE11_REG_LIST_BASE(), \ 114 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 115 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 116 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 117 .BLND_CONTROL[2] = mmBLNDV_CONTROL 118 119 #define HWSEQ_CZ_REG_LIST() \ 120 HWSEQ_DCE11_REG_LIST_BASE(), \ 121 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 122 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 123 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 124 SRII(BLND_CONTROL, BLND, 2), \ 125 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 126 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 127 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 128 .BLND_CONTROL[3] = mmBLNDV_CONTROL 129 130 #define HWSEQ_DCE120_REG_LIST() \ 131 HWSEQ_DCE10_REG_LIST(), \ 132 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 133 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 134 SR(DCHUB_FB_LOCATION),\ 135 SR(DCHUB_AGP_BASE),\ 136 SR(DCHUB_AGP_BOT),\ 137 SR(DCHUB_AGP_TOP), \ 138 BL_REG_LIST() 139 140 #define HWSEQ_VG20_REG_LIST() \ 141 HWSEQ_DCE120_REG_LIST(),\ 142 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 143 144 #define HWSEQ_DCE112_REG_LIST() \ 145 HWSEQ_DCE10_REG_LIST(), \ 146 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 147 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 148 BL_REG_LIST() 149 150 #define HWSEQ_DCN_REG_LIST()\ 151 SR(REFCLK_CNTL), \ 152 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 153 SR(DIO_MEM_PWR_CTRL), \ 154 SR(DCCG_GATE_DISABLE_CNTL), \ 155 SR(DCCG_GATE_DISABLE_CNTL2), \ 156 SR(DCFCLK_CNTL),\ 157 SR(DCFCLK_CNTL), \ 158 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 159 160 161 #define MMHUB_DCN_REG_LIST()\ 162 /* todo: get these from GVM instead of reading registers ourselves */\ 163 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 164 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 165 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 166 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 167 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 168 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 169 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 170 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 171 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 172 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 173 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 174 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 175 176 177 #define HWSEQ_DCN1_REG_LIST()\ 178 HWSEQ_DCN_REG_LIST(), \ 179 MMHUB_DCN_REG_LIST(), \ 180 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 181 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 182 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 183 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 184 SR(DCHUBBUB_SDPIF_FB_BASE),\ 185 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 186 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 187 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 188 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 189 SR(DOMAIN0_PG_CONFIG), \ 190 SR(DOMAIN1_PG_CONFIG), \ 191 SR(DOMAIN2_PG_CONFIG), \ 192 SR(DOMAIN3_PG_CONFIG), \ 193 SR(DOMAIN4_PG_CONFIG), \ 194 SR(DOMAIN5_PG_CONFIG), \ 195 SR(DOMAIN6_PG_CONFIG), \ 196 SR(DOMAIN7_PG_CONFIG), \ 197 SR(DOMAIN0_PG_STATUS), \ 198 SR(DOMAIN1_PG_STATUS), \ 199 SR(DOMAIN2_PG_STATUS), \ 200 SR(DOMAIN3_PG_STATUS), \ 201 SR(DOMAIN4_PG_STATUS), \ 202 SR(DOMAIN5_PG_STATUS), \ 203 SR(DOMAIN6_PG_STATUS), \ 204 SR(DOMAIN7_PG_STATUS), \ 205 SR(D1VGA_CONTROL), \ 206 SR(D2VGA_CONTROL), \ 207 SR(D3VGA_CONTROL), \ 208 SR(D4VGA_CONTROL), \ 209 SR(VGA_TEST_CONTROL), \ 210 SR(DC_IP_REQUEST_CNTL), \ 211 BL_REG_LIST() 212 213 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 214 #define HWSEQ_DCN2_REG_LIST()\ 215 HWSEQ_DCN_REG_LIST(), \ 216 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 217 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 218 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 219 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 220 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 221 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ 222 SR(MICROSECOND_TIME_BASE_DIV), \ 223 SR(MILLISECOND_TIME_BASE_DIV), \ 224 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 225 SR(RBBMIF_TIMEOUT_DIS), \ 226 SR(RBBMIF_TIMEOUT_DIS_2), \ 227 SR(DCHUBBUB_CRC_CTRL), \ 228 SR(DPP_TOP0_DPP_CRC_CTRL), \ 229 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 230 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 231 SR(MPC_CRC_CTRL), \ 232 SR(MPC_CRC_RESULT_GB), \ 233 SR(MPC_CRC_RESULT_C), \ 234 SR(MPC_CRC_RESULT_AR), \ 235 SR(DOMAIN0_PG_CONFIG), \ 236 SR(DOMAIN1_PG_CONFIG), \ 237 SR(DOMAIN2_PG_CONFIG), \ 238 SR(DOMAIN3_PG_CONFIG), \ 239 SR(DOMAIN4_PG_CONFIG), \ 240 SR(DOMAIN5_PG_CONFIG), \ 241 SR(DOMAIN6_PG_CONFIG), \ 242 SR(DOMAIN7_PG_CONFIG), \ 243 SR(DOMAIN8_PG_CONFIG), \ 244 SR(DOMAIN9_PG_CONFIG), \ 245 /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ 246 /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ 247 SR(DOMAIN16_PG_CONFIG), \ 248 SR(DOMAIN17_PG_CONFIG), \ 249 SR(DOMAIN18_PG_CONFIG), \ 250 SR(DOMAIN19_PG_CONFIG), \ 251 SR(DOMAIN20_PG_CONFIG), \ 252 SR(DOMAIN21_PG_CONFIG), \ 253 SR(DOMAIN0_PG_STATUS), \ 254 SR(DOMAIN1_PG_STATUS), \ 255 SR(DOMAIN2_PG_STATUS), \ 256 SR(DOMAIN3_PG_STATUS), \ 257 SR(DOMAIN4_PG_STATUS), \ 258 SR(DOMAIN5_PG_STATUS), \ 259 SR(DOMAIN6_PG_STATUS), \ 260 SR(DOMAIN7_PG_STATUS), \ 261 SR(DOMAIN8_PG_STATUS), \ 262 SR(DOMAIN9_PG_STATUS), \ 263 SR(DOMAIN10_PG_STATUS), \ 264 SR(DOMAIN11_PG_STATUS), \ 265 SR(DOMAIN16_PG_STATUS), \ 266 SR(DOMAIN17_PG_STATUS), \ 267 SR(DOMAIN18_PG_STATUS), \ 268 SR(DOMAIN19_PG_STATUS), \ 269 SR(DOMAIN20_PG_STATUS), \ 270 SR(DOMAIN21_PG_STATUS), \ 271 SR(D1VGA_CONTROL), \ 272 SR(D2VGA_CONTROL), \ 273 SR(D3VGA_CONTROL), \ 274 SR(D4VGA_CONTROL), \ 275 SR(D5VGA_CONTROL), \ 276 SR(D6VGA_CONTROL), \ 277 SR(DC_IP_REQUEST_CNTL), \ 278 BL_REG_LIST() 279 #endif 280 281 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 282 #define HWSEQ_DCN21_REG_LIST()\ 283 HWSEQ_DCN_REG_LIST(), \ 284 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 285 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 286 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 287 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 288 MMHUB_DCN_REG_LIST(), \ 289 SR(MICROSECOND_TIME_BASE_DIV), \ 290 SR(MILLISECOND_TIME_BASE_DIV), \ 291 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 292 SR(RBBMIF_TIMEOUT_DIS), \ 293 SR(RBBMIF_TIMEOUT_DIS_2), \ 294 SR(DCHUBBUB_CRC_CTRL), \ 295 SR(DPP_TOP0_DPP_CRC_CTRL), \ 296 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 297 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 298 SR(MPC_CRC_CTRL), \ 299 SR(MPC_CRC_RESULT_GB), \ 300 SR(MPC_CRC_RESULT_C), \ 301 SR(MPC_CRC_RESULT_AR), \ 302 SR(DOMAIN0_PG_CONFIG), \ 303 SR(DOMAIN1_PG_CONFIG), \ 304 SR(DOMAIN2_PG_CONFIG), \ 305 SR(DOMAIN3_PG_CONFIG), \ 306 SR(DOMAIN4_PG_CONFIG), \ 307 SR(DOMAIN5_PG_CONFIG), \ 308 SR(DOMAIN6_PG_CONFIG), \ 309 SR(DOMAIN7_PG_CONFIG), \ 310 SR(DOMAIN16_PG_CONFIG), \ 311 SR(DOMAIN17_PG_CONFIG), \ 312 SR(DOMAIN18_PG_CONFIG), \ 313 SR(DOMAIN0_PG_STATUS), \ 314 SR(DOMAIN1_PG_STATUS), \ 315 SR(DOMAIN2_PG_STATUS), \ 316 SR(DOMAIN3_PG_STATUS), \ 317 SR(DOMAIN4_PG_STATUS), \ 318 SR(DOMAIN5_PG_STATUS), \ 319 SR(DOMAIN6_PG_STATUS), \ 320 SR(DOMAIN7_PG_STATUS), \ 321 SR(DOMAIN16_PG_STATUS), \ 322 SR(DOMAIN17_PG_STATUS), \ 323 SR(DOMAIN18_PG_STATUS), \ 324 SR(D1VGA_CONTROL), \ 325 SR(D2VGA_CONTROL), \ 326 SR(D3VGA_CONTROL), \ 327 SR(D4VGA_CONTROL), \ 328 SR(D5VGA_CONTROL), \ 329 SR(D6VGA_CONTROL), \ 330 SR(DC_IP_REQUEST_CNTL), \ 331 BL_REG_LIST() 332 #endif 333 334 struct dce_hwseq_registers { 335 336 /* Backlight registers */ 337 uint32_t LVTMA_PWRSEQ_CNTL; 338 uint32_t LVTMA_PWRSEQ_STATE; 339 340 uint32_t DCFE_CLOCK_CONTROL[6]; 341 uint32_t DCFEV_CLOCK_CONTROL; 342 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 343 uint32_t BLND_V_UPDATE_LOCK[6]; 344 uint32_t BLND_CONTROL[6]; 345 uint32_t BLNDV_CONTROL; 346 uint32_t CRTC_H_BLANK_START_END[6]; 347 uint32_t PIXEL_RATE_CNTL[6]; 348 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 349 /*DCHUB*/ 350 uint32_t DCHUB_FB_LOCATION; 351 uint32_t DCHUB_AGP_BASE; 352 uint32_t DCHUB_AGP_BOT; 353 uint32_t DCHUB_AGP_TOP; 354 355 uint32_t REFCLK_CNTL; 356 357 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 358 uint32_t DCHUBBUB_SDPIF_FB_BASE; 359 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 360 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 361 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 362 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 363 uint32_t DC_IP_REQUEST_CNTL; 364 uint32_t DOMAIN0_PG_CONFIG; 365 uint32_t DOMAIN1_PG_CONFIG; 366 uint32_t DOMAIN2_PG_CONFIG; 367 uint32_t DOMAIN3_PG_CONFIG; 368 uint32_t DOMAIN4_PG_CONFIG; 369 uint32_t DOMAIN5_PG_CONFIG; 370 uint32_t DOMAIN6_PG_CONFIG; 371 uint32_t DOMAIN7_PG_CONFIG; 372 uint32_t DOMAIN8_PG_CONFIG; 373 uint32_t DOMAIN9_PG_CONFIG; 374 uint32_t DOMAIN10_PG_CONFIG; 375 uint32_t DOMAIN11_PG_CONFIG; 376 uint32_t DOMAIN16_PG_CONFIG; 377 uint32_t DOMAIN17_PG_CONFIG; 378 uint32_t DOMAIN18_PG_CONFIG; 379 uint32_t DOMAIN19_PG_CONFIG; 380 uint32_t DOMAIN20_PG_CONFIG; 381 uint32_t DOMAIN21_PG_CONFIG; 382 uint32_t DOMAIN0_PG_STATUS; 383 uint32_t DOMAIN1_PG_STATUS; 384 uint32_t DOMAIN2_PG_STATUS; 385 uint32_t DOMAIN3_PG_STATUS; 386 uint32_t DOMAIN4_PG_STATUS; 387 uint32_t DOMAIN5_PG_STATUS; 388 uint32_t DOMAIN6_PG_STATUS; 389 uint32_t DOMAIN7_PG_STATUS; 390 uint32_t DOMAIN8_PG_STATUS; 391 uint32_t DOMAIN9_PG_STATUS; 392 uint32_t DOMAIN10_PG_STATUS; 393 uint32_t DOMAIN11_PG_STATUS; 394 uint32_t DOMAIN16_PG_STATUS; 395 uint32_t DOMAIN17_PG_STATUS; 396 uint32_t DOMAIN18_PG_STATUS; 397 uint32_t DOMAIN19_PG_STATUS; 398 uint32_t DOMAIN20_PG_STATUS; 399 uint32_t DOMAIN21_PG_STATUS; 400 uint32_t DIO_MEM_PWR_CTRL; 401 uint32_t DCCG_GATE_DISABLE_CNTL; 402 uint32_t DCCG_GATE_DISABLE_CNTL2; 403 uint32_t DCFCLK_CNTL; 404 uint32_t MICROSECOND_TIME_BASE_DIV; 405 uint32_t MILLISECOND_TIME_BASE_DIV; 406 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 407 uint32_t RBBMIF_TIMEOUT_DIS; 408 uint32_t RBBMIF_TIMEOUT_DIS_2; 409 uint32_t DCHUBBUB_CRC_CTRL; 410 uint32_t DPP_TOP0_DPP_CRC_CTRL; 411 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 412 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 413 uint32_t MPC_CRC_CTRL; 414 uint32_t MPC_CRC_RESULT_GB; 415 uint32_t MPC_CRC_RESULT_C; 416 uint32_t MPC_CRC_RESULT_AR; 417 uint32_t D1VGA_CONTROL; 418 uint32_t D2VGA_CONTROL; 419 uint32_t D3VGA_CONTROL; 420 uint32_t D4VGA_CONTROL; 421 uint32_t D5VGA_CONTROL; 422 uint32_t D6VGA_CONTROL; 423 uint32_t VGA_TEST_CONTROL; 424 /* MMHUB registers. read only. temporary hack */ 425 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 426 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 427 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 428 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 429 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 430 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 431 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 432 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 433 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 434 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 435 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 436 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 437 uint32_t MC_VM_XGMI_LFB_CNTL; 438 uint32_t AZALIA_AUDIO_DTO; 439 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 440 }; 441 /* set field name */ 442 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 443 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 444 445 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 446 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 447 448 449 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 450 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 451 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 452 453 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 454 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 455 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 456 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 457 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 458 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 459 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 460 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 461 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 462 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 463 464 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 465 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 466 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 467 468 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 469 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 470 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 471 472 #define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\ 473 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 474 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ 475 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ 476 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 477 478 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 479 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 480 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 481 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 482 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 483 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 484 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 485 HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) 486 487 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 488 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 489 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 490 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 491 HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) 492 493 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 494 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 495 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 496 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 497 498 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 499 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 500 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 501 502 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 503 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 504 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 505 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 506 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 507 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 508 509 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 510 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 511 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 512 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 513 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 514 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\ 515 HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) 516 517 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 518 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 519 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 520 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 521 522 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 523 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 524 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 525 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 526 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 527 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 528 529 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 530 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 531 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 532 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 533 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 534 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 535 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 536 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 537 /* todo: get these from GVM instead of reading registers ourselves */\ 538 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 539 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 540 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 541 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 542 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 543 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 544 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 545 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 546 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 547 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 548 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 549 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 550 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 551 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 552 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 553 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 554 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 555 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 556 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 557 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 558 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 559 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 560 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 561 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 562 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 563 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 564 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 565 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 566 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 567 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 568 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 569 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 570 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 571 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 572 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 573 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 574 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 575 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 576 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 577 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ 578 HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) 579 580 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 581 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 582 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 583 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 584 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 585 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 586 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 587 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 588 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 589 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 590 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 591 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 592 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 593 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 594 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 595 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 596 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 597 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 598 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 599 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 600 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 601 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 602 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 603 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 604 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 605 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 606 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 607 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 608 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 609 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 610 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 611 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 612 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 613 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 614 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 615 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 616 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 617 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 618 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 619 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 620 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 621 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 622 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 623 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 624 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 625 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 626 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 627 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 628 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 629 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 630 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 631 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 632 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 633 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 634 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 635 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 636 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 637 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 638 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 639 HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) 640 #endif 641 642 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 643 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ 644 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 645 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 646 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 647 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 648 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 649 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 650 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 651 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 652 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 653 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 654 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 655 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 656 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 657 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 658 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 659 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 660 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 661 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 662 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 663 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 664 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 665 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 666 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 667 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 668 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 669 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 670 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 671 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 672 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 673 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 674 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 675 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 676 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 677 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 678 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 679 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 680 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 681 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 682 HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \ 683 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 684 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 685 #endif 686 687 #define HWSEQ_REG_FIELD_LIST(type) \ 688 type DCFE_CLOCK_ENABLE; \ 689 type DCFEV_CLOCK_ENABLE; \ 690 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 691 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 692 type BLND_SCL_V_UPDATE_LOCK; \ 693 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 694 type BLND_BLND_V_UPDATE_LOCK; \ 695 type BLND_V_UPDATE_LOCK_MODE; \ 696 type BLND_FEEDTHROUGH_EN; \ 697 type BLND_ALPHA_MODE; \ 698 type BLND_MODE; \ 699 type BLND_MULTIPLIED_MODE; \ 700 type DP_DTO0_ENABLE; \ 701 type PIXEL_RATE_SOURCE; \ 702 type PHYPLL_PIXEL_RATE_SOURCE; \ 703 type PIXEL_RATE_PLL_SOURCE; \ 704 /* todo: get these from GVM instead of reading registers ourselves */\ 705 type PAGE_DIRECTORY_ENTRY_HI32;\ 706 type PAGE_DIRECTORY_ENTRY_LO32;\ 707 type LOGICAL_PAGE_NUMBER_HI4;\ 708 type LOGICAL_PAGE_NUMBER_LO32;\ 709 type PHYSICAL_PAGE_ADDR_HI4;\ 710 type PHYSICAL_PAGE_ADDR_LO32;\ 711 type PHYSICAL_PAGE_NUMBER_MSB;\ 712 type PHYSICAL_PAGE_NUMBER_LSB;\ 713 type LOGICAL_ADDR; \ 714 type PF_LFB_REGION;\ 715 type PF_MAX_REGION;\ 716 type ENABLE_L1_TLB;\ 717 type SYSTEM_ACCESS_MODE;\ 718 type LVTMA_BLON;\ 719 type LVTMA_DIGON;\ 720 type LVTMA_DIGON_OVRD;\ 721 type LVTMA_PWRSEQ_TARGET_STATE_R; 722 723 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 724 type HUBP_VTG_SEL; \ 725 type HUBP_CLOCK_ENABLE; \ 726 type DPP_CLOCK_ENABLE; \ 727 type SDPIF_FB_BASE;\ 728 type SDPIF_FB_OFFSET;\ 729 type SDPIF_AGP_BASE;\ 730 type SDPIF_AGP_BOT;\ 731 type SDPIF_AGP_TOP;\ 732 type FB_TOP;\ 733 type FB_BASE;\ 734 type FB_OFFSET;\ 735 type AGP_BASE;\ 736 type AGP_BOT;\ 737 type AGP_TOP;\ 738 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 739 type OPP_PIPE_CLOCK_EN;\ 740 type IP_REQUEST_EN; \ 741 type DOMAIN0_POWER_FORCEON; \ 742 type DOMAIN0_POWER_GATE; \ 743 type DOMAIN1_POWER_FORCEON; \ 744 type DOMAIN1_POWER_GATE; \ 745 type DOMAIN2_POWER_FORCEON; \ 746 type DOMAIN2_POWER_GATE; \ 747 type DOMAIN3_POWER_FORCEON; \ 748 type DOMAIN3_POWER_GATE; \ 749 type DOMAIN4_POWER_FORCEON; \ 750 type DOMAIN4_POWER_GATE; \ 751 type DOMAIN5_POWER_FORCEON; \ 752 type DOMAIN5_POWER_GATE; \ 753 type DOMAIN6_POWER_FORCEON; \ 754 type DOMAIN6_POWER_GATE; \ 755 type DOMAIN7_POWER_FORCEON; \ 756 type DOMAIN7_POWER_GATE; \ 757 type DOMAIN8_POWER_FORCEON; \ 758 type DOMAIN8_POWER_GATE; \ 759 type DOMAIN9_POWER_FORCEON; \ 760 type DOMAIN9_POWER_GATE; \ 761 type DOMAIN10_POWER_FORCEON; \ 762 type DOMAIN10_POWER_GATE; \ 763 type DOMAIN11_POWER_FORCEON; \ 764 type DOMAIN11_POWER_GATE; \ 765 type DOMAIN16_POWER_FORCEON; \ 766 type DOMAIN16_POWER_GATE; \ 767 type DOMAIN17_POWER_FORCEON; \ 768 type DOMAIN17_POWER_GATE; \ 769 type DOMAIN18_POWER_FORCEON; \ 770 type DOMAIN18_POWER_GATE; \ 771 type DOMAIN19_POWER_FORCEON; \ 772 type DOMAIN19_POWER_GATE; \ 773 type DOMAIN20_POWER_FORCEON; \ 774 type DOMAIN20_POWER_GATE; \ 775 type DOMAIN21_POWER_FORCEON; \ 776 type DOMAIN21_POWER_GATE; \ 777 type DOMAIN0_PGFSM_PWR_STATUS; \ 778 type DOMAIN1_PGFSM_PWR_STATUS; \ 779 type DOMAIN2_PGFSM_PWR_STATUS; \ 780 type DOMAIN3_PGFSM_PWR_STATUS; \ 781 type DOMAIN4_PGFSM_PWR_STATUS; \ 782 type DOMAIN5_PGFSM_PWR_STATUS; \ 783 type DOMAIN6_PGFSM_PWR_STATUS; \ 784 type DOMAIN7_PGFSM_PWR_STATUS; \ 785 type DOMAIN8_PGFSM_PWR_STATUS; \ 786 type DOMAIN9_PGFSM_PWR_STATUS; \ 787 type DOMAIN10_PGFSM_PWR_STATUS; \ 788 type DOMAIN11_PGFSM_PWR_STATUS; \ 789 type DOMAIN16_PGFSM_PWR_STATUS; \ 790 type DOMAIN17_PGFSM_PWR_STATUS; \ 791 type DOMAIN18_PGFSM_PWR_STATUS; \ 792 type DOMAIN19_PGFSM_PWR_STATUS; \ 793 type DOMAIN20_PGFSM_PWR_STATUS; \ 794 type DOMAIN21_PGFSM_PWR_STATUS; \ 795 type DCFCLK_GATE_DIS; \ 796 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 797 type VGA_TEST_ENABLE; \ 798 type VGA_TEST_RENDER_START; \ 799 type D1VGA_MODE_ENABLE; \ 800 type D2VGA_MODE_ENABLE; \ 801 type D3VGA_MODE_ENABLE; \ 802 type D4VGA_MODE_ENABLE; \ 803 type AZALIA_AUDIO_DTO_MODULE;\ 804 type HPO_HDMISTREAMCLK_GATE_DIS; 805 806 struct dce_hwseq_shift { 807 HWSEQ_REG_FIELD_LIST(uint8_t) 808 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 809 }; 810 811 struct dce_hwseq_mask { 812 HWSEQ_REG_FIELD_LIST(uint32_t) 813 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 814 }; 815 816 817 enum blnd_mode { 818 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 819 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 820 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 821 }; 822 823 void dce_enable_fe_clock(struct dce_hwseq *hwss, 824 unsigned int inst, bool enable); 825 826 void dce_pipe_control_lock(struct dc *dc, 827 struct pipe_ctx *pipe, 828 bool lock); 829 830 void dce_set_blender_mode(struct dce_hwseq *hws, 831 unsigned int blnd_inst, enum blnd_mode mode); 832 833 void dce_clock_gating_power_up(struct dce_hwseq *hws, 834 bool enable); 835 836 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 837 struct clock_source *clk_src, 838 unsigned int tg_inst); 839 840 bool dce_use_lut(enum surface_pixel_format format); 841 #endif /*__DCE_HWSEQ_H__*/ 842