1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "dc_types.h" 29 30 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 37 38 #define HWSEQ_DCEF_REG_LIST() \ 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 46 47 #define HWSEQ_BLND_REG_LIST() \ 48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 54 SRII(BLND_CONTROL, BLND, 0), \ 55 SRII(BLND_CONTROL, BLND, 1), \ 56 SRII(BLND_CONTROL, BLND, 2), \ 57 SRII(BLND_CONTROL, BLND, 3), \ 58 SRII(BLND_CONTROL, BLND, 4), \ 59 SRII(BLND_CONTROL, BLND, 5) 60 61 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ 62 SRII(PIXEL_RATE_CNTL, blk, inst), \ 63 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \ 82 SRII(PIXEL_RATE_CNTL, blk, 0), \ 83 SRII(PIXEL_RATE_CNTL, blk, 1),\ 84 SRII(PIXEL_RATE_CNTL, blk, 2),\ 85 SRII(PIXEL_RATE_CNTL, blk, 3), \ 86 SRII(PIXEL_RATE_CNTL, blk, 4), \ 87 SRII(PIXEL_RATE_CNTL, blk, 5) 88 89 #define HWSEQ_PHYPLL_REG_LIST_3(blk) \ 90 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 91 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ 92 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ 93 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 94 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 95 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 96 97 #define HWSEQ_DCE11_REG_LIST_BASE() \ 98 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 99 SR(DCFEV_CLOCK_CONTROL), \ 100 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 101 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 102 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 103 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 104 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 105 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 106 SRII(BLND_CONTROL, BLND, 0),\ 107 SRII(BLND_CONTROL, BLND, 1),\ 108 SR(BLNDV_CONTROL),\ 109 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 110 111 #if defined(CONFIG_DRM_AMD_DC_SI) 112 #define HWSEQ_DCE6_REG_LIST() \ 113 HWSEQ_DCEF_REG_LIST_DCE8(), \ 114 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 115 #endif 116 117 #define HWSEQ_DCE8_REG_LIST() \ 118 HWSEQ_DCEF_REG_LIST_DCE8(), \ 119 HWSEQ_BLND_REG_LIST(), \ 120 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 121 122 #define HWSEQ_DCE10_REG_LIST() \ 123 HWSEQ_DCEF_REG_LIST(), \ 124 HWSEQ_BLND_REG_LIST(), \ 125 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 126 127 #define HWSEQ_ST_REG_LIST() \ 128 HWSEQ_DCE11_REG_LIST_BASE(), \ 129 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 130 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 131 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 132 .BLND_CONTROL[2] = mmBLNDV_CONTROL 133 134 #define HWSEQ_CZ_REG_LIST() \ 135 HWSEQ_DCE11_REG_LIST_BASE(), \ 136 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 137 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 138 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 139 SRII(BLND_CONTROL, BLND, 2), \ 140 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 141 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 142 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 143 .BLND_CONTROL[3] = mmBLNDV_CONTROL 144 145 #define HWSEQ_DCE120_REG_LIST() \ 146 HWSEQ_DCE10_REG_LIST(), \ 147 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 148 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 149 SR(DCHUB_FB_LOCATION),\ 150 SR(DCHUB_AGP_BASE),\ 151 SR(DCHUB_AGP_BOT),\ 152 SR(DCHUB_AGP_TOP) 153 154 #define HWSEQ_VG20_REG_LIST() \ 155 HWSEQ_DCE120_REG_LIST(),\ 156 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 157 158 #define HWSEQ_DCE112_REG_LIST() \ 159 HWSEQ_DCE10_REG_LIST(), \ 160 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 161 HWSEQ_PHYPLL_REG_LIST(CRTC) 162 163 #define HWSEQ_DCN_REG_LIST()\ 164 SR(REFCLK_CNTL), \ 165 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 166 SR(DIO_MEM_PWR_CTRL), \ 167 SR(DCCG_GATE_DISABLE_CNTL), \ 168 SR(DCCG_GATE_DISABLE_CNTL2), \ 169 SR(DCFCLK_CNTL),\ 170 SR(DCFCLK_CNTL), \ 171 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 172 173 174 #define MMHUB_DCN_REG_LIST()\ 175 /* todo: get these from GVM instead of reading registers ourselves */\ 176 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 177 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 178 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 179 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 180 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 181 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 182 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 183 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 184 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 185 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 186 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 187 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 188 189 190 #define HWSEQ_DCN1_REG_LIST()\ 191 HWSEQ_DCN_REG_LIST(), \ 192 MMHUB_DCN_REG_LIST(), \ 193 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 194 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 195 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 196 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 197 SR(DCHUBBUB_SDPIF_FB_BASE),\ 198 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 199 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 200 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 201 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 202 SR(DOMAIN0_PG_CONFIG), \ 203 SR(DOMAIN1_PG_CONFIG), \ 204 SR(DOMAIN2_PG_CONFIG), \ 205 SR(DOMAIN3_PG_CONFIG), \ 206 SR(DOMAIN4_PG_CONFIG), \ 207 SR(DOMAIN5_PG_CONFIG), \ 208 SR(DOMAIN6_PG_CONFIG), \ 209 SR(DOMAIN7_PG_CONFIG), \ 210 SR(DOMAIN0_PG_STATUS), \ 211 SR(DOMAIN1_PG_STATUS), \ 212 SR(DOMAIN2_PG_STATUS), \ 213 SR(DOMAIN3_PG_STATUS), \ 214 SR(DOMAIN4_PG_STATUS), \ 215 SR(DOMAIN5_PG_STATUS), \ 216 SR(DOMAIN6_PG_STATUS), \ 217 SR(DOMAIN7_PG_STATUS), \ 218 SR(D1VGA_CONTROL), \ 219 SR(D2VGA_CONTROL), \ 220 SR(D3VGA_CONTROL), \ 221 SR(D4VGA_CONTROL), \ 222 SR(VGA_TEST_CONTROL), \ 223 SR(DC_IP_REQUEST_CNTL) 224 225 #define HWSEQ_DCN2_REG_LIST()\ 226 HWSEQ_DCN_REG_LIST(), \ 227 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 228 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 229 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 230 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 231 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 232 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ 233 SR(MICROSECOND_TIME_BASE_DIV), \ 234 SR(MILLISECOND_TIME_BASE_DIV), \ 235 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 236 SR(RBBMIF_TIMEOUT_DIS), \ 237 SR(RBBMIF_TIMEOUT_DIS_2), \ 238 SR(DCHUBBUB_CRC_CTRL), \ 239 SR(DPP_TOP0_DPP_CRC_CTRL), \ 240 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 241 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 242 SR(MPC_CRC_CTRL), \ 243 SR(MPC_CRC_RESULT_GB), \ 244 SR(MPC_CRC_RESULT_C), \ 245 SR(MPC_CRC_RESULT_AR), \ 246 SR(DOMAIN0_PG_CONFIG), \ 247 SR(DOMAIN1_PG_CONFIG), \ 248 SR(DOMAIN2_PG_CONFIG), \ 249 SR(DOMAIN3_PG_CONFIG), \ 250 SR(DOMAIN4_PG_CONFIG), \ 251 SR(DOMAIN5_PG_CONFIG), \ 252 SR(DOMAIN6_PG_CONFIG), \ 253 SR(DOMAIN7_PG_CONFIG), \ 254 SR(DOMAIN8_PG_CONFIG), \ 255 SR(DOMAIN9_PG_CONFIG), \ 256 /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ 257 /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ 258 SR(DOMAIN16_PG_CONFIG), \ 259 SR(DOMAIN17_PG_CONFIG), \ 260 SR(DOMAIN18_PG_CONFIG), \ 261 SR(DOMAIN19_PG_CONFIG), \ 262 SR(DOMAIN20_PG_CONFIG), \ 263 SR(DOMAIN21_PG_CONFIG), \ 264 SR(DOMAIN0_PG_STATUS), \ 265 SR(DOMAIN1_PG_STATUS), \ 266 SR(DOMAIN2_PG_STATUS), \ 267 SR(DOMAIN3_PG_STATUS), \ 268 SR(DOMAIN4_PG_STATUS), \ 269 SR(DOMAIN5_PG_STATUS), \ 270 SR(DOMAIN6_PG_STATUS), \ 271 SR(DOMAIN7_PG_STATUS), \ 272 SR(DOMAIN8_PG_STATUS), \ 273 SR(DOMAIN9_PG_STATUS), \ 274 SR(DOMAIN10_PG_STATUS), \ 275 SR(DOMAIN11_PG_STATUS), \ 276 SR(DOMAIN16_PG_STATUS), \ 277 SR(DOMAIN17_PG_STATUS), \ 278 SR(DOMAIN18_PG_STATUS), \ 279 SR(DOMAIN19_PG_STATUS), \ 280 SR(DOMAIN20_PG_STATUS), \ 281 SR(DOMAIN21_PG_STATUS), \ 282 SR(D1VGA_CONTROL), \ 283 SR(D2VGA_CONTROL), \ 284 SR(D3VGA_CONTROL), \ 285 SR(D4VGA_CONTROL), \ 286 SR(D5VGA_CONTROL), \ 287 SR(D6VGA_CONTROL), \ 288 SR(DC_IP_REQUEST_CNTL) 289 290 #define HWSEQ_DCN21_REG_LIST()\ 291 HWSEQ_DCN_REG_LIST(), \ 292 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 293 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 294 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 295 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 296 MMHUB_DCN_REG_LIST(), \ 297 SR(MICROSECOND_TIME_BASE_DIV), \ 298 SR(MILLISECOND_TIME_BASE_DIV), \ 299 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 300 SR(RBBMIF_TIMEOUT_DIS), \ 301 SR(RBBMIF_TIMEOUT_DIS_2), \ 302 SR(DCHUBBUB_CRC_CTRL), \ 303 SR(DPP_TOP0_DPP_CRC_CTRL), \ 304 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 305 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 306 SR(MPC_CRC_CTRL), \ 307 SR(MPC_CRC_RESULT_GB), \ 308 SR(MPC_CRC_RESULT_C), \ 309 SR(MPC_CRC_RESULT_AR), \ 310 SR(DOMAIN0_PG_CONFIG), \ 311 SR(DOMAIN1_PG_CONFIG), \ 312 SR(DOMAIN2_PG_CONFIG), \ 313 SR(DOMAIN3_PG_CONFIG), \ 314 SR(DOMAIN4_PG_CONFIG), \ 315 SR(DOMAIN5_PG_CONFIG), \ 316 SR(DOMAIN6_PG_CONFIG), \ 317 SR(DOMAIN7_PG_CONFIG), \ 318 SR(DOMAIN16_PG_CONFIG), \ 319 SR(DOMAIN17_PG_CONFIG), \ 320 SR(DOMAIN18_PG_CONFIG), \ 321 SR(DOMAIN0_PG_STATUS), \ 322 SR(DOMAIN1_PG_STATUS), \ 323 SR(DOMAIN2_PG_STATUS), \ 324 SR(DOMAIN3_PG_STATUS), \ 325 SR(DOMAIN4_PG_STATUS), \ 326 SR(DOMAIN5_PG_STATUS), \ 327 SR(DOMAIN6_PG_STATUS), \ 328 SR(DOMAIN7_PG_STATUS), \ 329 SR(DOMAIN16_PG_STATUS), \ 330 SR(DOMAIN17_PG_STATUS), \ 331 SR(DOMAIN18_PG_STATUS), \ 332 SR(D1VGA_CONTROL), \ 333 SR(D2VGA_CONTROL), \ 334 SR(D3VGA_CONTROL), \ 335 SR(D4VGA_CONTROL), \ 336 SR(D5VGA_CONTROL), \ 337 SR(D6VGA_CONTROL), \ 338 SR(DC_IP_REQUEST_CNTL) 339 340 #define HWSEQ_DCN30_REG_LIST()\ 341 HWSEQ_DCN2_REG_LIST(),\ 342 HWSEQ_DCN_REG_LIST(), \ 343 HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \ 344 HWSEQ_PHYPLL_REG_LIST_3(OTG), \ 345 SR(MICROSECOND_TIME_BASE_DIV), \ 346 SR(MILLISECOND_TIME_BASE_DIV), \ 347 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 348 SR(RBBMIF_TIMEOUT_DIS), \ 349 SR(RBBMIF_TIMEOUT_DIS_2), \ 350 SR(DCHUBBUB_CRC_CTRL), \ 351 SR(DPP_TOP0_DPP_CRC_CTRL), \ 352 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 353 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 354 SR(MPC_CRC_CTRL), \ 355 SR(MPC_CRC_RESULT_GB), \ 356 SR(MPC_CRC_RESULT_C), \ 357 SR(MPC_CRC_RESULT_AR), \ 358 SR(AZALIA_AUDIO_DTO), \ 359 SR(AZALIA_CONTROLLER_CLOCK_GATING) 360 361 #define HWSEQ_DCN301_REG_LIST()\ 362 SR(REFCLK_CNTL), \ 363 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 364 SR(DIO_MEM_PWR_CTRL), \ 365 SR(DCCG_GATE_DISABLE_CNTL), \ 366 SR(DCCG_GATE_DISABLE_CNTL2), \ 367 SR(DCFCLK_CNTL),\ 368 SR(DCFCLK_CNTL), \ 369 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 370 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 371 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 372 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 373 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 374 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 375 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 376 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 377 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 378 SR(MICROSECOND_TIME_BASE_DIV), \ 379 SR(MILLISECOND_TIME_BASE_DIV), \ 380 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 381 SR(RBBMIF_TIMEOUT_DIS), \ 382 SR(RBBMIF_TIMEOUT_DIS_2), \ 383 SR(DCHUBBUB_CRC_CTRL), \ 384 SR(DPP_TOP0_DPP_CRC_CTRL), \ 385 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 386 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 387 SR(MPC_CRC_CTRL), \ 388 SR(MPC_CRC_RESULT_GB), \ 389 SR(MPC_CRC_RESULT_C), \ 390 SR(MPC_CRC_RESULT_AR), \ 391 SR(DOMAIN0_PG_CONFIG), \ 392 SR(DOMAIN1_PG_CONFIG), \ 393 SR(DOMAIN2_PG_CONFIG), \ 394 SR(DOMAIN3_PG_CONFIG), \ 395 SR(DOMAIN4_PG_CONFIG), \ 396 SR(DOMAIN5_PG_CONFIG), \ 397 SR(DOMAIN6_PG_CONFIG), \ 398 SR(DOMAIN7_PG_CONFIG), \ 399 SR(DOMAIN16_PG_CONFIG), \ 400 SR(DOMAIN17_PG_CONFIG), \ 401 SR(DOMAIN18_PG_CONFIG), \ 402 SR(DOMAIN0_PG_STATUS), \ 403 SR(DOMAIN1_PG_STATUS), \ 404 SR(DOMAIN2_PG_STATUS), \ 405 SR(DOMAIN3_PG_STATUS), \ 406 SR(DOMAIN4_PG_STATUS), \ 407 SR(DOMAIN5_PG_STATUS), \ 408 SR(DOMAIN6_PG_STATUS), \ 409 SR(DOMAIN7_PG_STATUS), \ 410 SR(DOMAIN16_PG_STATUS), \ 411 SR(DOMAIN17_PG_STATUS), \ 412 SR(DOMAIN18_PG_STATUS), \ 413 SR(D1VGA_CONTROL), \ 414 SR(D2VGA_CONTROL), \ 415 SR(D3VGA_CONTROL), \ 416 SR(D4VGA_CONTROL), \ 417 SR(D5VGA_CONTROL), \ 418 SR(D6VGA_CONTROL), \ 419 SR(DC_IP_REQUEST_CNTL), \ 420 SR(AZALIA_AUDIO_DTO), \ 421 SR(AZALIA_CONTROLLER_CLOCK_GATING) 422 423 #define HWSEQ_DCN302_REG_LIST()\ 424 HWSEQ_DCN_REG_LIST(), \ 425 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 426 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 427 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 428 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 429 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 430 SR(MICROSECOND_TIME_BASE_DIV), \ 431 SR(MILLISECOND_TIME_BASE_DIV), \ 432 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 433 SR(RBBMIF_TIMEOUT_DIS), \ 434 SR(RBBMIF_TIMEOUT_DIS_2), \ 435 SR(DCHUBBUB_CRC_CTRL), \ 436 SR(DPP_TOP0_DPP_CRC_CTRL), \ 437 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 438 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 439 SR(MPC_CRC_CTRL), \ 440 SR(MPC_CRC_RESULT_GB), \ 441 SR(MPC_CRC_RESULT_C), \ 442 SR(MPC_CRC_RESULT_AR), \ 443 SR(DOMAIN0_PG_CONFIG), \ 444 SR(DOMAIN1_PG_CONFIG), \ 445 SR(DOMAIN2_PG_CONFIG), \ 446 SR(DOMAIN3_PG_CONFIG), \ 447 SR(DOMAIN4_PG_CONFIG), \ 448 SR(DOMAIN5_PG_CONFIG), \ 449 SR(DOMAIN6_PG_CONFIG), \ 450 SR(DOMAIN7_PG_CONFIG), \ 451 SR(DOMAIN8_PG_CONFIG), \ 452 SR(DOMAIN9_PG_CONFIG), \ 453 SR(DOMAIN16_PG_CONFIG), \ 454 SR(DOMAIN17_PG_CONFIG), \ 455 SR(DOMAIN18_PG_CONFIG), \ 456 SR(DOMAIN19_PG_CONFIG), \ 457 SR(DOMAIN20_PG_CONFIG), \ 458 SR(DOMAIN0_PG_STATUS), \ 459 SR(DOMAIN1_PG_STATUS), \ 460 SR(DOMAIN2_PG_STATUS), \ 461 SR(DOMAIN3_PG_STATUS), \ 462 SR(DOMAIN4_PG_STATUS), \ 463 SR(DOMAIN5_PG_STATUS), \ 464 SR(DOMAIN6_PG_STATUS), \ 465 SR(DOMAIN7_PG_STATUS), \ 466 SR(DOMAIN8_PG_STATUS), \ 467 SR(DOMAIN9_PG_STATUS), \ 468 SR(DOMAIN16_PG_STATUS), \ 469 SR(DOMAIN17_PG_STATUS), \ 470 SR(DOMAIN18_PG_STATUS), \ 471 SR(DOMAIN19_PG_STATUS), \ 472 SR(DOMAIN20_PG_STATUS), \ 473 SR(D1VGA_CONTROL), \ 474 SR(D2VGA_CONTROL), \ 475 SR(D3VGA_CONTROL), \ 476 SR(D4VGA_CONTROL), \ 477 SR(D5VGA_CONTROL), \ 478 SR(D6VGA_CONTROL), \ 479 SR(DC_IP_REQUEST_CNTL), \ 480 SR(AZALIA_AUDIO_DTO), \ 481 SR(AZALIA_CONTROLLER_CLOCK_GATING) 482 483 #define HWSEQ_DCN303_REG_LIST() \ 484 HWSEQ_DCN_REG_LIST(), \ 485 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 486 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 487 SR(MICROSECOND_TIME_BASE_DIV), \ 488 SR(MILLISECOND_TIME_BASE_DIV), \ 489 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 490 SR(RBBMIF_TIMEOUT_DIS), \ 491 SR(RBBMIF_TIMEOUT_DIS_2), \ 492 SR(DCHUBBUB_CRC_CTRL), \ 493 SR(DPP_TOP0_DPP_CRC_CTRL), \ 494 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 495 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 496 SR(MPC_CRC_CTRL), \ 497 SR(MPC_CRC_RESULT_GB), \ 498 SR(MPC_CRC_RESULT_C), \ 499 SR(MPC_CRC_RESULT_AR), \ 500 SR(D1VGA_CONTROL), \ 501 SR(D2VGA_CONTROL), \ 502 SR(D3VGA_CONTROL), \ 503 SR(D4VGA_CONTROL), \ 504 SR(D5VGA_CONTROL), \ 505 SR(D6VGA_CONTROL), \ 506 HWSEQ_PIXEL_RATE_REG_LIST_303(OTG), \ 507 HWSEQ_PHYPLL_REG_LIST_303(OTG), \ 508 SR(AZALIA_AUDIO_DTO), \ 509 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 510 SR(HPO_TOP_CLOCK_CONTROL) 511 512 #define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \ 513 SRII(PIXEL_RATE_CNTL, blk, 0), \ 514 SRII(PIXEL_RATE_CNTL, blk, 1),\ 515 SRII(PIXEL_RATE_CNTL, blk, 2),\ 516 SRII(PIXEL_RATE_CNTL, blk, 3), \ 517 SRII(PIXEL_RATE_CNTL, blk, 4) 518 519 #define HWSEQ_PHYPLL_REG_LIST_302(blk) \ 520 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 521 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ 522 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ 523 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 524 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4) 525 526 #define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \ 527 SRII(PIXEL_RATE_CNTL, blk, 0), \ 528 SRII(PIXEL_RATE_CNTL, blk, 1) 529 530 #define HWSEQ_PHYPLL_REG_LIST_303(blk) \ 531 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 532 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1) 533 534 struct dce_hwseq_registers { 535 uint32_t DCFE_CLOCK_CONTROL[6]; 536 uint32_t DCFEV_CLOCK_CONTROL; 537 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 538 uint32_t BLND_V_UPDATE_LOCK[6]; 539 uint32_t BLND_CONTROL[6]; 540 uint32_t BLNDV_CONTROL; 541 uint32_t CRTC_H_BLANK_START_END[6]; 542 uint32_t PIXEL_RATE_CNTL[6]; 543 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 544 /*DCHUB*/ 545 uint32_t DCHUB_FB_LOCATION; 546 uint32_t DCHUB_AGP_BASE; 547 uint32_t DCHUB_AGP_BOT; 548 uint32_t DCHUB_AGP_TOP; 549 550 uint32_t REFCLK_CNTL; 551 552 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 553 uint32_t DCHUBBUB_SDPIF_FB_BASE; 554 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 555 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 556 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 557 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 558 uint32_t DC_IP_REQUEST_CNTL; 559 uint32_t DOMAIN0_PG_CONFIG; 560 uint32_t DOMAIN1_PG_CONFIG; 561 uint32_t DOMAIN2_PG_CONFIG; 562 uint32_t DOMAIN3_PG_CONFIG; 563 uint32_t DOMAIN4_PG_CONFIG; 564 uint32_t DOMAIN5_PG_CONFIG; 565 uint32_t DOMAIN6_PG_CONFIG; 566 uint32_t DOMAIN7_PG_CONFIG; 567 uint32_t DOMAIN8_PG_CONFIG; 568 uint32_t DOMAIN9_PG_CONFIG; 569 uint32_t DOMAIN10_PG_CONFIG; 570 uint32_t DOMAIN11_PG_CONFIG; 571 uint32_t DOMAIN16_PG_CONFIG; 572 uint32_t DOMAIN17_PG_CONFIG; 573 uint32_t DOMAIN18_PG_CONFIG; 574 uint32_t DOMAIN19_PG_CONFIG; 575 uint32_t DOMAIN20_PG_CONFIG; 576 uint32_t DOMAIN21_PG_CONFIG; 577 uint32_t DOMAIN0_PG_STATUS; 578 uint32_t DOMAIN1_PG_STATUS; 579 uint32_t DOMAIN2_PG_STATUS; 580 uint32_t DOMAIN3_PG_STATUS; 581 uint32_t DOMAIN4_PG_STATUS; 582 uint32_t DOMAIN5_PG_STATUS; 583 uint32_t DOMAIN6_PG_STATUS; 584 uint32_t DOMAIN7_PG_STATUS; 585 uint32_t DOMAIN8_PG_STATUS; 586 uint32_t DOMAIN9_PG_STATUS; 587 uint32_t DOMAIN10_PG_STATUS; 588 uint32_t DOMAIN11_PG_STATUS; 589 uint32_t DOMAIN16_PG_STATUS; 590 uint32_t DOMAIN17_PG_STATUS; 591 uint32_t DOMAIN18_PG_STATUS; 592 uint32_t DOMAIN19_PG_STATUS; 593 uint32_t DOMAIN20_PG_STATUS; 594 uint32_t DOMAIN21_PG_STATUS; 595 uint32_t DIO_MEM_PWR_CTRL; 596 uint32_t DCCG_GATE_DISABLE_CNTL; 597 uint32_t DCCG_GATE_DISABLE_CNTL2; 598 uint32_t DCFCLK_CNTL; 599 uint32_t MICROSECOND_TIME_BASE_DIV; 600 uint32_t MILLISECOND_TIME_BASE_DIV; 601 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 602 uint32_t RBBMIF_TIMEOUT_DIS; 603 uint32_t RBBMIF_TIMEOUT_DIS_2; 604 uint32_t DCHUBBUB_CRC_CTRL; 605 uint32_t DPP_TOP0_DPP_CRC_CTRL; 606 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 607 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 608 uint32_t MPC_CRC_CTRL; 609 uint32_t MPC_CRC_RESULT_GB; 610 uint32_t MPC_CRC_RESULT_C; 611 uint32_t MPC_CRC_RESULT_AR; 612 uint32_t D1VGA_CONTROL; 613 uint32_t D2VGA_CONTROL; 614 uint32_t D3VGA_CONTROL; 615 uint32_t D4VGA_CONTROL; 616 uint32_t D5VGA_CONTROL; 617 uint32_t D6VGA_CONTROL; 618 uint32_t VGA_TEST_CONTROL; 619 /* MMHUB registers. read only. temporary hack */ 620 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 621 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 622 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 623 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 624 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 625 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 626 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 627 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 628 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 629 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 630 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 631 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 632 uint32_t MC_VM_XGMI_LFB_CNTL; 633 uint32_t AZALIA_AUDIO_DTO; 634 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 635 uint32_t HPO_TOP_CLOCK_CONTROL; 636 uint32_t ODM_MEM_PWR_CTRL3; 637 uint32_t DMU_MEM_PWR_CNTL; 638 uint32_t MMHUBBUB_MEM_PWR_CNTL; 639 }; 640 /* set field name */ 641 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 642 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 643 644 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 645 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 646 647 648 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 649 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 650 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 651 652 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 653 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 654 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 655 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 656 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 657 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 658 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 659 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 660 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 661 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 662 663 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 664 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 665 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 666 667 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 668 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 669 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 670 671 #if defined(CONFIG_DRM_AMD_DC_SI) 672 #define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\ 673 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 674 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 675 #endif 676 677 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 678 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 679 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 680 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 681 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 682 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 683 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 684 685 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 686 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 687 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 688 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 689 690 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 691 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 692 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 693 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 694 695 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 696 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 697 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 698 699 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 700 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 701 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 702 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 703 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 704 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 705 706 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 707 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 708 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 709 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 710 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 711 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) 712 713 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 714 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 715 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 716 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 717 718 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 719 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 720 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 721 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 722 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 723 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 724 725 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 726 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 727 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 728 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 729 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 730 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 731 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 732 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 733 /* todo: get these from GVM instead of reading registers ourselves */\ 734 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 735 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 736 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 737 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 738 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 739 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 740 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 741 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 742 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 743 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 744 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 745 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 746 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 747 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 748 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 749 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 750 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 751 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 752 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 753 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 754 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 755 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 756 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 757 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 758 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 759 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 760 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 761 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 762 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 763 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 764 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 765 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 766 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 767 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 768 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 769 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 770 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 771 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 772 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 773 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 774 775 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 776 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 777 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 778 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 779 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 780 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 781 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 782 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 783 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 784 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 785 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 786 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 787 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 788 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 789 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 790 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 791 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 792 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 793 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 794 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 795 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 796 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 797 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 798 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 799 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 800 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 801 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 802 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 803 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 804 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 805 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 806 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 807 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 808 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 809 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 810 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 811 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 812 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 813 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 814 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 815 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 816 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 817 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 818 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 819 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 820 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 821 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 822 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 823 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 824 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 825 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 826 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 827 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 828 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 829 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 830 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 831 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 832 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 833 834 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ 835 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 836 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 837 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 838 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 839 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 840 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 841 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 842 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 843 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 844 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 845 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 846 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 847 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 848 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 849 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 850 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 851 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 852 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 853 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 854 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 855 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 856 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 857 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 858 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 859 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 860 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 861 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 862 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 863 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 864 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 865 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 866 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 867 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 868 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 869 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 870 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 871 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 872 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 873 874 #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\ 875 HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \ 876 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 877 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 878 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 879 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 880 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 881 882 #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\ 883 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 884 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 885 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 886 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 887 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 888 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 889 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 890 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 891 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 892 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 893 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 894 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 895 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 896 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 897 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 898 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 899 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 900 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 901 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 902 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 903 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 904 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 905 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 906 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 907 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 908 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 909 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 910 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 911 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 912 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 913 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 914 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 915 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 916 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 917 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 918 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 919 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\ 920 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\ 921 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\ 922 HWS_SF(, PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh),\ 923 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 924 925 #define HWSEQ_DCN302_MASK_SH_LIST(mask_sh)\ 926 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 927 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 928 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 929 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 930 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 931 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 932 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 933 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 934 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 935 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 936 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 937 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 938 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 939 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 940 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 941 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 942 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 943 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 944 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 945 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 946 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 947 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 948 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 949 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 950 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 951 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 952 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 953 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 954 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 955 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 956 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 957 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 958 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 959 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 960 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 961 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 962 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 963 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 964 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 965 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 966 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 967 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 968 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 969 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 970 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 971 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 972 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 973 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 974 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 975 976 #define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) \ 977 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 978 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 979 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 980 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh) 981 982 #define HWSEQ_REG_FIELD_LIST(type) \ 983 type DCFE_CLOCK_ENABLE; \ 984 type DCFEV_CLOCK_ENABLE; \ 985 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 986 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 987 type BLND_SCL_V_UPDATE_LOCK; \ 988 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 989 type BLND_BLND_V_UPDATE_LOCK; \ 990 type BLND_V_UPDATE_LOCK_MODE; \ 991 type BLND_FEEDTHROUGH_EN; \ 992 type BLND_ALPHA_MODE; \ 993 type BLND_MODE; \ 994 type BLND_MULTIPLIED_MODE; \ 995 type DP_DTO0_ENABLE; \ 996 type PIXEL_RATE_SOURCE; \ 997 type PHYPLL_PIXEL_RATE_SOURCE; \ 998 type PIXEL_RATE_PLL_SOURCE; \ 999 /* todo: get these from GVM instead of reading registers ourselves */\ 1000 type PAGE_DIRECTORY_ENTRY_HI32;\ 1001 type PAGE_DIRECTORY_ENTRY_LO32;\ 1002 type LOGICAL_PAGE_NUMBER_HI4;\ 1003 type LOGICAL_PAGE_NUMBER_LO32;\ 1004 type PHYSICAL_PAGE_ADDR_HI4;\ 1005 type PHYSICAL_PAGE_ADDR_LO32;\ 1006 type PHYSICAL_PAGE_NUMBER_MSB;\ 1007 type PHYSICAL_PAGE_NUMBER_LSB;\ 1008 type LOGICAL_ADDR; \ 1009 type PF_LFB_REGION;\ 1010 type PF_MAX_REGION;\ 1011 type ENABLE_L1_TLB;\ 1012 type SYSTEM_ACCESS_MODE; 1013 1014 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 1015 type HUBP_VTG_SEL; \ 1016 type HUBP_CLOCK_ENABLE; \ 1017 type DPP_CLOCK_ENABLE; \ 1018 type SDPIF_FB_BASE;\ 1019 type SDPIF_FB_OFFSET;\ 1020 type SDPIF_AGP_BASE;\ 1021 type SDPIF_AGP_BOT;\ 1022 type SDPIF_AGP_TOP;\ 1023 type FB_TOP;\ 1024 type FB_BASE;\ 1025 type FB_OFFSET;\ 1026 type AGP_BASE;\ 1027 type AGP_BOT;\ 1028 type AGP_TOP;\ 1029 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 1030 type OPP_PIPE_CLOCK_EN;\ 1031 type IP_REQUEST_EN; \ 1032 type DOMAIN0_POWER_FORCEON; \ 1033 type DOMAIN0_POWER_GATE; \ 1034 type DOMAIN1_POWER_FORCEON; \ 1035 type DOMAIN1_POWER_GATE; \ 1036 type DOMAIN2_POWER_FORCEON; \ 1037 type DOMAIN2_POWER_GATE; \ 1038 type DOMAIN3_POWER_FORCEON; \ 1039 type DOMAIN3_POWER_GATE; \ 1040 type DOMAIN4_POWER_FORCEON; \ 1041 type DOMAIN4_POWER_GATE; \ 1042 type DOMAIN5_POWER_FORCEON; \ 1043 type DOMAIN5_POWER_GATE; \ 1044 type DOMAIN6_POWER_FORCEON; \ 1045 type DOMAIN6_POWER_GATE; \ 1046 type DOMAIN7_POWER_FORCEON; \ 1047 type DOMAIN7_POWER_GATE; \ 1048 type DOMAIN8_POWER_FORCEON; \ 1049 type DOMAIN8_POWER_GATE; \ 1050 type DOMAIN9_POWER_FORCEON; \ 1051 type DOMAIN9_POWER_GATE; \ 1052 type DOMAIN10_POWER_FORCEON; \ 1053 type DOMAIN10_POWER_GATE; \ 1054 type DOMAIN11_POWER_FORCEON; \ 1055 type DOMAIN11_POWER_GATE; \ 1056 type DOMAIN16_POWER_FORCEON; \ 1057 type DOMAIN16_POWER_GATE; \ 1058 type DOMAIN17_POWER_FORCEON; \ 1059 type DOMAIN17_POWER_GATE; \ 1060 type DOMAIN18_POWER_FORCEON; \ 1061 type DOMAIN18_POWER_GATE; \ 1062 type DOMAIN19_POWER_FORCEON; \ 1063 type DOMAIN19_POWER_GATE; \ 1064 type DOMAIN20_POWER_FORCEON; \ 1065 type DOMAIN20_POWER_GATE; \ 1066 type DOMAIN21_POWER_FORCEON; \ 1067 type DOMAIN21_POWER_GATE; \ 1068 type DOMAIN0_PGFSM_PWR_STATUS; \ 1069 type DOMAIN1_PGFSM_PWR_STATUS; \ 1070 type DOMAIN2_PGFSM_PWR_STATUS; \ 1071 type DOMAIN3_PGFSM_PWR_STATUS; \ 1072 type DOMAIN4_PGFSM_PWR_STATUS; \ 1073 type DOMAIN5_PGFSM_PWR_STATUS; \ 1074 type DOMAIN6_PGFSM_PWR_STATUS; \ 1075 type DOMAIN7_PGFSM_PWR_STATUS; \ 1076 type DOMAIN8_PGFSM_PWR_STATUS; \ 1077 type DOMAIN9_PGFSM_PWR_STATUS; \ 1078 type DOMAIN10_PGFSM_PWR_STATUS; \ 1079 type DOMAIN11_PGFSM_PWR_STATUS; \ 1080 type DOMAIN16_PGFSM_PWR_STATUS; \ 1081 type DOMAIN17_PGFSM_PWR_STATUS; \ 1082 type DOMAIN18_PGFSM_PWR_STATUS; \ 1083 type DOMAIN19_PGFSM_PWR_STATUS; \ 1084 type DOMAIN20_PGFSM_PWR_STATUS; \ 1085 type DOMAIN21_PGFSM_PWR_STATUS; \ 1086 type DCFCLK_GATE_DIS; \ 1087 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 1088 type VGA_TEST_ENABLE; \ 1089 type VGA_TEST_RENDER_START; \ 1090 type D1VGA_MODE_ENABLE; \ 1091 type D2VGA_MODE_ENABLE; \ 1092 type D3VGA_MODE_ENABLE; \ 1093 type D4VGA_MODE_ENABLE; \ 1094 type AZALIA_AUDIO_DTO_MODULE; \ 1095 type ODM_MEM_UNASSIGNED_PWR_MODE; \ 1096 type ODM_MEM_VBLANK_PWR_MODE; \ 1097 type DMCU_ERAM_MEM_PWR_FORCE; \ 1098 type VGA_MEM_PWR_FORCE; 1099 1100 #define HWSEQ_DCN3_REG_FIELD_LIST(type) \ 1101 type HPO_HDMISTREAMCLK_GATE_DIS; 1102 1103 #define HWSEQ_DCN301_REG_FIELD_LIST(type) \ 1104 type PANEL_BLON;\ 1105 type PANEL_DIGON;\ 1106 type PANEL_DIGON_OVRD;\ 1107 type PANEL_PWRSEQ_TARGET_STATE_R; 1108 1109 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1110 #define HWSEQ_DCN31_REG_FIELD_LIST(type) \ 1111 type DOMAIN_POWER_FORCEON;\ 1112 type DOMAIN_POWER_GATE;\ 1113 type DOMAIN_PGFSM_PWR_STATUS;\ 1114 type HPO_HDMISTREAMCLK_G_GATE_DIS; 1115 1116 #endif 1117 struct dce_hwseq_shift { 1118 HWSEQ_REG_FIELD_LIST(uint8_t) 1119 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 1120 HWSEQ_DCN3_REG_FIELD_LIST(uint8_t) 1121 HWSEQ_DCN301_REG_FIELD_LIST(uint8_t) 1122 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1123 HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) 1124 #endif 1125 }; 1126 1127 struct dce_hwseq_mask { 1128 HWSEQ_REG_FIELD_LIST(uint32_t) 1129 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 1130 HWSEQ_DCN3_REG_FIELD_LIST(uint32_t) 1131 HWSEQ_DCN301_REG_FIELD_LIST(uint32_t) 1132 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1133 HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) 1134 #endif 1135 }; 1136 1137 1138 enum blnd_mode { 1139 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 1140 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 1141 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 1142 }; 1143 1144 struct dce_hwseq; 1145 struct pipe_ctx; 1146 struct clock_source; 1147 1148 void dce_enable_fe_clock(struct dce_hwseq *hwss, 1149 unsigned int inst, bool enable); 1150 1151 void dce_pipe_control_lock(struct dc *dc, 1152 struct pipe_ctx *pipe, 1153 bool lock); 1154 1155 void dce_set_blender_mode(struct dce_hwseq *hws, 1156 unsigned int blnd_inst, enum blnd_mode mode); 1157 1158 #if defined(CONFIG_DRM_AMD_DC_SI) 1159 void dce60_pipe_control_lock(struct dc *dc, 1160 struct pipe_ctx *pipe, 1161 bool lock); 1162 #endif 1163 1164 void dce_clock_gating_power_up(struct dce_hwseq *hws, 1165 bool enable); 1166 1167 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 1168 struct clock_source *clk_src, 1169 unsigned int tg_inst); 1170 1171 bool dce_use_lut(enum surface_pixel_format format); 1172 #endif /*__DCE_HWSEQ_H__*/ 1173