1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "dc_types.h" 29 30 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 37 38 #define HWSEQ_DCEF_REG_LIST() \ 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 46 47 #define HWSEQ_BLND_REG_LIST() \ 48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 54 SRII(BLND_CONTROL, BLND, 0), \ 55 SRII(BLND_CONTROL, BLND, 1), \ 56 SRII(BLND_CONTROL, BLND, 2), \ 57 SRII(BLND_CONTROL, BLND, 3), \ 58 SRII(BLND_CONTROL, BLND, 4), \ 59 SRII(BLND_CONTROL, BLND, 5) 60 61 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ 62 SRII(PIXEL_RATE_CNTL, blk, inst), \ 63 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #define HWSEQ_DCE11_REG_LIST_BASE() \ 82 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 83 SR(DCFEV_CLOCK_CONTROL), \ 84 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 85 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 86 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 87 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 88 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 89 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 90 SRII(BLND_CONTROL, BLND, 0),\ 91 SRII(BLND_CONTROL, BLND, 1),\ 92 SR(BLNDV_CONTROL),\ 93 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 94 95 #define HWSEQ_DCE8_REG_LIST() \ 96 HWSEQ_DCEF_REG_LIST_DCE8(), \ 97 HWSEQ_BLND_REG_LIST(), \ 98 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 99 100 #define HWSEQ_DCE10_REG_LIST() \ 101 HWSEQ_DCEF_REG_LIST(), \ 102 HWSEQ_BLND_REG_LIST(), \ 103 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 104 105 #define HWSEQ_ST_REG_LIST() \ 106 HWSEQ_DCE11_REG_LIST_BASE(), \ 107 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 108 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 109 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 110 .BLND_CONTROL[2] = mmBLNDV_CONTROL 111 112 #define HWSEQ_CZ_REG_LIST() \ 113 HWSEQ_DCE11_REG_LIST_BASE(), \ 114 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 115 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 116 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 117 SRII(BLND_CONTROL, BLND, 2), \ 118 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 119 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 120 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 121 .BLND_CONTROL[3] = mmBLNDV_CONTROL 122 123 #define HWSEQ_DCE120_REG_LIST() \ 124 HWSEQ_DCE10_REG_LIST(), \ 125 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 126 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 127 SR(DCHUB_FB_LOCATION),\ 128 SR(DCHUB_AGP_BASE),\ 129 SR(DCHUB_AGP_BOT),\ 130 SR(DCHUB_AGP_TOP) 131 132 #define HWSEQ_VG20_REG_LIST() \ 133 HWSEQ_DCE120_REG_LIST(),\ 134 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 135 136 #define HWSEQ_DCE112_REG_LIST() \ 137 HWSEQ_DCE10_REG_LIST(), \ 138 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 139 HWSEQ_PHYPLL_REG_LIST(CRTC) 140 141 #define HWSEQ_DCN_REG_LIST()\ 142 SR(REFCLK_CNTL), \ 143 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 144 SR(DIO_MEM_PWR_CTRL), \ 145 SR(DCCG_GATE_DISABLE_CNTL), \ 146 SR(DCCG_GATE_DISABLE_CNTL2), \ 147 SR(DCFCLK_CNTL),\ 148 SR(DCFCLK_CNTL), \ 149 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 150 151 152 #define MMHUB_DCN_REG_LIST()\ 153 /* todo: get these from GVM instead of reading registers ourselves */\ 154 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 155 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 156 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 157 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 158 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 159 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 160 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 161 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 162 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 163 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 164 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 165 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 166 167 168 #define HWSEQ_DCN1_REG_LIST()\ 169 HWSEQ_DCN_REG_LIST(), \ 170 MMHUB_DCN_REG_LIST(), \ 171 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 172 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 173 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 174 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 175 SR(DCHUBBUB_SDPIF_FB_BASE),\ 176 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 177 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 178 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 179 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 180 SR(DOMAIN0_PG_CONFIG), \ 181 SR(DOMAIN1_PG_CONFIG), \ 182 SR(DOMAIN2_PG_CONFIG), \ 183 SR(DOMAIN3_PG_CONFIG), \ 184 SR(DOMAIN4_PG_CONFIG), \ 185 SR(DOMAIN5_PG_CONFIG), \ 186 SR(DOMAIN6_PG_CONFIG), \ 187 SR(DOMAIN7_PG_CONFIG), \ 188 SR(DOMAIN0_PG_STATUS), \ 189 SR(DOMAIN1_PG_STATUS), \ 190 SR(DOMAIN2_PG_STATUS), \ 191 SR(DOMAIN3_PG_STATUS), \ 192 SR(DOMAIN4_PG_STATUS), \ 193 SR(DOMAIN5_PG_STATUS), \ 194 SR(DOMAIN6_PG_STATUS), \ 195 SR(DOMAIN7_PG_STATUS), \ 196 SR(D1VGA_CONTROL), \ 197 SR(D2VGA_CONTROL), \ 198 SR(D3VGA_CONTROL), \ 199 SR(D4VGA_CONTROL), \ 200 SR(VGA_TEST_CONTROL), \ 201 SR(DC_IP_REQUEST_CNTL) 202 203 #define HWSEQ_DCN2_REG_LIST()\ 204 HWSEQ_DCN_REG_LIST(), \ 205 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 206 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 207 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 208 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 209 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 210 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ 211 SR(MICROSECOND_TIME_BASE_DIV), \ 212 SR(MILLISECOND_TIME_BASE_DIV), \ 213 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 214 SR(RBBMIF_TIMEOUT_DIS), \ 215 SR(RBBMIF_TIMEOUT_DIS_2), \ 216 SR(DCHUBBUB_CRC_CTRL), \ 217 SR(DPP_TOP0_DPP_CRC_CTRL), \ 218 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 219 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 220 SR(MPC_CRC_CTRL), \ 221 SR(MPC_CRC_RESULT_GB), \ 222 SR(MPC_CRC_RESULT_C), \ 223 SR(MPC_CRC_RESULT_AR), \ 224 SR(DOMAIN0_PG_CONFIG), \ 225 SR(DOMAIN1_PG_CONFIG), \ 226 SR(DOMAIN2_PG_CONFIG), \ 227 SR(DOMAIN3_PG_CONFIG), \ 228 SR(DOMAIN4_PG_CONFIG), \ 229 SR(DOMAIN5_PG_CONFIG), \ 230 SR(DOMAIN6_PG_CONFIG), \ 231 SR(DOMAIN7_PG_CONFIG), \ 232 SR(DOMAIN8_PG_CONFIG), \ 233 SR(DOMAIN9_PG_CONFIG), \ 234 /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ 235 /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ 236 SR(DOMAIN16_PG_CONFIG), \ 237 SR(DOMAIN17_PG_CONFIG), \ 238 SR(DOMAIN18_PG_CONFIG), \ 239 SR(DOMAIN19_PG_CONFIG), \ 240 SR(DOMAIN20_PG_CONFIG), \ 241 SR(DOMAIN21_PG_CONFIG), \ 242 SR(DOMAIN0_PG_STATUS), \ 243 SR(DOMAIN1_PG_STATUS), \ 244 SR(DOMAIN2_PG_STATUS), \ 245 SR(DOMAIN3_PG_STATUS), \ 246 SR(DOMAIN4_PG_STATUS), \ 247 SR(DOMAIN5_PG_STATUS), \ 248 SR(DOMAIN6_PG_STATUS), \ 249 SR(DOMAIN7_PG_STATUS), \ 250 SR(DOMAIN8_PG_STATUS), \ 251 SR(DOMAIN9_PG_STATUS), \ 252 SR(DOMAIN10_PG_STATUS), \ 253 SR(DOMAIN11_PG_STATUS), \ 254 SR(DOMAIN16_PG_STATUS), \ 255 SR(DOMAIN17_PG_STATUS), \ 256 SR(DOMAIN18_PG_STATUS), \ 257 SR(DOMAIN19_PG_STATUS), \ 258 SR(DOMAIN20_PG_STATUS), \ 259 SR(DOMAIN21_PG_STATUS), \ 260 SR(D1VGA_CONTROL), \ 261 SR(D2VGA_CONTROL), \ 262 SR(D3VGA_CONTROL), \ 263 SR(D4VGA_CONTROL), \ 264 SR(D5VGA_CONTROL), \ 265 SR(D6VGA_CONTROL), \ 266 SR(DC_IP_REQUEST_CNTL) 267 268 #define HWSEQ_DCN21_REG_LIST()\ 269 HWSEQ_DCN_REG_LIST(), \ 270 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 271 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 272 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 273 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 274 MMHUB_DCN_REG_LIST(), \ 275 SR(MICROSECOND_TIME_BASE_DIV), \ 276 SR(MILLISECOND_TIME_BASE_DIV), \ 277 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 278 SR(RBBMIF_TIMEOUT_DIS), \ 279 SR(RBBMIF_TIMEOUT_DIS_2), \ 280 SR(DCHUBBUB_CRC_CTRL), \ 281 SR(DPP_TOP0_DPP_CRC_CTRL), \ 282 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 283 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 284 SR(MPC_CRC_CTRL), \ 285 SR(MPC_CRC_RESULT_GB), \ 286 SR(MPC_CRC_RESULT_C), \ 287 SR(MPC_CRC_RESULT_AR), \ 288 SR(DOMAIN0_PG_CONFIG), \ 289 SR(DOMAIN1_PG_CONFIG), \ 290 SR(DOMAIN2_PG_CONFIG), \ 291 SR(DOMAIN3_PG_CONFIG), \ 292 SR(DOMAIN4_PG_CONFIG), \ 293 SR(DOMAIN5_PG_CONFIG), \ 294 SR(DOMAIN6_PG_CONFIG), \ 295 SR(DOMAIN7_PG_CONFIG), \ 296 SR(DOMAIN16_PG_CONFIG), \ 297 SR(DOMAIN17_PG_CONFIG), \ 298 SR(DOMAIN18_PG_CONFIG), \ 299 SR(DOMAIN0_PG_STATUS), \ 300 SR(DOMAIN1_PG_STATUS), \ 301 SR(DOMAIN2_PG_STATUS), \ 302 SR(DOMAIN3_PG_STATUS), \ 303 SR(DOMAIN4_PG_STATUS), \ 304 SR(DOMAIN5_PG_STATUS), \ 305 SR(DOMAIN6_PG_STATUS), \ 306 SR(DOMAIN7_PG_STATUS), \ 307 SR(DOMAIN16_PG_STATUS), \ 308 SR(DOMAIN17_PG_STATUS), \ 309 SR(DOMAIN18_PG_STATUS), \ 310 SR(D1VGA_CONTROL), \ 311 SR(D2VGA_CONTROL), \ 312 SR(D3VGA_CONTROL), \ 313 SR(D4VGA_CONTROL), \ 314 SR(D5VGA_CONTROL), \ 315 SR(D6VGA_CONTROL), \ 316 SR(DC_IP_REQUEST_CNTL) 317 318 struct dce_hwseq_registers { 319 uint32_t DCFE_CLOCK_CONTROL[6]; 320 uint32_t DCFEV_CLOCK_CONTROL; 321 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 322 uint32_t BLND_V_UPDATE_LOCK[6]; 323 uint32_t BLND_CONTROL[6]; 324 uint32_t BLNDV_CONTROL; 325 uint32_t CRTC_H_BLANK_START_END[6]; 326 uint32_t PIXEL_RATE_CNTL[6]; 327 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 328 /*DCHUB*/ 329 uint32_t DCHUB_FB_LOCATION; 330 uint32_t DCHUB_AGP_BASE; 331 uint32_t DCHUB_AGP_BOT; 332 uint32_t DCHUB_AGP_TOP; 333 334 uint32_t REFCLK_CNTL; 335 336 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 337 uint32_t DCHUBBUB_SDPIF_FB_BASE; 338 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 339 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 340 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 341 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 342 uint32_t DC_IP_REQUEST_CNTL; 343 uint32_t DOMAIN0_PG_CONFIG; 344 uint32_t DOMAIN1_PG_CONFIG; 345 uint32_t DOMAIN2_PG_CONFIG; 346 uint32_t DOMAIN3_PG_CONFIG; 347 uint32_t DOMAIN4_PG_CONFIG; 348 uint32_t DOMAIN5_PG_CONFIG; 349 uint32_t DOMAIN6_PG_CONFIG; 350 uint32_t DOMAIN7_PG_CONFIG; 351 uint32_t DOMAIN8_PG_CONFIG; 352 uint32_t DOMAIN9_PG_CONFIG; 353 uint32_t DOMAIN10_PG_CONFIG; 354 uint32_t DOMAIN11_PG_CONFIG; 355 uint32_t DOMAIN16_PG_CONFIG; 356 uint32_t DOMAIN17_PG_CONFIG; 357 uint32_t DOMAIN18_PG_CONFIG; 358 uint32_t DOMAIN19_PG_CONFIG; 359 uint32_t DOMAIN20_PG_CONFIG; 360 uint32_t DOMAIN21_PG_CONFIG; 361 uint32_t DOMAIN0_PG_STATUS; 362 uint32_t DOMAIN1_PG_STATUS; 363 uint32_t DOMAIN2_PG_STATUS; 364 uint32_t DOMAIN3_PG_STATUS; 365 uint32_t DOMAIN4_PG_STATUS; 366 uint32_t DOMAIN5_PG_STATUS; 367 uint32_t DOMAIN6_PG_STATUS; 368 uint32_t DOMAIN7_PG_STATUS; 369 uint32_t DOMAIN8_PG_STATUS; 370 uint32_t DOMAIN9_PG_STATUS; 371 uint32_t DOMAIN10_PG_STATUS; 372 uint32_t DOMAIN11_PG_STATUS; 373 uint32_t DOMAIN16_PG_STATUS; 374 uint32_t DOMAIN17_PG_STATUS; 375 uint32_t DOMAIN18_PG_STATUS; 376 uint32_t DOMAIN19_PG_STATUS; 377 uint32_t DOMAIN20_PG_STATUS; 378 uint32_t DOMAIN21_PG_STATUS; 379 uint32_t DIO_MEM_PWR_CTRL; 380 uint32_t DCCG_GATE_DISABLE_CNTL; 381 uint32_t DCCG_GATE_DISABLE_CNTL2; 382 uint32_t DCFCLK_CNTL; 383 uint32_t MICROSECOND_TIME_BASE_DIV; 384 uint32_t MILLISECOND_TIME_BASE_DIV; 385 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 386 uint32_t RBBMIF_TIMEOUT_DIS; 387 uint32_t RBBMIF_TIMEOUT_DIS_2; 388 uint32_t DCHUBBUB_CRC_CTRL; 389 uint32_t DPP_TOP0_DPP_CRC_CTRL; 390 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 391 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 392 uint32_t MPC_CRC_CTRL; 393 uint32_t MPC_CRC_RESULT_GB; 394 uint32_t MPC_CRC_RESULT_C; 395 uint32_t MPC_CRC_RESULT_AR; 396 uint32_t D1VGA_CONTROL; 397 uint32_t D2VGA_CONTROL; 398 uint32_t D3VGA_CONTROL; 399 uint32_t D4VGA_CONTROL; 400 uint32_t D5VGA_CONTROL; 401 uint32_t D6VGA_CONTROL; 402 uint32_t VGA_TEST_CONTROL; 403 /* MMHUB registers. read only. temporary hack */ 404 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 405 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 406 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 407 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 408 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 409 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 410 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 411 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 412 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 413 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 414 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 415 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 416 uint32_t MC_VM_XGMI_LFB_CNTL; 417 uint32_t AZALIA_AUDIO_DTO; 418 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 419 }; 420 /* set field name */ 421 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 422 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 423 424 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 425 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 426 427 428 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 429 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 430 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 431 432 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 433 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 434 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 435 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 436 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 437 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 438 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 439 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 440 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 441 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 442 443 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 444 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 445 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 446 447 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 448 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 449 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 450 451 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 452 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 453 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 454 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 455 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 456 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 457 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 458 459 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 460 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 461 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 462 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 463 464 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 465 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 466 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 467 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 468 469 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 470 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 471 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 472 473 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 474 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 475 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 476 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 477 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 478 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 479 480 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 481 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 482 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 483 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 484 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 485 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) 486 487 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 488 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 489 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 490 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 491 492 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 493 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 494 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 495 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 496 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 497 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 498 499 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 500 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 501 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 502 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 503 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 504 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 505 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 506 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 507 /* todo: get these from GVM instead of reading registers ourselves */\ 508 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 509 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 510 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 511 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 512 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 513 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 514 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 515 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 516 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 517 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 518 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 519 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 520 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 521 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 522 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 523 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 524 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 525 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 526 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 527 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 528 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 529 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 530 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 531 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 532 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 533 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 534 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 535 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 536 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 537 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 538 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 539 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 540 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 541 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 542 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 543 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 544 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 545 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 546 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 547 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 548 549 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 550 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 551 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 552 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 553 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 554 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 555 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 556 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 557 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 558 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 559 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 560 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 561 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 562 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 563 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 564 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 565 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 566 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 567 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 568 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 569 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 570 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 571 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 572 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 573 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 574 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 575 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 576 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 577 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 578 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 579 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 580 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 581 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 582 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 583 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 584 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 585 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 586 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 587 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 588 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 589 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 590 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 591 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 592 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 593 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 594 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 595 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 596 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 597 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 598 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 599 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 600 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 601 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 602 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 603 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 604 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 605 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 606 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 607 608 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ 609 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 610 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 611 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 612 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 613 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 614 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 615 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 616 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 617 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 618 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 619 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 620 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 621 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 622 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 623 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 624 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 625 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 626 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 627 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 628 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 629 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 630 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 631 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 632 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 633 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 634 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 635 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 636 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 637 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 638 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 639 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 640 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 641 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 642 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 643 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 644 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 645 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 646 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 647 648 #define HWSEQ_REG_FIELD_LIST(type) \ 649 type DCFE_CLOCK_ENABLE; \ 650 type DCFEV_CLOCK_ENABLE; \ 651 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 652 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 653 type BLND_SCL_V_UPDATE_LOCK; \ 654 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 655 type BLND_BLND_V_UPDATE_LOCK; \ 656 type BLND_V_UPDATE_LOCK_MODE; \ 657 type BLND_FEEDTHROUGH_EN; \ 658 type BLND_ALPHA_MODE; \ 659 type BLND_MODE; \ 660 type BLND_MULTIPLIED_MODE; \ 661 type DP_DTO0_ENABLE; \ 662 type PIXEL_RATE_SOURCE; \ 663 type PHYPLL_PIXEL_RATE_SOURCE; \ 664 type PIXEL_RATE_PLL_SOURCE; \ 665 /* todo: get these from GVM instead of reading registers ourselves */\ 666 type PAGE_DIRECTORY_ENTRY_HI32;\ 667 type PAGE_DIRECTORY_ENTRY_LO32;\ 668 type LOGICAL_PAGE_NUMBER_HI4;\ 669 type LOGICAL_PAGE_NUMBER_LO32;\ 670 type PHYSICAL_PAGE_ADDR_HI4;\ 671 type PHYSICAL_PAGE_ADDR_LO32;\ 672 type PHYSICAL_PAGE_NUMBER_MSB;\ 673 type PHYSICAL_PAGE_NUMBER_LSB;\ 674 type LOGICAL_ADDR; \ 675 type PF_LFB_REGION;\ 676 type PF_MAX_REGION;\ 677 type ENABLE_L1_TLB;\ 678 type SYSTEM_ACCESS_MODE; 679 680 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 681 type HUBP_VTG_SEL; \ 682 type HUBP_CLOCK_ENABLE; \ 683 type DPP_CLOCK_ENABLE; \ 684 type SDPIF_FB_BASE;\ 685 type SDPIF_FB_OFFSET;\ 686 type SDPIF_AGP_BASE;\ 687 type SDPIF_AGP_BOT;\ 688 type SDPIF_AGP_TOP;\ 689 type FB_TOP;\ 690 type FB_BASE;\ 691 type FB_OFFSET;\ 692 type AGP_BASE;\ 693 type AGP_BOT;\ 694 type AGP_TOP;\ 695 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 696 type OPP_PIPE_CLOCK_EN;\ 697 type IP_REQUEST_EN; \ 698 type DOMAIN0_POWER_FORCEON; \ 699 type DOMAIN0_POWER_GATE; \ 700 type DOMAIN1_POWER_FORCEON; \ 701 type DOMAIN1_POWER_GATE; \ 702 type DOMAIN2_POWER_FORCEON; \ 703 type DOMAIN2_POWER_GATE; \ 704 type DOMAIN3_POWER_FORCEON; \ 705 type DOMAIN3_POWER_GATE; \ 706 type DOMAIN4_POWER_FORCEON; \ 707 type DOMAIN4_POWER_GATE; \ 708 type DOMAIN5_POWER_FORCEON; \ 709 type DOMAIN5_POWER_GATE; \ 710 type DOMAIN6_POWER_FORCEON; \ 711 type DOMAIN6_POWER_GATE; \ 712 type DOMAIN7_POWER_FORCEON; \ 713 type DOMAIN7_POWER_GATE; \ 714 type DOMAIN8_POWER_FORCEON; \ 715 type DOMAIN8_POWER_GATE; \ 716 type DOMAIN9_POWER_FORCEON; \ 717 type DOMAIN9_POWER_GATE; \ 718 type DOMAIN10_POWER_FORCEON; \ 719 type DOMAIN10_POWER_GATE; \ 720 type DOMAIN11_POWER_FORCEON; \ 721 type DOMAIN11_POWER_GATE; \ 722 type DOMAIN16_POWER_FORCEON; \ 723 type DOMAIN16_POWER_GATE; \ 724 type DOMAIN17_POWER_FORCEON; \ 725 type DOMAIN17_POWER_GATE; \ 726 type DOMAIN18_POWER_FORCEON; \ 727 type DOMAIN18_POWER_GATE; \ 728 type DOMAIN19_POWER_FORCEON; \ 729 type DOMAIN19_POWER_GATE; \ 730 type DOMAIN20_POWER_FORCEON; \ 731 type DOMAIN20_POWER_GATE; \ 732 type DOMAIN21_POWER_FORCEON; \ 733 type DOMAIN21_POWER_GATE; \ 734 type DOMAIN0_PGFSM_PWR_STATUS; \ 735 type DOMAIN1_PGFSM_PWR_STATUS; \ 736 type DOMAIN2_PGFSM_PWR_STATUS; \ 737 type DOMAIN3_PGFSM_PWR_STATUS; \ 738 type DOMAIN4_PGFSM_PWR_STATUS; \ 739 type DOMAIN5_PGFSM_PWR_STATUS; \ 740 type DOMAIN6_PGFSM_PWR_STATUS; \ 741 type DOMAIN7_PGFSM_PWR_STATUS; \ 742 type DOMAIN8_PGFSM_PWR_STATUS; \ 743 type DOMAIN9_PGFSM_PWR_STATUS; \ 744 type DOMAIN10_PGFSM_PWR_STATUS; \ 745 type DOMAIN11_PGFSM_PWR_STATUS; \ 746 type DOMAIN16_PGFSM_PWR_STATUS; \ 747 type DOMAIN17_PGFSM_PWR_STATUS; \ 748 type DOMAIN18_PGFSM_PWR_STATUS; \ 749 type DOMAIN19_PGFSM_PWR_STATUS; \ 750 type DOMAIN20_PGFSM_PWR_STATUS; \ 751 type DOMAIN21_PGFSM_PWR_STATUS; \ 752 type DCFCLK_GATE_DIS; \ 753 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 754 type VGA_TEST_ENABLE; \ 755 type VGA_TEST_RENDER_START; \ 756 type D1VGA_MODE_ENABLE; \ 757 type D2VGA_MODE_ENABLE; \ 758 type D3VGA_MODE_ENABLE; \ 759 type D4VGA_MODE_ENABLE; \ 760 type AZALIA_AUDIO_DTO_MODULE; 761 762 struct dce_hwseq_shift { 763 HWSEQ_REG_FIELD_LIST(uint8_t) 764 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 765 }; 766 767 struct dce_hwseq_mask { 768 HWSEQ_REG_FIELD_LIST(uint32_t) 769 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 770 }; 771 772 773 enum blnd_mode { 774 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 775 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 776 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 777 }; 778 779 struct dce_hwseq; 780 struct pipe_ctx; 781 struct clock_source; 782 783 void dce_enable_fe_clock(struct dce_hwseq *hwss, 784 unsigned int inst, bool enable); 785 786 void dce_pipe_control_lock(struct dc *dc, 787 struct pipe_ctx *pipe, 788 bool lock); 789 790 void dce_set_blender_mode(struct dce_hwseq *hws, 791 unsigned int blnd_inst, enum blnd_mode mode); 792 793 void dce_clock_gating_power_up(struct dce_hwseq *hws, 794 bool enable); 795 796 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 797 struct clock_source *clk_src, 798 unsigned int tg_inst); 799 800 bool dce_use_lut(enum surface_pixel_format format); 801 #endif /*__DCE_HWSEQ_H__*/ 802