1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "dc_types.h" 29 30 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 37 38 #define HWSEQ_DCEF_REG_LIST() \ 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 46 47 #define HWSEQ_BLND_REG_LIST() \ 48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 54 SRII(BLND_CONTROL, BLND, 0), \ 55 SRII(BLND_CONTROL, BLND, 1), \ 56 SRII(BLND_CONTROL, BLND, 2), \ 57 SRII(BLND_CONTROL, BLND, 3), \ 58 SRII(BLND_CONTROL, BLND, 4), \ 59 SRII(BLND_CONTROL, BLND, 5) 60 61 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ 62 SRII(PIXEL_RATE_CNTL, blk, inst), \ 63 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 82 #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \ 83 SRII(PIXEL_RATE_CNTL, blk, 0), \ 84 SRII(PIXEL_RATE_CNTL, blk, 1),\ 85 SRII(PIXEL_RATE_CNTL, blk, 2),\ 86 SRII(PIXEL_RATE_CNTL, blk, 3), \ 87 SRII(PIXEL_RATE_CNTL, blk, 4), \ 88 SRII(PIXEL_RATE_CNTL, blk, 5) 89 90 #define HWSEQ_PHYPLL_REG_LIST_3(blk) \ 91 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 92 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ 93 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ 94 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 95 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 96 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 97 #endif 98 99 #define HWSEQ_DCE11_REG_LIST_BASE() \ 100 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 101 SR(DCFEV_CLOCK_CONTROL), \ 102 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 103 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 104 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 105 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 106 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 107 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 108 SRII(BLND_CONTROL, BLND, 0),\ 109 SRII(BLND_CONTROL, BLND, 1),\ 110 SR(BLNDV_CONTROL),\ 111 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 112 113 #if defined(CONFIG_DRM_AMD_DC_SI) 114 #define HWSEQ_DCE6_REG_LIST() \ 115 HWSEQ_DCEF_REG_LIST_DCE8(), \ 116 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 117 #endif 118 119 #define HWSEQ_DCE8_REG_LIST() \ 120 HWSEQ_DCEF_REG_LIST_DCE8(), \ 121 HWSEQ_BLND_REG_LIST(), \ 122 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 123 124 #define HWSEQ_DCE10_REG_LIST() \ 125 HWSEQ_DCEF_REG_LIST(), \ 126 HWSEQ_BLND_REG_LIST(), \ 127 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 128 129 #define HWSEQ_ST_REG_LIST() \ 130 HWSEQ_DCE11_REG_LIST_BASE(), \ 131 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 132 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 133 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 134 .BLND_CONTROL[2] = mmBLNDV_CONTROL 135 136 #define HWSEQ_CZ_REG_LIST() \ 137 HWSEQ_DCE11_REG_LIST_BASE(), \ 138 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 139 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 140 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 141 SRII(BLND_CONTROL, BLND, 2), \ 142 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 143 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 144 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 145 .BLND_CONTROL[3] = mmBLNDV_CONTROL 146 147 #define HWSEQ_DCE120_REG_LIST() \ 148 HWSEQ_DCE10_REG_LIST(), \ 149 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 150 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 151 SR(DCHUB_FB_LOCATION),\ 152 SR(DCHUB_AGP_BASE),\ 153 SR(DCHUB_AGP_BOT),\ 154 SR(DCHUB_AGP_TOP) 155 156 #define HWSEQ_VG20_REG_LIST() \ 157 HWSEQ_DCE120_REG_LIST(),\ 158 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 159 160 #define HWSEQ_DCE112_REG_LIST() \ 161 HWSEQ_DCE10_REG_LIST(), \ 162 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 163 HWSEQ_PHYPLL_REG_LIST(CRTC) 164 165 #define HWSEQ_DCN_REG_LIST()\ 166 SR(REFCLK_CNTL), \ 167 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 168 SR(DIO_MEM_PWR_CTRL), \ 169 SR(DCCG_GATE_DISABLE_CNTL), \ 170 SR(DCCG_GATE_DISABLE_CNTL2), \ 171 SR(DCFCLK_CNTL),\ 172 SR(DCFCLK_CNTL), \ 173 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 174 175 176 #define MMHUB_DCN_REG_LIST()\ 177 /* todo: get these from GVM instead of reading registers ourselves */\ 178 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 179 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 180 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 181 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 182 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 183 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 184 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 185 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 186 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 187 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 188 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 189 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 190 191 192 #define HWSEQ_DCN1_REG_LIST()\ 193 HWSEQ_DCN_REG_LIST(), \ 194 MMHUB_DCN_REG_LIST(), \ 195 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 196 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 197 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 198 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 199 SR(DCHUBBUB_SDPIF_FB_BASE),\ 200 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 201 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 202 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 203 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 204 SR(DOMAIN0_PG_CONFIG), \ 205 SR(DOMAIN1_PG_CONFIG), \ 206 SR(DOMAIN2_PG_CONFIG), \ 207 SR(DOMAIN3_PG_CONFIG), \ 208 SR(DOMAIN4_PG_CONFIG), \ 209 SR(DOMAIN5_PG_CONFIG), \ 210 SR(DOMAIN6_PG_CONFIG), \ 211 SR(DOMAIN7_PG_CONFIG), \ 212 SR(DOMAIN0_PG_STATUS), \ 213 SR(DOMAIN1_PG_STATUS), \ 214 SR(DOMAIN2_PG_STATUS), \ 215 SR(DOMAIN3_PG_STATUS), \ 216 SR(DOMAIN4_PG_STATUS), \ 217 SR(DOMAIN5_PG_STATUS), \ 218 SR(DOMAIN6_PG_STATUS), \ 219 SR(DOMAIN7_PG_STATUS), \ 220 SR(D1VGA_CONTROL), \ 221 SR(D2VGA_CONTROL), \ 222 SR(D3VGA_CONTROL), \ 223 SR(D4VGA_CONTROL), \ 224 SR(VGA_TEST_CONTROL), \ 225 SR(DC_IP_REQUEST_CNTL) 226 227 #define HWSEQ_DCN2_REG_LIST()\ 228 HWSEQ_DCN_REG_LIST(), \ 229 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 230 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 231 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 232 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 233 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 234 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ 235 SR(MICROSECOND_TIME_BASE_DIV), \ 236 SR(MILLISECOND_TIME_BASE_DIV), \ 237 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 238 SR(RBBMIF_TIMEOUT_DIS), \ 239 SR(RBBMIF_TIMEOUT_DIS_2), \ 240 SR(DCHUBBUB_CRC_CTRL), \ 241 SR(DPP_TOP0_DPP_CRC_CTRL), \ 242 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 243 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 244 SR(MPC_CRC_CTRL), \ 245 SR(MPC_CRC_RESULT_GB), \ 246 SR(MPC_CRC_RESULT_C), \ 247 SR(MPC_CRC_RESULT_AR), \ 248 SR(DOMAIN0_PG_CONFIG), \ 249 SR(DOMAIN1_PG_CONFIG), \ 250 SR(DOMAIN2_PG_CONFIG), \ 251 SR(DOMAIN3_PG_CONFIG), \ 252 SR(DOMAIN4_PG_CONFIG), \ 253 SR(DOMAIN5_PG_CONFIG), \ 254 SR(DOMAIN6_PG_CONFIG), \ 255 SR(DOMAIN7_PG_CONFIG), \ 256 SR(DOMAIN8_PG_CONFIG), \ 257 SR(DOMAIN9_PG_CONFIG), \ 258 /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ 259 /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ 260 SR(DOMAIN16_PG_CONFIG), \ 261 SR(DOMAIN17_PG_CONFIG), \ 262 SR(DOMAIN18_PG_CONFIG), \ 263 SR(DOMAIN19_PG_CONFIG), \ 264 SR(DOMAIN20_PG_CONFIG), \ 265 SR(DOMAIN21_PG_CONFIG), \ 266 SR(DOMAIN0_PG_STATUS), \ 267 SR(DOMAIN1_PG_STATUS), \ 268 SR(DOMAIN2_PG_STATUS), \ 269 SR(DOMAIN3_PG_STATUS), \ 270 SR(DOMAIN4_PG_STATUS), \ 271 SR(DOMAIN5_PG_STATUS), \ 272 SR(DOMAIN6_PG_STATUS), \ 273 SR(DOMAIN7_PG_STATUS), \ 274 SR(DOMAIN8_PG_STATUS), \ 275 SR(DOMAIN9_PG_STATUS), \ 276 SR(DOMAIN10_PG_STATUS), \ 277 SR(DOMAIN11_PG_STATUS), \ 278 SR(DOMAIN16_PG_STATUS), \ 279 SR(DOMAIN17_PG_STATUS), \ 280 SR(DOMAIN18_PG_STATUS), \ 281 SR(DOMAIN19_PG_STATUS), \ 282 SR(DOMAIN20_PG_STATUS), \ 283 SR(DOMAIN21_PG_STATUS), \ 284 SR(D1VGA_CONTROL), \ 285 SR(D2VGA_CONTROL), \ 286 SR(D3VGA_CONTROL), \ 287 SR(D4VGA_CONTROL), \ 288 SR(D5VGA_CONTROL), \ 289 SR(D6VGA_CONTROL), \ 290 SR(DC_IP_REQUEST_CNTL) 291 292 #define HWSEQ_DCN21_REG_LIST()\ 293 HWSEQ_DCN_REG_LIST(), \ 294 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 295 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 296 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 297 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 298 MMHUB_DCN_REG_LIST(), \ 299 SR(MICROSECOND_TIME_BASE_DIV), \ 300 SR(MILLISECOND_TIME_BASE_DIV), \ 301 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 302 SR(RBBMIF_TIMEOUT_DIS), \ 303 SR(RBBMIF_TIMEOUT_DIS_2), \ 304 SR(DCHUBBUB_CRC_CTRL), \ 305 SR(DPP_TOP0_DPP_CRC_CTRL), \ 306 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 307 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 308 SR(MPC_CRC_CTRL), \ 309 SR(MPC_CRC_RESULT_GB), \ 310 SR(MPC_CRC_RESULT_C), \ 311 SR(MPC_CRC_RESULT_AR), \ 312 SR(DOMAIN0_PG_CONFIG), \ 313 SR(DOMAIN1_PG_CONFIG), \ 314 SR(DOMAIN2_PG_CONFIG), \ 315 SR(DOMAIN3_PG_CONFIG), \ 316 SR(DOMAIN4_PG_CONFIG), \ 317 SR(DOMAIN5_PG_CONFIG), \ 318 SR(DOMAIN6_PG_CONFIG), \ 319 SR(DOMAIN7_PG_CONFIG), \ 320 SR(DOMAIN16_PG_CONFIG), \ 321 SR(DOMAIN17_PG_CONFIG), \ 322 SR(DOMAIN18_PG_CONFIG), \ 323 SR(DOMAIN0_PG_STATUS), \ 324 SR(DOMAIN1_PG_STATUS), \ 325 SR(DOMAIN2_PG_STATUS), \ 326 SR(DOMAIN3_PG_STATUS), \ 327 SR(DOMAIN4_PG_STATUS), \ 328 SR(DOMAIN5_PG_STATUS), \ 329 SR(DOMAIN6_PG_STATUS), \ 330 SR(DOMAIN7_PG_STATUS), \ 331 SR(DOMAIN16_PG_STATUS), \ 332 SR(DOMAIN17_PG_STATUS), \ 333 SR(DOMAIN18_PG_STATUS), \ 334 SR(D1VGA_CONTROL), \ 335 SR(D2VGA_CONTROL), \ 336 SR(D3VGA_CONTROL), \ 337 SR(D4VGA_CONTROL), \ 338 SR(D5VGA_CONTROL), \ 339 SR(D6VGA_CONTROL), \ 340 SR(DC_IP_REQUEST_CNTL) 341 342 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 343 #define HWSEQ_DCN30_REG_LIST()\ 344 HWSEQ_DCN2_REG_LIST(),\ 345 HWSEQ_DCN_REG_LIST(), \ 346 HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \ 347 HWSEQ_PHYPLL_REG_LIST_3(OTG), \ 348 SR(MICROSECOND_TIME_BASE_DIV), \ 349 SR(MILLISECOND_TIME_BASE_DIV), \ 350 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 351 SR(RBBMIF_TIMEOUT_DIS), \ 352 SR(RBBMIF_TIMEOUT_DIS_2), \ 353 SR(DCHUBBUB_CRC_CTRL), \ 354 SR(DPP_TOP0_DPP_CRC_CTRL), \ 355 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 356 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 357 SR(MPC_CRC_CTRL), \ 358 SR(MPC_CRC_RESULT_GB), \ 359 SR(MPC_CRC_RESULT_C), \ 360 SR(MPC_CRC_RESULT_AR), \ 361 SR(AZALIA_AUDIO_DTO), \ 362 SR(AZALIA_CONTROLLER_CLOCK_GATING) 363 #endif 364 365 #if defined(CONFIG_DRM_AMD_DC_DCN3_01) 366 #define HWSEQ_DCN301_REG_LIST()\ 367 SR(REFCLK_CNTL), \ 368 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 369 SR(DIO_MEM_PWR_CTRL), \ 370 SR(DCCG_GATE_DISABLE_CNTL), \ 371 SR(DCCG_GATE_DISABLE_CNTL2), \ 372 SR(DCFCLK_CNTL),\ 373 SR(DCFCLK_CNTL), \ 374 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 375 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 376 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 377 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 378 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 379 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 380 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 381 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 382 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 383 SR(MICROSECOND_TIME_BASE_DIV), \ 384 SR(MILLISECOND_TIME_BASE_DIV), \ 385 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 386 SR(RBBMIF_TIMEOUT_DIS), \ 387 SR(RBBMIF_TIMEOUT_DIS_2), \ 388 SR(DCHUBBUB_CRC_CTRL), \ 389 SR(DPP_TOP0_DPP_CRC_CTRL), \ 390 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 391 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 392 SR(MPC_CRC_CTRL), \ 393 SR(MPC_CRC_RESULT_GB), \ 394 SR(MPC_CRC_RESULT_C), \ 395 SR(MPC_CRC_RESULT_AR), \ 396 SR(DOMAIN0_PG_CONFIG), \ 397 SR(DOMAIN1_PG_CONFIG), \ 398 SR(DOMAIN2_PG_CONFIG), \ 399 SR(DOMAIN3_PG_CONFIG), \ 400 SR(DOMAIN4_PG_CONFIG), \ 401 SR(DOMAIN5_PG_CONFIG), \ 402 SR(DOMAIN6_PG_CONFIG), \ 403 SR(DOMAIN7_PG_CONFIG), \ 404 SR(DOMAIN16_PG_CONFIG), \ 405 SR(DOMAIN17_PG_CONFIG), \ 406 SR(DOMAIN18_PG_CONFIG), \ 407 SR(DOMAIN0_PG_STATUS), \ 408 SR(DOMAIN1_PG_STATUS), \ 409 SR(DOMAIN2_PG_STATUS), \ 410 SR(DOMAIN3_PG_STATUS), \ 411 SR(DOMAIN4_PG_STATUS), \ 412 SR(DOMAIN5_PG_STATUS), \ 413 SR(DOMAIN6_PG_STATUS), \ 414 SR(DOMAIN7_PG_STATUS), \ 415 SR(DOMAIN16_PG_STATUS), \ 416 SR(DOMAIN17_PG_STATUS), \ 417 SR(DOMAIN18_PG_STATUS), \ 418 SR(D1VGA_CONTROL), \ 419 SR(D2VGA_CONTROL), \ 420 SR(D3VGA_CONTROL), \ 421 SR(D4VGA_CONTROL), \ 422 SR(D5VGA_CONTROL), \ 423 SR(D6VGA_CONTROL), \ 424 SR(DC_IP_REQUEST_CNTL), \ 425 SR(AZALIA_AUDIO_DTO), \ 426 SR(AZALIA_CONTROLLER_CLOCK_GATING) 427 #endif 428 429 struct dce_hwseq_registers { 430 uint32_t DCFE_CLOCK_CONTROL[6]; 431 uint32_t DCFEV_CLOCK_CONTROL; 432 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 433 uint32_t BLND_V_UPDATE_LOCK[6]; 434 uint32_t BLND_CONTROL[6]; 435 uint32_t BLNDV_CONTROL; 436 uint32_t CRTC_H_BLANK_START_END[6]; 437 uint32_t PIXEL_RATE_CNTL[6]; 438 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 439 /*DCHUB*/ 440 uint32_t DCHUB_FB_LOCATION; 441 uint32_t DCHUB_AGP_BASE; 442 uint32_t DCHUB_AGP_BOT; 443 uint32_t DCHUB_AGP_TOP; 444 445 uint32_t REFCLK_CNTL; 446 447 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 448 uint32_t DCHUBBUB_SDPIF_FB_BASE; 449 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 450 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 451 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 452 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 453 uint32_t DC_IP_REQUEST_CNTL; 454 uint32_t DOMAIN0_PG_CONFIG; 455 uint32_t DOMAIN1_PG_CONFIG; 456 uint32_t DOMAIN2_PG_CONFIG; 457 uint32_t DOMAIN3_PG_CONFIG; 458 uint32_t DOMAIN4_PG_CONFIG; 459 uint32_t DOMAIN5_PG_CONFIG; 460 uint32_t DOMAIN6_PG_CONFIG; 461 uint32_t DOMAIN7_PG_CONFIG; 462 uint32_t DOMAIN8_PG_CONFIG; 463 uint32_t DOMAIN9_PG_CONFIG; 464 uint32_t DOMAIN10_PG_CONFIG; 465 uint32_t DOMAIN11_PG_CONFIG; 466 uint32_t DOMAIN16_PG_CONFIG; 467 uint32_t DOMAIN17_PG_CONFIG; 468 uint32_t DOMAIN18_PG_CONFIG; 469 uint32_t DOMAIN19_PG_CONFIG; 470 uint32_t DOMAIN20_PG_CONFIG; 471 uint32_t DOMAIN21_PG_CONFIG; 472 uint32_t DOMAIN0_PG_STATUS; 473 uint32_t DOMAIN1_PG_STATUS; 474 uint32_t DOMAIN2_PG_STATUS; 475 uint32_t DOMAIN3_PG_STATUS; 476 uint32_t DOMAIN4_PG_STATUS; 477 uint32_t DOMAIN5_PG_STATUS; 478 uint32_t DOMAIN6_PG_STATUS; 479 uint32_t DOMAIN7_PG_STATUS; 480 uint32_t DOMAIN8_PG_STATUS; 481 uint32_t DOMAIN9_PG_STATUS; 482 uint32_t DOMAIN10_PG_STATUS; 483 uint32_t DOMAIN11_PG_STATUS; 484 uint32_t DOMAIN16_PG_STATUS; 485 uint32_t DOMAIN17_PG_STATUS; 486 uint32_t DOMAIN18_PG_STATUS; 487 uint32_t DOMAIN19_PG_STATUS; 488 uint32_t DOMAIN20_PG_STATUS; 489 uint32_t DOMAIN21_PG_STATUS; 490 uint32_t DIO_MEM_PWR_CTRL; 491 uint32_t DCCG_GATE_DISABLE_CNTL; 492 uint32_t DCCG_GATE_DISABLE_CNTL2; 493 uint32_t DCFCLK_CNTL; 494 uint32_t MICROSECOND_TIME_BASE_DIV; 495 uint32_t MILLISECOND_TIME_BASE_DIV; 496 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 497 uint32_t RBBMIF_TIMEOUT_DIS; 498 uint32_t RBBMIF_TIMEOUT_DIS_2; 499 uint32_t DCHUBBUB_CRC_CTRL; 500 uint32_t DPP_TOP0_DPP_CRC_CTRL; 501 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 502 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 503 uint32_t MPC_CRC_CTRL; 504 uint32_t MPC_CRC_RESULT_GB; 505 uint32_t MPC_CRC_RESULT_C; 506 uint32_t MPC_CRC_RESULT_AR; 507 uint32_t D1VGA_CONTROL; 508 uint32_t D2VGA_CONTROL; 509 uint32_t D3VGA_CONTROL; 510 uint32_t D4VGA_CONTROL; 511 uint32_t D5VGA_CONTROL; 512 uint32_t D6VGA_CONTROL; 513 uint32_t VGA_TEST_CONTROL; 514 /* MMHUB registers. read only. temporary hack */ 515 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 516 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 517 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 518 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 519 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 520 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 521 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 522 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 523 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 524 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 525 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 526 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 527 uint32_t MC_VM_XGMI_LFB_CNTL; 528 uint32_t AZALIA_AUDIO_DTO; 529 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 530 }; 531 /* set field name */ 532 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 533 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 534 535 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 536 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 537 538 539 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 540 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 541 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 542 543 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 544 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 545 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 546 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 547 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 548 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 549 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 550 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 551 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 552 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 553 554 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 555 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 556 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 557 558 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 559 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 560 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 561 562 #if defined(CONFIG_DRM_AMD_DC_SI) 563 #define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\ 564 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 565 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 566 #endif 567 568 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 569 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 570 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 571 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 572 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 573 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 574 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 575 576 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 577 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 578 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 579 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 580 581 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 582 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 583 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 584 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 585 586 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 587 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 588 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 589 590 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 591 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 592 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 593 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 594 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 595 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 596 597 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 598 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 599 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 600 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 601 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 602 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) 603 604 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 605 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 606 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 607 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 608 609 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 610 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 611 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 612 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 613 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 614 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 615 616 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 617 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 618 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 619 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 620 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 621 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 622 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 623 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 624 /* todo: get these from GVM instead of reading registers ourselves */\ 625 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 626 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 627 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 628 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 629 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 630 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 631 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 632 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 633 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 634 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 635 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 636 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 637 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 638 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 639 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 640 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 641 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 642 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 643 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 644 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 645 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 646 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 647 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 648 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 649 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 650 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 651 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 652 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 653 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 654 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 655 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 656 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 657 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 658 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 659 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 660 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 661 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 662 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 663 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 664 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 665 666 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 667 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 668 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 669 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 670 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 671 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 672 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 673 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 674 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 675 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 676 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 677 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 678 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 679 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 680 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 681 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 682 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 683 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 684 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 685 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 686 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 687 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 688 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 689 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 690 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 691 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 692 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 693 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 694 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 695 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 696 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 697 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 698 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 699 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 700 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 701 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 702 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 703 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 704 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 705 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 706 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 707 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 708 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 709 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 710 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 711 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 712 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 713 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 714 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 715 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 716 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 717 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 718 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 719 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 720 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 721 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 722 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 723 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 724 725 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ 726 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 727 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 728 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 729 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 730 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 731 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 732 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 733 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 734 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 735 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 736 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 737 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 738 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 739 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 740 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 741 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 742 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 743 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 744 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 745 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 747 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 749 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 751 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 752 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 753 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 754 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 755 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 760 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 761 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 762 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 763 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 764 765 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 766 #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\ 767 HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \ 768 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 769 #endif 770 771 #if defined(CONFIG_DRM_AMD_DC_DCN3_01) 772 #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\ 773 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 774 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 775 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 776 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 777 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 778 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 779 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 780 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 781 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 782 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 783 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 784 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 785 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 786 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 787 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 788 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 789 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 790 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 791 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 792 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 793 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 794 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 795 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 796 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 797 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 798 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 799 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 800 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 801 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 802 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 803 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 804 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 805 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 806 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 807 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 808 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 809 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\ 810 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\ 811 HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\ 812 HWS_SF(, PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh),\ 813 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 814 #endif 815 816 #define HWSEQ_REG_FIELD_LIST(type) \ 817 type DCFE_CLOCK_ENABLE; \ 818 type DCFEV_CLOCK_ENABLE; \ 819 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 820 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 821 type BLND_SCL_V_UPDATE_LOCK; \ 822 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 823 type BLND_BLND_V_UPDATE_LOCK; \ 824 type BLND_V_UPDATE_LOCK_MODE; \ 825 type BLND_FEEDTHROUGH_EN; \ 826 type BLND_ALPHA_MODE; \ 827 type BLND_MODE; \ 828 type BLND_MULTIPLIED_MODE; \ 829 type DP_DTO0_ENABLE; \ 830 type PIXEL_RATE_SOURCE; \ 831 type PHYPLL_PIXEL_RATE_SOURCE; \ 832 type PIXEL_RATE_PLL_SOURCE; \ 833 /* todo: get these from GVM instead of reading registers ourselves */\ 834 type PAGE_DIRECTORY_ENTRY_HI32;\ 835 type PAGE_DIRECTORY_ENTRY_LO32;\ 836 type LOGICAL_PAGE_NUMBER_HI4;\ 837 type LOGICAL_PAGE_NUMBER_LO32;\ 838 type PHYSICAL_PAGE_ADDR_HI4;\ 839 type PHYSICAL_PAGE_ADDR_LO32;\ 840 type PHYSICAL_PAGE_NUMBER_MSB;\ 841 type PHYSICAL_PAGE_NUMBER_LSB;\ 842 type LOGICAL_ADDR; \ 843 type PF_LFB_REGION;\ 844 type PF_MAX_REGION;\ 845 type ENABLE_L1_TLB;\ 846 type SYSTEM_ACCESS_MODE; 847 848 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 849 type HUBP_VTG_SEL; \ 850 type HUBP_CLOCK_ENABLE; \ 851 type DPP_CLOCK_ENABLE; \ 852 type SDPIF_FB_BASE;\ 853 type SDPIF_FB_OFFSET;\ 854 type SDPIF_AGP_BASE;\ 855 type SDPIF_AGP_BOT;\ 856 type SDPIF_AGP_TOP;\ 857 type FB_TOP;\ 858 type FB_BASE;\ 859 type FB_OFFSET;\ 860 type AGP_BASE;\ 861 type AGP_BOT;\ 862 type AGP_TOP;\ 863 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 864 type OPP_PIPE_CLOCK_EN;\ 865 type IP_REQUEST_EN; \ 866 type DOMAIN0_POWER_FORCEON; \ 867 type DOMAIN0_POWER_GATE; \ 868 type DOMAIN1_POWER_FORCEON; \ 869 type DOMAIN1_POWER_GATE; \ 870 type DOMAIN2_POWER_FORCEON; \ 871 type DOMAIN2_POWER_GATE; \ 872 type DOMAIN3_POWER_FORCEON; \ 873 type DOMAIN3_POWER_GATE; \ 874 type DOMAIN4_POWER_FORCEON; \ 875 type DOMAIN4_POWER_GATE; \ 876 type DOMAIN5_POWER_FORCEON; \ 877 type DOMAIN5_POWER_GATE; \ 878 type DOMAIN6_POWER_FORCEON; \ 879 type DOMAIN6_POWER_GATE; \ 880 type DOMAIN7_POWER_FORCEON; \ 881 type DOMAIN7_POWER_GATE; \ 882 type DOMAIN8_POWER_FORCEON; \ 883 type DOMAIN8_POWER_GATE; \ 884 type DOMAIN9_POWER_FORCEON; \ 885 type DOMAIN9_POWER_GATE; \ 886 type DOMAIN10_POWER_FORCEON; \ 887 type DOMAIN10_POWER_GATE; \ 888 type DOMAIN11_POWER_FORCEON; \ 889 type DOMAIN11_POWER_GATE; \ 890 type DOMAIN16_POWER_FORCEON; \ 891 type DOMAIN16_POWER_GATE; \ 892 type DOMAIN17_POWER_FORCEON; \ 893 type DOMAIN17_POWER_GATE; \ 894 type DOMAIN18_POWER_FORCEON; \ 895 type DOMAIN18_POWER_GATE; \ 896 type DOMAIN19_POWER_FORCEON; \ 897 type DOMAIN19_POWER_GATE; \ 898 type DOMAIN20_POWER_FORCEON; \ 899 type DOMAIN20_POWER_GATE; \ 900 type DOMAIN21_POWER_FORCEON; \ 901 type DOMAIN21_POWER_GATE; \ 902 type DOMAIN0_PGFSM_PWR_STATUS; \ 903 type DOMAIN1_PGFSM_PWR_STATUS; \ 904 type DOMAIN2_PGFSM_PWR_STATUS; \ 905 type DOMAIN3_PGFSM_PWR_STATUS; \ 906 type DOMAIN4_PGFSM_PWR_STATUS; \ 907 type DOMAIN5_PGFSM_PWR_STATUS; \ 908 type DOMAIN6_PGFSM_PWR_STATUS; \ 909 type DOMAIN7_PGFSM_PWR_STATUS; \ 910 type DOMAIN8_PGFSM_PWR_STATUS; \ 911 type DOMAIN9_PGFSM_PWR_STATUS; \ 912 type DOMAIN10_PGFSM_PWR_STATUS; \ 913 type DOMAIN11_PGFSM_PWR_STATUS; \ 914 type DOMAIN16_PGFSM_PWR_STATUS; \ 915 type DOMAIN17_PGFSM_PWR_STATUS; \ 916 type DOMAIN18_PGFSM_PWR_STATUS; \ 917 type DOMAIN19_PGFSM_PWR_STATUS; \ 918 type DOMAIN20_PGFSM_PWR_STATUS; \ 919 type DOMAIN21_PGFSM_PWR_STATUS; \ 920 type DCFCLK_GATE_DIS; \ 921 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 922 type VGA_TEST_ENABLE; \ 923 type VGA_TEST_RENDER_START; \ 924 type D1VGA_MODE_ENABLE; \ 925 type D2VGA_MODE_ENABLE; \ 926 type D3VGA_MODE_ENABLE; \ 927 type D4VGA_MODE_ENABLE; \ 928 type AZALIA_AUDIO_DTO_MODULE; 929 930 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 931 #define HWSEQ_DCN3_REG_FIELD_LIST(type) \ 932 type HPO_HDMISTREAMCLK_GATE_DIS; 933 #endif 934 935 #if defined(CONFIG_DRM_AMD_DC_DCN3_01) 936 #define HWSEQ_DCN301_REG_FIELD_LIST(type) \ 937 type PANEL_BLON;\ 938 type PANEL_DIGON;\ 939 type PANEL_DIGON_OVRD;\ 940 type PANEL_PWRSEQ_TARGET_STATE_R; 941 #endif 942 943 struct dce_hwseq_shift { 944 HWSEQ_REG_FIELD_LIST(uint8_t) 945 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 946 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 947 HWSEQ_DCN3_REG_FIELD_LIST(uint8_t) 948 #endif 949 #if defined(CONFIG_DRM_AMD_DC_DCN3_01) 950 HWSEQ_DCN301_REG_FIELD_LIST(uint8_t) 951 #endif 952 }; 953 954 struct dce_hwseq_mask { 955 HWSEQ_REG_FIELD_LIST(uint32_t) 956 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 957 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 958 HWSEQ_DCN3_REG_FIELD_LIST(uint32_t) 959 #endif 960 #if defined(CONFIG_DRM_AMD_DC_DCN3_01) 961 HWSEQ_DCN301_REG_FIELD_LIST(uint32_t) 962 #endif 963 }; 964 965 966 enum blnd_mode { 967 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 968 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 969 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 970 }; 971 972 struct dce_hwseq; 973 struct pipe_ctx; 974 struct clock_source; 975 976 void dce_enable_fe_clock(struct dce_hwseq *hwss, 977 unsigned int inst, bool enable); 978 979 void dce_pipe_control_lock(struct dc *dc, 980 struct pipe_ctx *pipe, 981 bool lock); 982 983 void dce_set_blender_mode(struct dce_hwseq *hws, 984 unsigned int blnd_inst, enum blnd_mode mode); 985 986 #if defined(CONFIG_DRM_AMD_DC_SI) 987 void dce60_pipe_control_lock(struct dc *dc, 988 struct pipe_ctx *pipe, 989 bool lock); 990 #endif 991 992 void dce_clock_gating_power_up(struct dce_hwseq *hws, 993 bool enable); 994 995 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 996 struct clock_source *clk_src, 997 unsigned int tg_inst); 998 999 bool dce_use_lut(enum surface_pixel_format format); 1000 #endif /*__DCE_HWSEQ_H__*/ 1001