1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "hw_sequencer.h" 29 30 #define BL_REG_LIST()\ 31 SR(LVTMA_PWRSEQ_CNTL), \ 32 SR(LVTMA_PWRSEQ_STATE) 33 34 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 35 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 37 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 38 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 39 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 40 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 41 42 #define HWSEQ_DCEF_REG_LIST() \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 45 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 46 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 47 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 48 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 50 51 #define HWSEQ_BLND_REG_LIST() \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 54 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 55 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 56 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 57 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 58 SRII(BLND_CONTROL, BLND, 0), \ 59 SRII(BLND_CONTROL, BLND, 1), \ 60 SRII(BLND_CONTROL, BLND, 2), \ 61 SRII(BLND_CONTROL, BLND, 3), \ 62 SRII(BLND_CONTROL, BLND, 4), \ 63 SRII(BLND_CONTROL, BLND, 5) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #define HWSEQ_DCE11_REG_LIST_BASE() \ 82 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 83 SR(DCFEV_CLOCK_CONTROL), \ 84 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 85 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 86 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 87 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 88 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 89 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 90 SRII(BLND_CONTROL, BLND, 0),\ 91 SRII(BLND_CONTROL, BLND, 1),\ 92 SR(BLNDV_CONTROL),\ 93 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 94 BL_REG_LIST() 95 96 #define HWSEQ_DCE8_REG_LIST() \ 97 HWSEQ_DCEF_REG_LIST_DCE8(), \ 98 HWSEQ_BLND_REG_LIST(), \ 99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 100 BL_REG_LIST() 101 102 #define HWSEQ_DCE10_REG_LIST() \ 103 HWSEQ_DCEF_REG_LIST(), \ 104 HWSEQ_BLND_REG_LIST(), \ 105 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 106 BL_REG_LIST() 107 108 #define HWSEQ_ST_REG_LIST() \ 109 HWSEQ_DCE11_REG_LIST_BASE(), \ 110 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 111 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 112 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 113 .BLND_CONTROL[2] = mmBLNDV_CONTROL 114 115 #define HWSEQ_CZ_REG_LIST() \ 116 HWSEQ_DCE11_REG_LIST_BASE(), \ 117 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 118 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 119 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 120 SRII(BLND_CONTROL, BLND, 2), \ 121 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 122 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 123 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 124 .BLND_CONTROL[3] = mmBLNDV_CONTROL 125 126 #define HWSEQ_DCE120_REG_LIST() \ 127 HWSEQ_DCE10_REG_LIST(), \ 128 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 129 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 130 SR(DCHUB_FB_LOCATION),\ 131 SR(DCHUB_AGP_BASE),\ 132 SR(DCHUB_AGP_BOT),\ 133 SR(DCHUB_AGP_TOP), \ 134 BL_REG_LIST() 135 136 #define HWSEQ_VG20_REG_LIST() \ 137 HWSEQ_DCE120_REG_LIST(),\ 138 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 139 140 #define HWSEQ_DCE112_REG_LIST() \ 141 HWSEQ_DCE10_REG_LIST(), \ 142 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 143 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 144 BL_REG_LIST() 145 146 #define HWSEQ_DCN_REG_LIST()\ 147 SR(REFCLK_CNTL), \ 148 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 149 SR(DIO_MEM_PWR_CTRL), \ 150 SR(DCCG_GATE_DISABLE_CNTL), \ 151 SR(DCCG_GATE_DISABLE_CNTL2), \ 152 SR(DCFCLK_CNTL),\ 153 SR(DCFCLK_CNTL), \ 154 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 155 /* todo: get these from GVM instead of reading registers ourselves */\ 156 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 157 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 158 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 159 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 160 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 161 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 162 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 163 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 164 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 165 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 166 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 167 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 168 169 #define HWSEQ_DCN1_REG_LIST()\ 170 HWSEQ_DCN_REG_LIST(), \ 171 HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ 172 HWSEQ_PHYPLL_REG_LIST(OTG), \ 173 SR(DCHUBBUB_SDPIF_FB_BASE),\ 174 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 175 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 176 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 177 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 178 SR(DOMAIN0_PG_CONFIG), \ 179 SR(DOMAIN1_PG_CONFIG), \ 180 SR(DOMAIN2_PG_CONFIG), \ 181 SR(DOMAIN3_PG_CONFIG), \ 182 SR(DOMAIN4_PG_CONFIG), \ 183 SR(DOMAIN5_PG_CONFIG), \ 184 SR(DOMAIN6_PG_CONFIG), \ 185 SR(DOMAIN7_PG_CONFIG), \ 186 SR(DOMAIN0_PG_STATUS), \ 187 SR(DOMAIN1_PG_STATUS), \ 188 SR(DOMAIN2_PG_STATUS), \ 189 SR(DOMAIN3_PG_STATUS), \ 190 SR(DOMAIN4_PG_STATUS), \ 191 SR(DOMAIN5_PG_STATUS), \ 192 SR(DOMAIN6_PG_STATUS), \ 193 SR(DOMAIN7_PG_STATUS), \ 194 SR(D1VGA_CONTROL), \ 195 SR(D2VGA_CONTROL), \ 196 SR(D3VGA_CONTROL), \ 197 SR(D4VGA_CONTROL), \ 198 SR(VGA_TEST_CONTROL), \ 199 SR(DC_IP_REQUEST_CNTL), \ 200 BL_REG_LIST() 201 202 struct dce_hwseq_registers { 203 204 /* Backlight registers */ 205 uint32_t LVTMA_PWRSEQ_CNTL; 206 uint32_t LVTMA_PWRSEQ_STATE; 207 208 uint32_t DCFE_CLOCK_CONTROL[6]; 209 uint32_t DCFEV_CLOCK_CONTROL; 210 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 211 uint32_t BLND_V_UPDATE_LOCK[6]; 212 uint32_t BLND_CONTROL[6]; 213 uint32_t BLNDV_CONTROL; 214 uint32_t CRTC_H_BLANK_START_END[6]; 215 uint32_t PIXEL_RATE_CNTL[6]; 216 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 217 /*DCHUB*/ 218 uint32_t DCHUB_FB_LOCATION; 219 uint32_t DCHUB_AGP_BASE; 220 uint32_t DCHUB_AGP_BOT; 221 uint32_t DCHUB_AGP_TOP; 222 223 uint32_t REFCLK_CNTL; 224 225 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 226 uint32_t DCHUBBUB_SDPIF_FB_BASE; 227 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 228 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 229 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 230 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 231 uint32_t DC_IP_REQUEST_CNTL; 232 uint32_t DOMAIN0_PG_CONFIG; 233 uint32_t DOMAIN1_PG_CONFIG; 234 uint32_t DOMAIN2_PG_CONFIG; 235 uint32_t DOMAIN3_PG_CONFIG; 236 uint32_t DOMAIN4_PG_CONFIG; 237 uint32_t DOMAIN5_PG_CONFIG; 238 uint32_t DOMAIN6_PG_CONFIG; 239 uint32_t DOMAIN7_PG_CONFIG; 240 uint32_t DOMAIN8_PG_CONFIG; 241 uint32_t DOMAIN9_PG_CONFIG; 242 uint32_t DOMAIN10_PG_CONFIG; 243 uint32_t DOMAIN11_PG_CONFIG; 244 uint32_t DOMAIN16_PG_CONFIG; 245 uint32_t DOMAIN17_PG_CONFIG; 246 uint32_t DOMAIN18_PG_CONFIG; 247 uint32_t DOMAIN19_PG_CONFIG; 248 uint32_t DOMAIN20_PG_CONFIG; 249 uint32_t DOMAIN21_PG_CONFIG; 250 uint32_t DOMAIN0_PG_STATUS; 251 uint32_t DOMAIN1_PG_STATUS; 252 uint32_t DOMAIN2_PG_STATUS; 253 uint32_t DOMAIN3_PG_STATUS; 254 uint32_t DOMAIN4_PG_STATUS; 255 uint32_t DOMAIN5_PG_STATUS; 256 uint32_t DOMAIN6_PG_STATUS; 257 uint32_t DOMAIN7_PG_STATUS; 258 uint32_t DOMAIN8_PG_STATUS; 259 uint32_t DOMAIN9_PG_STATUS; 260 uint32_t DOMAIN10_PG_STATUS; 261 uint32_t DOMAIN11_PG_STATUS; 262 uint32_t DOMAIN16_PG_STATUS; 263 uint32_t DOMAIN17_PG_STATUS; 264 uint32_t DOMAIN18_PG_STATUS; 265 uint32_t DOMAIN19_PG_STATUS; 266 uint32_t DOMAIN20_PG_STATUS; 267 uint32_t DOMAIN21_PG_STATUS; 268 uint32_t DIO_MEM_PWR_CTRL; 269 uint32_t DCCG_GATE_DISABLE_CNTL; 270 uint32_t DCCG_GATE_DISABLE_CNTL2; 271 uint32_t DCFCLK_CNTL; 272 uint32_t MICROSECOND_TIME_BASE_DIV; 273 uint32_t MILLISECOND_TIME_BASE_DIV; 274 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 275 uint32_t RBBMIF_TIMEOUT_DIS; 276 uint32_t RBBMIF_TIMEOUT_DIS_2; 277 uint32_t DCHUBBUB_CRC_CTRL; 278 uint32_t DPP_TOP0_DPP_CRC_CTRL; 279 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 280 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 281 uint32_t MPC_CRC_CTRL; 282 uint32_t MPC_CRC_RESULT_GB; 283 uint32_t MPC_CRC_RESULT_C; 284 uint32_t MPC_CRC_RESULT_AR; 285 uint32_t D1VGA_CONTROL; 286 uint32_t D2VGA_CONTROL; 287 uint32_t D3VGA_CONTROL; 288 uint32_t D4VGA_CONTROL; 289 uint32_t D5VGA_CONTROL; 290 uint32_t D6VGA_CONTROL; 291 uint32_t VGA_TEST_CONTROL; 292 /* MMHUB registers. read only. temporary hack */ 293 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 294 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 295 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 296 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 297 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 298 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 299 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 300 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 301 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 302 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 303 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 304 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 305 uint32_t MC_VM_XGMI_LFB_CNTL; 306 uint32_t AZALIA_AUDIO_DTO; 307 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 308 }; 309 /* set field name */ 310 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 311 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 312 313 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 314 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 315 316 317 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 318 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 319 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 320 321 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 322 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 323 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 324 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 325 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 326 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 327 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 328 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 329 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 330 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 331 332 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 333 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 334 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 335 336 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 337 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 338 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 339 340 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 341 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 342 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 343 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 344 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 345 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 346 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 347 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 348 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 349 350 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 351 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 352 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 353 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ 354 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 355 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 356 357 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 358 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 359 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 360 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 361 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ 362 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ 363 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 364 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 365 366 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 367 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 368 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 369 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 370 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 371 372 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 373 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 374 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 375 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 376 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 377 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ 378 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 379 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 380 381 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 382 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 383 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 384 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 385 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 386 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ 387 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 388 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 389 390 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 391 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 392 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 393 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 394 395 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 396 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 397 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 398 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 399 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 400 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 401 402 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 403 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 404 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 405 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 406 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 407 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 408 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 409 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 410 /* todo: get these from GVM instead of reading registers ourselves */\ 411 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 412 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 413 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 414 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 415 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 416 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 417 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 418 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 419 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 420 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 421 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 422 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 423 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 424 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 425 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 426 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 427 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 428 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 429 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 430 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 431 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 432 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 433 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 434 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 435 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 436 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 437 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 438 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 439 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 440 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 441 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 442 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 443 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 444 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 445 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 446 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 447 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 448 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 449 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 450 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ 451 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 452 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \ 453 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \ 454 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 455 456 #define HWSEQ_REG_FIELD_LIST(type) \ 457 type DCFE_CLOCK_ENABLE; \ 458 type DCFEV_CLOCK_ENABLE; \ 459 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 460 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 461 type BLND_SCL_V_UPDATE_LOCK; \ 462 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 463 type BLND_BLND_V_UPDATE_LOCK; \ 464 type BLND_V_UPDATE_LOCK_MODE; \ 465 type BLND_FEEDTHROUGH_EN; \ 466 type BLND_ALPHA_MODE; \ 467 type BLND_MODE; \ 468 type BLND_MULTIPLIED_MODE; \ 469 type DP_DTO0_ENABLE; \ 470 type PIXEL_RATE_SOURCE; \ 471 type PHYPLL_PIXEL_RATE_SOURCE; \ 472 type PIXEL_RATE_PLL_SOURCE; \ 473 /* todo: get these from GVM instead of reading registers ourselves */\ 474 type PAGE_DIRECTORY_ENTRY_HI32;\ 475 type PAGE_DIRECTORY_ENTRY_LO32;\ 476 type LOGICAL_PAGE_NUMBER_HI4;\ 477 type LOGICAL_PAGE_NUMBER_LO32;\ 478 type PHYSICAL_PAGE_ADDR_HI4;\ 479 type PHYSICAL_PAGE_ADDR_LO32;\ 480 type PHYSICAL_PAGE_NUMBER_MSB;\ 481 type PHYSICAL_PAGE_NUMBER_LSB;\ 482 type LOGICAL_ADDR; \ 483 type PF_LFB_REGION;\ 484 type PF_MAX_REGION;\ 485 type ENABLE_L1_TLB;\ 486 type SYSTEM_ACCESS_MODE;\ 487 type LVTMA_BLON;\ 488 type LVTMA_PWRSEQ_TARGET_STATE_R;\ 489 type LVTMA_DIGON;\ 490 type LVTMA_DIGON_OVRD; 491 492 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 493 type HUBP_VTG_SEL; \ 494 type HUBP_CLOCK_ENABLE; \ 495 type DPP_CLOCK_ENABLE; \ 496 type SDPIF_FB_BASE;\ 497 type SDPIF_FB_OFFSET;\ 498 type SDPIF_AGP_BASE;\ 499 type SDPIF_AGP_BOT;\ 500 type SDPIF_AGP_TOP;\ 501 type FB_TOP;\ 502 type FB_BASE;\ 503 type FB_OFFSET;\ 504 type AGP_BASE;\ 505 type AGP_BOT;\ 506 type AGP_TOP;\ 507 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 508 type OPP_PIPE_CLOCK_EN;\ 509 type IP_REQUEST_EN; \ 510 type DOMAIN0_POWER_FORCEON; \ 511 type DOMAIN0_POWER_GATE; \ 512 type DOMAIN1_POWER_FORCEON; \ 513 type DOMAIN1_POWER_GATE; \ 514 type DOMAIN2_POWER_FORCEON; \ 515 type DOMAIN2_POWER_GATE; \ 516 type DOMAIN3_POWER_FORCEON; \ 517 type DOMAIN3_POWER_GATE; \ 518 type DOMAIN4_POWER_FORCEON; \ 519 type DOMAIN4_POWER_GATE; \ 520 type DOMAIN5_POWER_FORCEON; \ 521 type DOMAIN5_POWER_GATE; \ 522 type DOMAIN6_POWER_FORCEON; \ 523 type DOMAIN6_POWER_GATE; \ 524 type DOMAIN7_POWER_FORCEON; \ 525 type DOMAIN7_POWER_GATE; \ 526 type DOMAIN8_POWER_FORCEON; \ 527 type DOMAIN8_POWER_GATE; \ 528 type DOMAIN9_POWER_FORCEON; \ 529 type DOMAIN9_POWER_GATE; \ 530 type DOMAIN10_POWER_FORCEON; \ 531 type DOMAIN10_POWER_GATE; \ 532 type DOMAIN11_POWER_FORCEON; \ 533 type DOMAIN11_POWER_GATE; \ 534 type DOMAIN16_POWER_FORCEON; \ 535 type DOMAIN16_POWER_GATE; \ 536 type DOMAIN17_POWER_FORCEON; \ 537 type DOMAIN17_POWER_GATE; \ 538 type DOMAIN18_POWER_FORCEON; \ 539 type DOMAIN18_POWER_GATE; \ 540 type DOMAIN19_POWER_FORCEON; \ 541 type DOMAIN19_POWER_GATE; \ 542 type DOMAIN20_POWER_FORCEON; \ 543 type DOMAIN20_POWER_GATE; \ 544 type DOMAIN21_POWER_FORCEON; \ 545 type DOMAIN21_POWER_GATE; \ 546 type DOMAIN0_PGFSM_PWR_STATUS; \ 547 type DOMAIN1_PGFSM_PWR_STATUS; \ 548 type DOMAIN2_PGFSM_PWR_STATUS; \ 549 type DOMAIN3_PGFSM_PWR_STATUS; \ 550 type DOMAIN4_PGFSM_PWR_STATUS; \ 551 type DOMAIN5_PGFSM_PWR_STATUS; \ 552 type DOMAIN6_PGFSM_PWR_STATUS; \ 553 type DOMAIN7_PGFSM_PWR_STATUS; \ 554 type DOMAIN8_PGFSM_PWR_STATUS; \ 555 type DOMAIN9_PGFSM_PWR_STATUS; \ 556 type DOMAIN10_PGFSM_PWR_STATUS; \ 557 type DOMAIN11_PGFSM_PWR_STATUS; \ 558 type DOMAIN16_PGFSM_PWR_STATUS; \ 559 type DOMAIN17_PGFSM_PWR_STATUS; \ 560 type DOMAIN18_PGFSM_PWR_STATUS; \ 561 type DOMAIN19_PGFSM_PWR_STATUS; \ 562 type DOMAIN20_PGFSM_PWR_STATUS; \ 563 type DOMAIN21_PGFSM_PWR_STATUS; \ 564 type DCFCLK_GATE_DIS; \ 565 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 566 type VGA_TEST_ENABLE; \ 567 type VGA_TEST_RENDER_START; \ 568 type D1VGA_MODE_ENABLE; \ 569 type D2VGA_MODE_ENABLE; \ 570 type D3VGA_MODE_ENABLE; \ 571 type D4VGA_MODE_ENABLE; \ 572 type AZALIA_AUDIO_DTO_MODULE; 573 574 struct dce_hwseq_shift { 575 HWSEQ_REG_FIELD_LIST(uint8_t) 576 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 577 }; 578 579 struct dce_hwseq_mask { 580 HWSEQ_REG_FIELD_LIST(uint32_t) 581 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 582 }; 583 584 585 enum blnd_mode { 586 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 587 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 588 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 589 }; 590 591 void dce_enable_fe_clock(struct dce_hwseq *hwss, 592 unsigned int inst, bool enable); 593 594 void dce_pipe_control_lock(struct dc *dc, 595 struct pipe_ctx *pipe, 596 bool lock); 597 598 void dce_set_blender_mode(struct dce_hwseq *hws, 599 unsigned int blnd_inst, enum blnd_mode mode); 600 601 void dce_clock_gating_power_up(struct dce_hwseq *hws, 602 bool enable); 603 604 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 605 struct clock_source *clk_src, 606 unsigned int tg_inst); 607 608 bool dce_use_lut(enum surface_pixel_format format); 609 #endif /*__DCE_HWSEQ_H__*/ 610