1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "hw_sequencer.h" 29 30 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 37 38 #define HWSEQ_DCEF_REG_LIST() \ 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 46 47 #define HWSEQ_BLND_REG_LIST() \ 48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 54 SRII(BLND_CONTROL, BLND, 0), \ 55 SRII(BLND_CONTROL, BLND, 1), \ 56 SRII(BLND_CONTROL, BLND, 2), \ 57 SRII(BLND_CONTROL, BLND, 3), \ 58 SRII(BLND_CONTROL, BLND, 4), \ 59 SRII(BLND_CONTROL, BLND, 5) 60 61 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 62 SRII(PIXEL_RATE_CNTL, blk, 0), \ 63 SRII(PIXEL_RATE_CNTL, blk, 1), \ 64 SRII(PIXEL_RATE_CNTL, blk, 2), \ 65 SRII(PIXEL_RATE_CNTL, blk, 3), \ 66 SRII(PIXEL_RATE_CNTL, blk, 4), \ 67 SRII(PIXEL_RATE_CNTL, blk, 5) 68 69 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 70 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 71 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 72 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 73 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 76 77 #define HWSEQ_DCE11_REG_LIST_BASE() \ 78 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 79 SR(DCFEV_CLOCK_CONTROL), \ 80 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 81 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 82 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 83 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 84 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 85 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 86 SRII(BLND_CONTROL, BLND, 0),\ 87 SRII(BLND_CONTROL, BLND, 1),\ 88 SR(BLNDV_CONTROL),\ 89 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 90 91 #define HWSEQ_DCE8_REG_LIST() \ 92 HWSEQ_DCEF_REG_LIST_DCE8(), \ 93 HWSEQ_BLND_REG_LIST(), \ 94 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 95 96 #define HWSEQ_DCE10_REG_LIST() \ 97 HWSEQ_DCEF_REG_LIST(), \ 98 HWSEQ_BLND_REG_LIST(), \ 99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 100 101 #define HWSEQ_ST_REG_LIST() \ 102 HWSEQ_DCE11_REG_LIST_BASE(), \ 103 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 104 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 105 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 106 .BLND_CONTROL[2] = mmBLNDV_CONTROL, 107 108 #define HWSEQ_CZ_REG_LIST() \ 109 HWSEQ_DCE11_REG_LIST_BASE(), \ 110 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 111 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 112 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 113 SRII(BLND_CONTROL, BLND, 2), \ 114 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 115 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 116 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 117 .BLND_CONTROL[3] = mmBLNDV_CONTROL 118 119 #define HWSEQ_DCE120_REG_LIST() \ 120 HWSEQ_DCE10_REG_LIST(), \ 121 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 122 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 123 SR(DCHUB_FB_LOCATION),\ 124 SR(DCHUB_AGP_BASE),\ 125 SR(DCHUB_AGP_BOT),\ 126 SR(DCHUB_AGP_TOP) 127 128 #define HWSEQ_DCE112_REG_LIST() \ 129 HWSEQ_DCE10_REG_LIST(), \ 130 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 131 HWSEQ_PHYPLL_REG_LIST(CRTC) 132 133 #define HWSEQ_DCN_REG_LIST()\ 134 HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ 135 HWSEQ_PHYPLL_REG_LIST(OTG), \ 136 SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \ 137 SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \ 138 SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \ 139 SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \ 140 SRII(DCHUBP_CNTL, HUBP, 0), \ 141 SRII(DCHUBP_CNTL, HUBP, 1), \ 142 SRII(DCHUBP_CNTL, HUBP, 2), \ 143 SRII(DCHUBP_CNTL, HUBP, 3), \ 144 SRII(HUBP_CLK_CNTL, HUBP, 0), \ 145 SRII(HUBP_CLK_CNTL, HUBP, 1), \ 146 SRII(HUBP_CLK_CNTL, HUBP, 2), \ 147 SRII(HUBP_CLK_CNTL, HUBP, 3), \ 148 SRII(DPP_CONTROL, DPP_TOP, 0), \ 149 SRII(DPP_CONTROL, DPP_TOP, 1), \ 150 SRII(DPP_CONTROL, DPP_TOP, 2), \ 151 SRII(DPP_CONTROL, DPP_TOP, 3), \ 152 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \ 153 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \ 154 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \ 155 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \ 156 SR(REFCLK_CNTL), \ 157 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 158 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ 159 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ 160 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ 161 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ 162 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 163 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ 164 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ 165 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ 166 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ 167 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 168 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ 169 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ 170 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ 171 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ 172 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 173 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\ 174 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ 175 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\ 176 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ 177 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 178 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ 179 SR(DCHUBBUB_ARB_SAT_LEVEL),\ 180 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ 181 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 182 SR(DCHUBBUB_TEST_DEBUG_INDEX), \ 183 SR(DCHUBBUB_TEST_DEBUG_DATA), \ 184 SR(DC_IP_REQUEST_CNTL), \ 185 SR(DOMAIN0_PG_CONFIG), \ 186 SR(DOMAIN1_PG_CONFIG), \ 187 SR(DOMAIN2_PG_CONFIG), \ 188 SR(DOMAIN3_PG_CONFIG), \ 189 SR(DOMAIN4_PG_CONFIG), \ 190 SR(DOMAIN5_PG_CONFIG), \ 191 SR(DOMAIN6_PG_CONFIG), \ 192 SR(DOMAIN7_PG_CONFIG), \ 193 SR(DOMAIN0_PG_STATUS), \ 194 SR(DOMAIN1_PG_STATUS), \ 195 SR(DOMAIN2_PG_STATUS), \ 196 SR(DOMAIN3_PG_STATUS), \ 197 SR(DOMAIN4_PG_STATUS), \ 198 SR(DOMAIN5_PG_STATUS), \ 199 SR(DOMAIN6_PG_STATUS), \ 200 SR(DOMAIN7_PG_STATUS), \ 201 SR(DIO_MEM_PWR_CTRL), \ 202 SR(DCCG_GATE_DISABLE_CNTL), \ 203 SR(DCCG_GATE_DISABLE_CNTL2), \ 204 SR(DCFCLK_CNTL),\ 205 SR(DCFCLK_CNTL), \ 206 SR(D1VGA_CONTROL), \ 207 SR(D2VGA_CONTROL), \ 208 SR(D3VGA_CONTROL), \ 209 SR(D4VGA_CONTROL), \ 210 /* todo: get these from GVM instead of reading registers ourselves */\ 211 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 212 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 213 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 214 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 215 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 216 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 217 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 218 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 219 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 220 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 221 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 222 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 223 224 #define HWSEQ_DCN1_REG_LIST()\ 225 HWSEQ_DCN_REG_LIST(), \ 226 SR(DCHUBBUB_SDPIF_FB_TOP),\ 227 SR(DCHUBBUB_SDPIF_FB_BASE),\ 228 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 229 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 230 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 231 SR(DCHUBBUB_SDPIF_AGP_TOP) 232 233 234 struct dce_hwseq_registers { 235 uint32_t DCFE_CLOCK_CONTROL[6]; 236 uint32_t DCFEV_CLOCK_CONTROL; 237 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 238 uint32_t BLND_V_UPDATE_LOCK[6]; 239 uint32_t BLND_CONTROL[6]; 240 uint32_t BLNDV_CONTROL; 241 uint32_t CRTC_H_BLANK_START_END[6]; 242 uint32_t PIXEL_RATE_CNTL[6]; 243 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 244 /*DCHUB*/ 245 uint32_t DCHUB_FB_LOCATION; 246 uint32_t DCHUB_AGP_BASE; 247 uint32_t DCHUB_AGP_BOT; 248 uint32_t DCHUB_AGP_TOP; 249 250 uint32_t OTG_GLOBAL_SYNC_STATUS[4]; 251 uint32_t DCHUBP_CNTL[4]; 252 uint32_t HUBP_CLK_CNTL[4]; 253 uint32_t DPP_CONTROL[4]; 254 uint32_t OPP_PIPE_CONTROL[4]; 255 uint32_t REFCLK_CNTL; 256 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; 257 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; 258 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; 259 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; 260 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; 261 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; 262 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; 263 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; 264 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; 265 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; 266 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; 267 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; 268 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; 269 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; 270 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; 271 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; 272 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; 273 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; 274 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; 275 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; 276 uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; 277 uint32_t DCHUBBUB_ARB_SAT_LEVEL; 278 uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; 279 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 280 uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; 281 uint32_t DCHUBBUB_TEST_DEBUG_INDEX; 282 uint32_t DCHUBBUB_TEST_DEBUG_DATA; 283 uint32_t DCHUBBUB_SDPIF_FB_TOP; 284 uint32_t DCHUBBUB_SDPIF_FB_BASE; 285 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 286 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 287 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 288 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 289 uint32_t DC_IP_REQUEST_CNTL; 290 uint32_t DOMAIN0_PG_CONFIG; 291 uint32_t DOMAIN1_PG_CONFIG; 292 uint32_t DOMAIN2_PG_CONFIG; 293 uint32_t DOMAIN3_PG_CONFIG; 294 uint32_t DOMAIN4_PG_CONFIG; 295 uint32_t DOMAIN5_PG_CONFIG; 296 uint32_t DOMAIN6_PG_CONFIG; 297 uint32_t DOMAIN7_PG_CONFIG; 298 uint32_t DOMAIN0_PG_STATUS; 299 uint32_t DOMAIN1_PG_STATUS; 300 uint32_t DOMAIN2_PG_STATUS; 301 uint32_t DOMAIN3_PG_STATUS; 302 uint32_t DOMAIN4_PG_STATUS; 303 uint32_t DOMAIN5_PG_STATUS; 304 uint32_t DOMAIN6_PG_STATUS; 305 uint32_t DOMAIN7_PG_STATUS; 306 uint32_t DIO_MEM_PWR_CTRL; 307 uint32_t DCCG_GATE_DISABLE_CNTL; 308 uint32_t DCCG_GATE_DISABLE_CNTL2; 309 uint32_t DCFCLK_CNTL; 310 uint32_t MICROSECOND_TIME_BASE_DIV; 311 uint32_t MILLISECOND_TIME_BASE_DIV; 312 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 313 uint32_t RBBMIF_TIMEOUT_DIS; 314 uint32_t RBBMIF_TIMEOUT_DIS_2; 315 uint32_t DENTIST_DISPCLK_CNTL; 316 uint32_t DCHUBBUB_CRC_CTRL; 317 uint32_t DPP_TOP0_DPP_CRC_CTRL; 318 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 319 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 320 uint32_t MPC_CRC_CTRL; 321 uint32_t MPC_CRC_RESULT_GB; 322 uint32_t MPC_CRC_RESULT_C; 323 uint32_t MPC_CRC_RESULT_AR; 324 uint32_t D1VGA_CONTROL; 325 uint32_t D2VGA_CONTROL; 326 uint32_t D3VGA_CONTROL; 327 uint32_t D4VGA_CONTROL; 328 /* MMHUB registers. read only. temporary hack */ 329 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 330 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 331 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 332 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 333 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 334 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 335 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 336 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 337 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 338 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 339 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 340 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 341 }; 342 /* set field name */ 343 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 344 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 345 346 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 347 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 348 349 350 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 351 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 352 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 353 354 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 355 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 356 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 357 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 358 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 359 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 360 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 361 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 362 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 363 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 364 365 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 366 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 367 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 368 369 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 370 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 371 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 372 373 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 374 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 375 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 376 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 377 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 378 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 379 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 380 381 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 382 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 383 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 384 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 385 386 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 387 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 388 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 389 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 390 391 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 392 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 393 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 394 395 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 396 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 397 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 398 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 399 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 400 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 401 402 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 403 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 404 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 405 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 406 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 407 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) 408 409 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 410 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 411 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 412 HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \ 413 HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \ 414 HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \ 415 HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \ 416 HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ 417 HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\ 418 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 419 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 420 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 421 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 422 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 423 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 424 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 425 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 426 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 427 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 428 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 429 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 430 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 431 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 432 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 433 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 434 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 435 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 436 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 437 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 438 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 439 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 440 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 441 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 442 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 443 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 444 HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ 445 HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ 446 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ 447 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ 448 HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ 449 HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ 450 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh) 451 452 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 453 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 454 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 455 HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ 456 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 457 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 458 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 459 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 460 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 461 HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh), \ 462 /* todo: get these from GVM instead of reading registers ourselves */\ 463 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 464 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 465 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 466 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 467 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 468 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 469 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 470 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 471 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh) 472 473 #define HWSEQ_REG_FIELD_LIST(type) \ 474 type DCFE_CLOCK_ENABLE; \ 475 type DCFEV_CLOCK_ENABLE; \ 476 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 477 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 478 type BLND_SCL_V_UPDATE_LOCK; \ 479 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 480 type BLND_BLND_V_UPDATE_LOCK; \ 481 type BLND_V_UPDATE_LOCK_MODE; \ 482 type BLND_FEEDTHROUGH_EN; \ 483 type BLND_ALPHA_MODE; \ 484 type BLND_MODE; \ 485 type BLND_MULTIPLIED_MODE; \ 486 type DP_DTO0_ENABLE; \ 487 type PIXEL_RATE_SOURCE; \ 488 type PHYPLL_PIXEL_RATE_SOURCE; \ 489 type PIXEL_RATE_PLL_SOURCE; \ 490 /* todo: get these from GVM instead of reading registers ourselves */\ 491 type PAGE_DIRECTORY_ENTRY_HI32;\ 492 type PAGE_DIRECTORY_ENTRY_LO32;\ 493 type LOGICAL_PAGE_NUMBER_HI4;\ 494 type LOGICAL_PAGE_NUMBER_LO32;\ 495 type PHYSICAL_PAGE_ADDR_HI4;\ 496 type PHYSICAL_PAGE_ADDR_LO32;\ 497 type PHYSICAL_PAGE_NUMBER_MSB;\ 498 type PHYSICAL_PAGE_NUMBER_LSB;\ 499 type LOGICAL_ADDR; \ 500 type ENABLE_L1_TLB;\ 501 type SYSTEM_ACCESS_MODE; 502 503 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 504 type VUPDATE_NO_LOCK_EVENT_CLEAR; \ 505 type VUPDATE_NO_LOCK_EVENT_OCCURRED; \ 506 type HUBP_VTG_SEL; \ 507 type HUBP_CLOCK_ENABLE; \ 508 type DPP_CLOCK_ENABLE; \ 509 type DPPCLK_RATE_CONTROL; \ 510 type SDPIF_FB_TOP;\ 511 type SDPIF_FB_BASE;\ 512 type SDPIF_FB_OFFSET;\ 513 type SDPIF_AGP_BASE;\ 514 type SDPIF_AGP_BOT;\ 515 type SDPIF_AGP_TOP;\ 516 type FB_TOP;\ 517 type FB_BASE;\ 518 type FB_OFFSET;\ 519 type AGP_BASE;\ 520 type AGP_BOT;\ 521 type AGP_TOP;\ 522 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 523 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ 524 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ 525 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ 526 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ 527 type DCHUBBUB_ARB_SAT_LEVEL;\ 528 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ 529 type OPP_PIPE_CLOCK_EN;\ 530 type IP_REQUEST_EN; \ 531 type DOMAIN0_POWER_FORCEON; \ 532 type DOMAIN0_POWER_GATE; \ 533 type DOMAIN1_POWER_FORCEON; \ 534 type DOMAIN1_POWER_GATE; \ 535 type DOMAIN2_POWER_FORCEON; \ 536 type DOMAIN2_POWER_GATE; \ 537 type DOMAIN3_POWER_FORCEON; \ 538 type DOMAIN3_POWER_GATE; \ 539 type DOMAIN4_POWER_FORCEON; \ 540 type DOMAIN4_POWER_GATE; \ 541 type DOMAIN5_POWER_FORCEON; \ 542 type DOMAIN5_POWER_GATE; \ 543 type DOMAIN6_POWER_FORCEON; \ 544 type DOMAIN6_POWER_GATE; \ 545 type DOMAIN7_POWER_FORCEON; \ 546 type DOMAIN7_POWER_GATE; \ 547 type DOMAIN0_PGFSM_PWR_STATUS; \ 548 type DOMAIN1_PGFSM_PWR_STATUS; \ 549 type DOMAIN2_PGFSM_PWR_STATUS; \ 550 type DOMAIN3_PGFSM_PWR_STATUS; \ 551 type DOMAIN4_PGFSM_PWR_STATUS; \ 552 type DOMAIN5_PGFSM_PWR_STATUS; \ 553 type DOMAIN6_PGFSM_PWR_STATUS; \ 554 type DOMAIN7_PGFSM_PWR_STATUS; \ 555 type DCFCLK_GATE_DIS; \ 556 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 557 type DENTIST_DPPCLK_WDIVIDER; 558 559 struct dce_hwseq_shift { 560 HWSEQ_REG_FIELD_LIST(uint8_t) 561 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 562 }; 563 564 struct dce_hwseq_mask { 565 HWSEQ_REG_FIELD_LIST(uint32_t) 566 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 567 }; 568 569 570 enum blnd_mode { 571 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 572 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 573 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 574 }; 575 576 void dce_enable_fe_clock(struct dce_hwseq *hwss, 577 unsigned int inst, bool enable); 578 579 void dce_pipe_control_lock(struct dc *dc, 580 struct pipe_ctx *pipe, 581 bool lock); 582 583 void dce_set_blender_mode(struct dce_hwseq *hws, 584 unsigned int blnd_inst, enum blnd_mode mode); 585 586 void dce_clock_gating_power_up(struct dce_hwseq *hws, 587 bool enable); 588 589 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 590 struct clock_source *clk_src, 591 unsigned int tg_inst); 592 593 bool dce_use_lut(const struct dc_plane_state *plane_state); 594 #endif /*__DCE_HWSEQ_H__*/ 595