1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce_hwseq.h" 27 #include "reg_helper.h" 28 #include "hw_sequencer.h" 29 30 #define CTX \ 31 hws->ctx 32 #define REG(reg)\ 33 hws->regs->reg 34 35 #undef FN 36 #define FN(reg_name, field_name) \ 37 hws->shifts->field_name, hws->masks->field_name 38 39 void dce_enable_fe_clock(struct dce_hwseq *hws, 40 unsigned int fe_inst, bool enable) 41 { 42 REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst], 43 DCFE_CLOCK_ENABLE, enable); 44 } 45 46 void dce_pipe_control_lock(struct dce_hwseq *hws, 47 unsigned int blnd_inst, 48 enum pipe_lock_control control_mask, 49 bool lock) 50 { 51 uint32_t lock_val = lock ? 1 : 0; 52 uint32_t dcp_grph, scl, blnd, update_lock_mode; 53 54 uint32_t val = REG_GET_4(BLND_V_UPDATE_LOCK[blnd_inst], 55 BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph, 56 BLND_SCL_V_UPDATE_LOCK, &scl, 57 BLND_BLND_V_UPDATE_LOCK, &blnd, 58 BLND_V_UPDATE_LOCK_MODE, &update_lock_mode); 59 60 if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) 61 dcp_grph = lock_val; 62 63 if (control_mask & PIPE_LOCK_CONTROL_SCL) 64 scl = lock_val; 65 66 if (control_mask & PIPE_LOCK_CONTROL_BLENDER) 67 blnd = lock_val; 68 69 if (control_mask & PIPE_LOCK_CONTROL_MODE) 70 update_lock_mode = lock_val; 71 72 REG_SET_4(BLND_V_UPDATE_LOCK[blnd_inst], val, 73 BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph, 74 BLND_SCL_V_UPDATE_LOCK, scl, 75 BLND_BLND_V_UPDATE_LOCK, blnd, 76 BLND_V_UPDATE_LOCK_MODE, update_lock_mode); 77 78 if (hws->wa.blnd_crtc_trigger) 79 if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) { 80 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[blnd_inst]); 81 REG_WRITE(CRTC_H_BLANK_START_END[blnd_inst], value); 82 } 83 } 84 85 void dce_set_blender_mode(struct dce_hwseq *hws, 86 unsigned int blnd_inst, 87 enum blnd_mode mode) 88 { 89 uint32_t feedthrough = 1; 90 uint32_t blnd_mode = 0; 91 uint32_t multiplied_mode = 0; 92 uint32_t alpha_mode = 2; 93 94 switch (mode) { 95 case BLND_MODE_OTHER_PIPE: 96 feedthrough = 0; 97 blnd_mode = 1; 98 alpha_mode = 0; 99 break; 100 case BLND_MODE_BLENDING: 101 feedthrough = 0; 102 blnd_mode = 2; 103 alpha_mode = 0; 104 multiplied_mode = 1; 105 break; 106 case BLND_MODE_CURRENT_PIPE: 107 default: 108 if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) || 109 blnd_inst == 0) 110 feedthrough = 0; 111 break; 112 } 113 114 REG_UPDATE_4(BLND_CONTROL[blnd_inst], 115 BLND_FEEDTHROUGH_EN, feedthrough, 116 BLND_ALPHA_MODE, alpha_mode, 117 BLND_MODE, blnd_mode, 118 BLND_MULTIPLIED_MODE, multiplied_mode); 119 } 120 121 122 static void dce_disable_sram_shut_down(struct dce_hwseq *hws) 123 { 124 if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL)) 125 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, 126 DC_MEM_GLOBAL_PWR_REQ_DIS, 1); 127 } 128 129 static void dce_underlay_clock_enable(struct dce_hwseq *hws) 130 { 131 /* todo: why do we need this at boot? is dce_enable_fe_clock enough? */ 132 if (REG(DCFEV_CLOCK_CONTROL)) 133 REG_UPDATE(DCFEV_CLOCK_CONTROL, 134 DCFEV_CLOCK_ENABLE, 1); 135 } 136 137 static void enable_hw_base_light_sleep(void) 138 { 139 /* TODO: implement */ 140 } 141 142 static void disable_sw_manual_control_light_sleep(void) 143 { 144 /* TODO: implement */ 145 } 146 147 void dce_clock_gating_power_up(struct dce_hwseq *hws, 148 bool enable) 149 { 150 if (enable) { 151 enable_hw_base_light_sleep(); 152 disable_sw_manual_control_light_sleep(); 153 } else { 154 dce_disable_sram_shut_down(hws); 155 dce_underlay_clock_enable(hws); 156 } 157 } 158 159 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 160 struct clock_source *clk_src, 161 unsigned int tg_inst) 162 { 163 if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO || clk_src->dp_clk_src) { 164 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], 165 DP_DTO0_ENABLE, 1); 166 167 } else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) { 168 uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0; 169 170 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], 171 PHYPLL_PIXEL_RATE_SOURCE, rate_source, 172 PIXEL_RATE_PLL_SOURCE, 0); 173 174 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], 175 DP_DTO0_ENABLE, 0); 176 177 } else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) { 178 uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0; 179 180 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], 181 PIXEL_RATE_SOURCE, rate_source, 182 DP_DTO0_ENABLE, 0); 183 184 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) 185 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], 186 PIXEL_RATE_PLL_SOURCE, 1); 187 } else { 188 DC_ERR("unknown clock source"); 189 } 190 } 191