1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dce_hwseq.h"
27 #include "reg_helper.h"
28 #include "hw_sequencer.h"
29 #include "core_dc.h"
30 
31 #define CTX \
32 	hws->ctx
33 #define REG(reg)\
34 	hws->regs->reg
35 
36 #undef FN
37 #define FN(reg_name, field_name) \
38 	hws->shifts->field_name, hws->masks->field_name
39 
40 void dce_enable_fe_clock(struct dce_hwseq *hws,
41 		unsigned int fe_inst, bool enable)
42 {
43 	REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
44 			DCFE_CLOCK_ENABLE, enable);
45 }
46 
47 void dce_pipe_control_lock(struct core_dc *dc,
48 		struct pipe_ctx *pipe,
49 		bool lock)
50 {
51 	uint32_t lock_val = lock ? 1 : 0;
52 	uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
53 	struct dce_hwseq *hws = dc->hwseq;
54 
55 	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
56 			BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
57 			BLND_SCL_V_UPDATE_LOCK, &scl,
58 			BLND_BLND_V_UPDATE_LOCK, &blnd,
59 			BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
60 
61 	dcp_grph = lock_val;
62 	scl = lock_val;
63 	blnd = lock_val;
64 	update_lock_mode = lock_val;
65 
66 	REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
67 			BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
68 			BLND_SCL_V_UPDATE_LOCK, scl);
69 
70 	if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
71 		REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
72 				BLND_BLND_V_UPDATE_LOCK, blnd,
73 				BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
74 
75 	if (hws->wa.blnd_crtc_trigger) {
76 		if (!lock) {
77 			uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]);
78 			REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], value);
79 		}
80 	}
81 }
82 
83 void dce_set_blender_mode(struct dce_hwseq *hws,
84 	unsigned int blnd_inst,
85 	enum blnd_mode mode)
86 {
87 	uint32_t feedthrough = 1;
88 	uint32_t blnd_mode = 0;
89 	uint32_t multiplied_mode = 0;
90 	uint32_t alpha_mode = 2;
91 
92 	switch (mode) {
93 	case BLND_MODE_OTHER_PIPE:
94 		feedthrough = 0;
95 		blnd_mode = 1;
96 		alpha_mode = 0;
97 		break;
98 	case BLND_MODE_BLENDING:
99 		feedthrough = 0;
100 		blnd_mode = 2;
101 		alpha_mode = 0;
102 		multiplied_mode = 1;
103 		break;
104 	case BLND_MODE_CURRENT_PIPE:
105 	default:
106 		if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
107 				blnd_inst == 0)
108 			feedthrough = 0;
109 		break;
110 	}
111 
112 	REG_UPDATE(BLND_CONTROL[blnd_inst],
113 		BLND_MODE, blnd_mode);
114 
115 	if (hws->masks->BLND_ALPHA_MODE != 0) {
116 		REG_UPDATE_3(BLND_CONTROL[blnd_inst],
117 			BLND_FEEDTHROUGH_EN, feedthrough,
118 			BLND_ALPHA_MODE, alpha_mode,
119 			BLND_MULTIPLIED_MODE, multiplied_mode);
120 	}
121 }
122 
123 
124 static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
125 {
126 	if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
127 		REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
128 				DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
129 }
130 
131 static void dce_underlay_clock_enable(struct dce_hwseq *hws)
132 {
133 	/* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
134 	if (REG(DCFEV_CLOCK_CONTROL))
135 		REG_UPDATE(DCFEV_CLOCK_CONTROL,
136 				DCFEV_CLOCK_ENABLE, 1);
137 }
138 
139 static void enable_hw_base_light_sleep(void)
140 {
141 	/* TODO: implement */
142 }
143 
144 static void disable_sw_manual_control_light_sleep(void)
145 {
146 	/* TODO: implement */
147 }
148 
149 void dce_clock_gating_power_up(struct dce_hwseq *hws,
150 		bool enable)
151 {
152 	if (enable) {
153 		enable_hw_base_light_sleep();
154 		disable_sw_manual_control_light_sleep();
155 	} else {
156 		dce_disable_sram_shut_down(hws);
157 		dce_underlay_clock_enable(hws);
158 	}
159 }
160 
161 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
162 		struct clock_source *clk_src,
163 		unsigned int tg_inst)
164 {
165 	if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO || clk_src->dp_clk_src) {
166 		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
167 				DP_DTO0_ENABLE, 1);
168 
169 	} else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
170 		uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
171 
172 		REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
173 				PHYPLL_PIXEL_RATE_SOURCE, rate_source,
174 				PIXEL_RATE_PLL_SOURCE, 0);
175 
176 		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
177 				DP_DTO0_ENABLE, 0);
178 
179 	} else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
180 		uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
181 
182 		REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
183 				PIXEL_RATE_SOURCE, rate_source,
184 				DP_DTO0_ENABLE, 0);
185 
186 		if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
187 			REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
188 					PIXEL_RATE_PLL_SOURCE, 1);
189 	} else {
190 		DC_ERR("Unknown clock source. clk_src id: %d, TG_inst: %d",
191 		       clk_src->id, tg_inst);
192 	}
193 }
194