1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef _DCE_DMCU_H_ 28 #define _DCE_DMCU_H_ 29 30 #include "dmcu.h" 31 32 #define DMCU_COMMON_REG_LIST_DCE_BASE() \ 33 SR(DMCU_CTRL), \ 34 SR(DMCU_STATUS), \ 35 SR(DMCU_RAM_ACCESS_CTRL), \ 36 SR(DMCU_IRAM_WR_CTRL), \ 37 SR(DMCU_IRAM_WR_DATA), \ 38 SR(MASTER_COMM_DATA_REG1), \ 39 SR(MASTER_COMM_DATA_REG2), \ 40 SR(MASTER_COMM_DATA_REG3), \ 41 SR(MASTER_COMM_CMD_REG), \ 42 SR(MASTER_COMM_CNTL_REG), \ 43 SR(DMCU_IRAM_RD_CTRL), \ 44 SR(DMCU_IRAM_RD_DATA), \ 45 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 46 SR(SMU_INTERRUPT_CONTROL), \ 47 SR(DC_DMCU_SCRATCH) 48 49 #define DMCU_DCE110_COMMON_REG_LIST() \ 50 DMCU_COMMON_REG_LIST_DCE_BASE(), \ 51 SR(DCI_MEM_PWR_STATUS) 52 53 #define DMCU_DCN10_REG_LIST()\ 54 DMCU_COMMON_REG_LIST_DCE_BASE(), \ 55 SR(DMU_MEM_PWR_CNTL) 56 57 #define DMCU_SF(reg_name, field_name, post_fix)\ 58 .field_name = reg_name ## __ ## field_name ## post_fix 59 60 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 61 DMCU_SF(DMCU_CTRL, \ 62 DMCU_ENABLE, mask_sh), \ 63 DMCU_SF(DMCU_STATUS, \ 64 UC_IN_STOP_MODE, mask_sh), \ 65 DMCU_SF(DMCU_STATUS, \ 66 UC_IN_RESET, mask_sh), \ 67 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 68 IRAM_HOST_ACCESS_EN, mask_sh), \ 69 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 70 IRAM_WR_ADDR_AUTO_INC, mask_sh), \ 71 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 72 IRAM_RD_ADDR_AUTO_INC, mask_sh), \ 73 DMCU_SF(MASTER_COMM_CMD_REG, \ 74 MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 75 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 76 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 77 STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \ 78 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 79 STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \ 80 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 81 STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \ 82 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 83 STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \ 84 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) 85 86 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \ 87 DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 88 DMCU_SF(DCI_MEM_PWR_STATUS, \ 89 DMCU_IRAM_MEM_PWR_STATE, mask_sh) 90 91 #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ 92 DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 93 DMCU_SF(DMU_MEM_PWR_CNTL, \ 94 DMCU_IRAM_MEM_PWR_STATE, mask_sh) 95 96 #define DMCU_REG_FIELD_LIST(type) \ 97 type DMCU_IRAM_MEM_PWR_STATE; \ 98 type IRAM_HOST_ACCESS_EN; \ 99 type IRAM_WR_ADDR_AUTO_INC; \ 100 type IRAM_RD_ADDR_AUTO_INC; \ 101 type DMCU_ENABLE; \ 102 type UC_IN_STOP_MODE; \ 103 type UC_IN_RESET; \ 104 type MASTER_COMM_CMD_REG_BYTE0; \ 105 type MASTER_COMM_INTERRUPT; \ 106 type DPHY_RX_FAST_TRAINING_CAPABLE; \ 107 type DPHY_LOAD_BS_COUNT; \ 108 type STATIC_SCREEN1_INT_TO_UC_EN; \ 109 type STATIC_SCREEN2_INT_TO_UC_EN; \ 110 type STATIC_SCREEN3_INT_TO_UC_EN; \ 111 type STATIC_SCREEN4_INT_TO_UC_EN; \ 112 type DP_SEC_GSP0_LINE_NUM; \ 113 type DP_SEC_GSP0_PRIORITY; \ 114 type DC_SMU_INT_ENABLE 115 116 struct dce_dmcu_shift { 117 DMCU_REG_FIELD_LIST(uint8_t); 118 }; 119 120 struct dce_dmcu_mask { 121 DMCU_REG_FIELD_LIST(uint32_t); 122 }; 123 124 struct dce_dmcu_registers { 125 uint32_t DMCU_CTRL; 126 uint32_t DMCU_STATUS; 127 uint32_t DMCU_RAM_ACCESS_CTRL; 128 uint32_t DCI_MEM_PWR_STATUS; 129 uint32_t DMU_MEM_PWR_CNTL; 130 uint32_t DMCU_IRAM_WR_CTRL; 131 uint32_t DMCU_IRAM_WR_DATA; 132 133 uint32_t MASTER_COMM_DATA_REG1; 134 uint32_t MASTER_COMM_DATA_REG2; 135 uint32_t MASTER_COMM_DATA_REG3; 136 uint32_t MASTER_COMM_CMD_REG; 137 uint32_t MASTER_COMM_CNTL_REG; 138 uint32_t DMCU_IRAM_RD_CTRL; 139 uint32_t DMCU_IRAM_RD_DATA; 140 uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; 141 uint32_t SMU_INTERRUPT_CONTROL; 142 uint32_t DC_DMCU_SCRATCH; 143 }; 144 145 struct dce_dmcu { 146 struct dmcu base; 147 const struct dce_dmcu_registers *regs; 148 const struct dce_dmcu_shift *dmcu_shift; 149 const struct dce_dmcu_mask *dmcu_mask; 150 }; 151 152 /******************************************************************* 153 * MASTER_COMM_DATA_REG1 Bit position Data 154 * 7:0 hyst_frames[7:0] 155 * 14:8 hyst_lines[6:0] 156 * 15 RFB_UPDATE_AUTO_EN 157 * 18:16 phy_num[2:0] 158 * 21:19 dcp_sel[2:0] 159 * 22 phy_type 160 * 23 frame_cap_ind 161 * 26:24 aux_chan[2:0] 162 * 30:27 aux_repeat[3:0] 163 * 31:31 reserved[31:31] 164 ******************************************************************/ 165 union dce_dmcu_psr_config_data_reg1 { 166 struct { 167 unsigned int timehyst_frames:8; /*[7:0]*/ 168 unsigned int hyst_lines:7; /*[14:8]*/ 169 unsigned int rfb_update_auto_en:1; /*[15:15]*/ 170 unsigned int dp_port_num:3; /*[18:16]*/ 171 unsigned int dcp_sel:3; /*[21:19]*/ 172 unsigned int phy_type:1; /*[22:22]*/ 173 unsigned int frame_cap_ind:1; /*[23:23]*/ 174 unsigned int aux_chan:3; /*[26:24]*/ 175 unsigned int aux_repeat:4; /*[30:27]*/ 176 unsigned int reserved:1; /*[31:31]*/ 177 } bits; 178 unsigned int u32All; 179 }; 180 181 /******************************************************************* 182 * MASTER_COMM_DATA_REG2 183 *******************************************************************/ 184 union dce_dmcu_psr_config_data_reg2 { 185 struct { 186 unsigned int dig_fe:3; /*[2:0]*/ 187 unsigned int dig_be:3; /*[5:3]*/ 188 unsigned int skip_wait_for_pll_lock:1; /*[6:6]*/ 189 unsigned int reserved:9; /*[15:7]*/ 190 unsigned int frame_delay:8; /*[23:16]*/ 191 unsigned int smu_phy_id:4; /*[27:24]*/ 192 unsigned int num_of_controllers:4; /*[31:28]*/ 193 } bits; 194 unsigned int u32All; 195 }; 196 197 /******************************************************************* 198 * MASTER_COMM_DATA_REG3 199 *******************************************************************/ 200 union dce_dmcu_psr_config_data_reg3 { 201 struct { 202 unsigned int psr_level:16; /*[15:0]*/ 203 unsigned int link_rate:4; /*[19:16]*/ 204 unsigned int reserved:12; /*[31:20]*/ 205 } bits; 206 unsigned int u32All; 207 }; 208 209 union dce_dmcu_psr_config_data_wait_loop_reg1 { 210 struct { 211 unsigned int wait_loop:16; /* [15:0] */ 212 unsigned int reserved:16; /* [31:16] */ 213 } bits; 214 unsigned int u32; 215 }; 216 217 struct dmcu *dce_dmcu_create( 218 struct dc_context *ctx, 219 const struct dce_dmcu_registers *regs, 220 const struct dce_dmcu_shift *dmcu_shift, 221 const struct dce_dmcu_mask *dmcu_mask); 222 223 struct dmcu *dcn10_dmcu_create( 224 struct dc_context *ctx, 225 const struct dce_dmcu_registers *regs, 226 const struct dce_dmcu_shift *dmcu_shift, 227 const struct dce_dmcu_mask *dmcu_mask); 228 229 void dce_dmcu_destroy(struct dmcu **dmcu); 230 231 #endif /* _DCE_ABM_H_ */ 232