1 /*
2  * Copyright 2012-16 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #ifndef _DCE_DMCU_H_
28 #define _DCE_DMCU_H_
29 
30 #include "dmcu.h"
31 
32 #define DMCU_COMMON_REG_LIST_DCE_BASE() \
33 	SR(DMCU_CTRL), \
34 	SR(DMCU_RAM_ACCESS_CTRL), \
35 	SR(DMCU_IRAM_WR_CTRL), \
36 	SR(DMCU_IRAM_WR_DATA), \
37 	SR(MASTER_COMM_DATA_REG1), \
38 	SR(MASTER_COMM_DATA_REG2), \
39 	SR(MASTER_COMM_DATA_REG3), \
40 	SR(MASTER_COMM_CMD_REG), \
41 	SR(MASTER_COMM_CNTL_REG), \
42 	SR(DMCU_IRAM_RD_CTRL), \
43 	SR(DMCU_IRAM_RD_DATA), \
44 	SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
45 	SR(SMU_INTERRUPT_CONTROL)
46 
47 #define DMCU_DCE110_COMMON_REG_LIST() \
48 	DMCU_COMMON_REG_LIST_DCE_BASE(), \
49 	SR(DCI_MEM_PWR_STATUS)
50 
51 #define DMCU_DCN10_REG_LIST()\
52 	DMCU_COMMON_REG_LIST_DCE_BASE(), \
53 	SR(DMU_MEM_PWR_CNTL)
54 
55 #define DMCU_SF(reg_name, field_name, post_fix)\
56 	.field_name = reg_name ## __ ## field_name ## post_fix
57 
58 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
59 	DMCU_SF(DMCU_CTRL, \
60 			DMCU_ENABLE, mask_sh), \
61 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
62 			IRAM_HOST_ACCESS_EN, mask_sh), \
63 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
64 			IRAM_WR_ADDR_AUTO_INC, mask_sh), \
65 	DMCU_SF(MASTER_COMM_CMD_REG, \
66 			MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
67 	DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
68 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
69 			STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \
70 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
71 			STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \
72 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
73 			STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \
74 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
75 			STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
76 	DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
77 
78 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
79 	DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
80 	DMCU_SF(DCI_MEM_PWR_STATUS, \
81 		DMCU_IRAM_MEM_PWR_STATE, mask_sh)
82 
83 #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \
84 	DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
85 	DMCU_SF(DMU_MEM_PWR_CNTL, \
86 			DMCU_IRAM_MEM_PWR_STATE, mask_sh)
87 
88 #define DMCU_REG_FIELD_LIST(type) \
89 	type DMCU_IRAM_MEM_PWR_STATE; \
90 	type IRAM_HOST_ACCESS_EN; \
91 	type IRAM_WR_ADDR_AUTO_INC; \
92 	type DMCU_ENABLE; \
93 	type MASTER_COMM_CMD_REG_BYTE0; \
94 	type MASTER_COMM_INTERRUPT; \
95 	type DPHY_RX_FAST_TRAINING_CAPABLE; \
96 	type DPHY_LOAD_BS_COUNT; \
97 	type STATIC_SCREEN1_INT_TO_UC_EN; \
98 	type STATIC_SCREEN2_INT_TO_UC_EN; \
99 	type STATIC_SCREEN3_INT_TO_UC_EN; \
100 	type STATIC_SCREEN4_INT_TO_UC_EN; \
101 	type DP_SEC_GSP0_LINE_NUM; \
102 	type DP_SEC_GSP0_PRIORITY; \
103 	type DC_SMU_INT_ENABLE
104 
105 struct dce_dmcu_shift {
106 	DMCU_REG_FIELD_LIST(uint8_t);
107 };
108 
109 struct dce_dmcu_mask {
110 	DMCU_REG_FIELD_LIST(uint32_t);
111 };
112 
113 struct dce_dmcu_registers {
114 	uint32_t DMCU_CTRL;
115 	uint32_t DMCU_RAM_ACCESS_CTRL;
116 	uint32_t DCI_MEM_PWR_STATUS;
117 	uint32_t DMU_MEM_PWR_CNTL;
118 	uint32_t DMCU_IRAM_WR_CTRL;
119 	uint32_t DMCU_IRAM_WR_DATA;
120 
121 	uint32_t MASTER_COMM_DATA_REG1;
122 	uint32_t MASTER_COMM_DATA_REG2;
123 	uint32_t MASTER_COMM_DATA_REG3;
124 	uint32_t MASTER_COMM_CMD_REG;
125 	uint32_t MASTER_COMM_CNTL_REG;
126 	uint32_t DMCU_IRAM_RD_CTRL;
127 	uint32_t DMCU_IRAM_RD_DATA;
128 	uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
129 	uint32_t SMU_INTERRUPT_CONTROL;
130 };
131 
132 struct dce_dmcu {
133 	struct dmcu base;
134 	const struct dce_dmcu_registers *regs;
135 	const struct dce_dmcu_shift *dmcu_shift;
136 	const struct dce_dmcu_mask *dmcu_mask;
137 };
138 
139 /*******************************************************************
140  *   MASTER_COMM_DATA_REG1   Bit position    Data
141  *                           7:0	            hyst_frames[7:0]
142  *                           14:8	        hyst_lines[6:0]
143  *                           15	            RFB_UPDATE_AUTO_EN
144  *                           18:16	        phy_num[2:0]
145  *                           21:19	        dcp_sel[2:0]
146  *                           22	            phy_type
147  *                           23	            frame_cap_ind
148  *                           26:24	        aux_chan[2:0]
149  *                           30:27	        aux_repeat[3:0]
150  *                           31:31	        reserved[31:31]
151  ******************************************************************/
152 union dce_dmcu_psr_config_data_reg1 {
153 	struct {
154 		unsigned int timehyst_frames:8;    /*[7:0]*/
155 		unsigned int hyst_lines:7;         /*[14:8]*/
156 		unsigned int rfb_update_auto_en:1; /*[15:15]*/
157 		unsigned int dp_port_num:3;        /*[18:16]*/
158 		unsigned int dcp_sel:3;            /*[21:19]*/
159 		unsigned int phy_type:1;           /*[22:22]*/
160 		unsigned int frame_cap_ind:1;      /*[23:23]*/
161 		unsigned int aux_chan:3;           /*[26:24]*/
162 		unsigned int aux_repeat:4;         /*[30:27]*/
163 		unsigned int reserved:1;           /*[31:31]*/
164 	} bits;
165 	unsigned int u32All;
166 };
167 
168 /*******************************************************************
169  *   MASTER_COMM_DATA_REG2
170  *******************************************************************/
171 union dce_dmcu_psr_config_data_reg2 {
172 	struct {
173 		unsigned int dig_fe:3;                  /*[2:0]*/
174 		unsigned int dig_be:3;                  /*[5:3]*/
175 		unsigned int skip_wait_for_pll_lock:1;  /*[6:6]*/
176 		unsigned int reserved:9;                /*[15:7]*/
177 		unsigned int frame_delay:8;             /*[23:16]*/
178 		unsigned int smu_phy_id:4;              /*[27:24]*/
179 		unsigned int num_of_controllers:4;      /*[31:28]*/
180 	} bits;
181 	unsigned int u32All;
182 };
183 
184 /*******************************************************************
185  *   MASTER_COMM_DATA_REG3
186  *******************************************************************/
187 union dce_dmcu_psr_config_data_reg3 {
188 	struct {
189 		unsigned int psr_level:16;      /*[15:0]*/
190 		unsigned int link_rate:4;       /*[19:16]*/
191 		unsigned int reserved:12;       /*[31:20]*/
192 	} bits;
193 	unsigned int u32All;
194 };
195 
196 union dce_dmcu_psr_config_data_wait_loop_reg1 {
197 	struct {
198 		unsigned int wait_loop:16; /* [15:0] */
199 		unsigned int reserved:16; /* [31:16] */
200 	} bits;
201 	unsigned int u32;
202 };
203 
204 struct dmcu *dce_dmcu_create(
205 	struct dc_context *ctx,
206 	const struct dce_dmcu_registers *regs,
207 	const struct dce_dmcu_shift *dmcu_shift,
208 	const struct dce_dmcu_mask *dmcu_mask);
209 
210 struct dmcu *dcn10_dmcu_create(
211 	struct dc_context *ctx,
212 	const struct dce_dmcu_registers *regs,
213 	const struct dce_dmcu_shift *dmcu_shift,
214 	const struct dce_dmcu_mask *dmcu_mask);
215 
216 void dce_dmcu_destroy(struct dmcu **dmcu);
217 
218 #endif /* _DCE_ABM_H_ */
219