1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "link_encoder.h" 28 #include "dce_dmcu.h" 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 #include "fixed31_32.h" 32 #include "dc.h" 33 34 #define TO_DCE_DMCU(dmcu)\ 35 container_of(dmcu, struct dce_dmcu, base) 36 37 #define REG(reg) \ 38 (dmcu_dce->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 43 44 #define CTX \ 45 dmcu_dce->base.ctx 46 47 /* PSR related commands */ 48 #define PSR_ENABLE 0x20 49 #define PSR_EXIT 0x21 50 #define PSR_SET 0x23 51 #define PSR_SET_WAITLOOP 0x31 52 #define MCP_INIT_DMCU 0x88 53 #define MCP_INIT_IRAM 0x89 54 #define MCP_DMCU_VERSION 0x90 55 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 56 57 static bool dce_dmcu_init(struct dmcu *dmcu) 58 { 59 // Do nothing 60 return true; 61 } 62 63 bool dce_dmcu_load_iram(struct dmcu *dmcu, 64 unsigned int start_offset, 65 const char *src, 66 unsigned int bytes) 67 { 68 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 69 unsigned int count = 0; 70 71 /* Enable write access to IRAM */ 72 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 73 IRAM_HOST_ACCESS_EN, 1, 74 IRAM_WR_ADDR_AUTO_INC, 1); 75 76 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 77 78 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 79 80 for (count = 0; count < bytes; count++) 81 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 82 83 /* Disable write access to IRAM to allow dynamic sleep state */ 84 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 85 IRAM_HOST_ACCESS_EN, 0, 86 IRAM_WR_ADDR_AUTO_INC, 0); 87 88 return true; 89 } 90 91 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 92 { 93 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 94 95 uint32_t psr_state_offset = 0xf0; 96 97 /* Enable write access to IRAM */ 98 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 99 100 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 101 102 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 103 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 104 105 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 106 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 107 108 /* Disable write access to IRAM after finished using IRAM 109 * in order to allow dynamic sleep state 110 */ 111 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 112 } 113 114 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 115 { 116 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 117 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 118 unsigned int dmcu_wait_reg_ready_interval = 100; 119 120 unsigned int retryCount; 121 uint32_t psr_state = 0; 122 123 /* waitDMCUReadyForCmd */ 124 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 125 dmcu_wait_reg_ready_interval, 126 dmcu_max_retry_on_wait_reg_ready); 127 128 /* setDMCUParam_Cmd */ 129 if (enable) 130 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 131 PSR_ENABLE); 132 else 133 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 134 PSR_EXIT); 135 136 /* notifyDMCUMsg */ 137 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 138 if (wait == true) { 139 for (retryCount = 0; retryCount <= 100; retryCount++) { 140 dce_get_dmcu_psr_state(dmcu, &psr_state); 141 if (enable) { 142 if (psr_state != 0) 143 break; 144 } else { 145 if (psr_state == 0) 146 break; 147 } 148 udelay(10); 149 } 150 } 151 } 152 153 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 154 struct dc_link *link, 155 struct psr_context *psr_context) 156 { 157 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 158 159 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 160 unsigned int dmcu_wait_reg_ready_interval = 100; 161 162 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 163 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 164 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 165 166 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 167 psr_context->psrExitLinkTrainingRequired); 168 169 /* Enable static screen interrupts for PSR supported display */ 170 /* Disable the interrupt coming from other displays. */ 171 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 172 STATIC_SCREEN1_INT_TO_UC_EN, 0, 173 STATIC_SCREEN2_INT_TO_UC_EN, 0, 174 STATIC_SCREEN3_INT_TO_UC_EN, 0, 175 STATIC_SCREEN4_INT_TO_UC_EN, 0); 176 177 switch (psr_context->controllerId) { 178 /* Driver uses case 1 for unconfigured */ 179 case 1: 180 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 181 STATIC_SCREEN1_INT_TO_UC_EN, 1); 182 break; 183 case 2: 184 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 185 STATIC_SCREEN2_INT_TO_UC_EN, 1); 186 break; 187 case 3: 188 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 189 STATIC_SCREEN3_INT_TO_UC_EN, 1); 190 break; 191 case 4: 192 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 193 STATIC_SCREEN4_INT_TO_UC_EN, 1); 194 break; 195 case 5: 196 /* CZ/NL only has 4 CRTC!! 197 * really valid. 198 * There is no interrupt enable mask for these instances. 199 */ 200 break; 201 case 6: 202 /* CZ/NL only has 4 CRTC!! 203 * These are here because they are defined in HW regspec, 204 * but not really valid. There is no interrupt enable mask 205 * for these instances. 206 */ 207 break; 208 default: 209 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 210 STATIC_SCREEN1_INT_TO_UC_EN, 1); 211 break; 212 } 213 214 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 215 psr_context->sdpTransmitLineNumDeadline); 216 217 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) 218 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 219 220 /* waitDMCUReadyForCmd */ 221 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 222 dmcu_wait_reg_ready_interval, 223 dmcu_max_retry_on_wait_reg_ready); 224 225 /* setDMCUParam_PSRHostConfigData */ 226 masterCmdData1.u32All = 0; 227 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 228 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 229 masterCmdData1.bits.rfb_update_auto_en = 230 psr_context->rfb_update_auto_en; 231 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 232 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 233 masterCmdData1.bits.phy_type = psr_context->phyType; 234 masterCmdData1.bits.frame_cap_ind = 235 psr_context->psrFrameCaptureIndicationReq; 236 masterCmdData1.bits.aux_chan = psr_context->channel; 237 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 238 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 239 masterCmdData1.u32All); 240 241 masterCmdData2.u32All = 0; 242 masterCmdData2.bits.dig_fe = psr_context->engineId; 243 masterCmdData2.bits.dig_be = psr_context->transmitterId; 244 masterCmdData2.bits.skip_wait_for_pll_lock = 245 psr_context->skipPsrWaitForPllLock; 246 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 247 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 248 masterCmdData2.bits.num_of_controllers = 249 psr_context->numberOfControllers; 250 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 251 masterCmdData2.u32All); 252 253 masterCmdData3.u32All = 0; 254 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 255 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 256 masterCmdData3.u32All); 257 258 /* setDMCUParam_Cmd */ 259 REG_UPDATE(MASTER_COMM_CMD_REG, 260 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 261 262 /* notifyDMCUMsg */ 263 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 264 265 return true; 266 } 267 268 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 269 { 270 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 271 unsigned int dmcu_uc_reset; 272 273 /* microcontroller is not running */ 274 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 275 276 /* DMCU is not running */ 277 if (dmcu_uc_reset) 278 return false; 279 280 return true; 281 } 282 283 static void dce_psr_wait_loop( 284 struct dmcu *dmcu, 285 unsigned int wait_loop_number) 286 { 287 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 288 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 289 290 if (dmcu->cached_wait_loop_number == wait_loop_number) 291 return; 292 293 /* DMCU is not running */ 294 if (!dce_is_dmcu_initialized(dmcu)) 295 return; 296 297 /* waitDMCUReadyForCmd */ 298 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 299 300 masterCmdData1.u32 = 0; 301 masterCmdData1.bits.wait_loop = wait_loop_number; 302 dmcu->cached_wait_loop_number = wait_loop_number; 303 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 304 305 /* setDMCUParam_Cmd */ 306 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 307 308 /* notifyDMCUMsg */ 309 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 310 } 311 312 static void dce_get_psr_wait_loop( 313 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 314 { 315 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 316 return; 317 } 318 319 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 320 static void dcn10_get_dmcu_state(struct dmcu *dmcu) 321 { 322 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 323 uint32_t dmcu_state_offset = 0xf6; 324 325 /* Enable write access to IRAM */ 326 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 327 IRAM_HOST_ACCESS_EN, 1, 328 IRAM_RD_ADDR_AUTO_INC, 1); 329 330 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 331 332 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 333 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset); 334 335 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 336 dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA); 337 338 /* Disable write access to IRAM to allow dynamic sleep state */ 339 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 340 IRAM_HOST_ACCESS_EN, 0, 341 IRAM_RD_ADDR_AUTO_INC, 0); 342 } 343 344 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 345 { 346 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 347 uint32_t dmcu_version_offset = 0xf1; 348 349 /* Clear scratch */ 350 REG_WRITE(DC_DMCU_SCRATCH, 0); 351 352 /* Enable write access to IRAM */ 353 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 354 IRAM_HOST_ACCESS_EN, 1, 355 IRAM_RD_ADDR_AUTO_INC, 1); 356 357 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 358 359 /* Write address to IRAM_RD_ADDR and read from DATA register */ 360 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 361 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 362 dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 363 REG_READ(DMCU_IRAM_RD_DATA)); 364 dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA); 365 dmcu->dmcu_version.date = REG_READ(DMCU_IRAM_RD_DATA); 366 367 /* Disable write access to IRAM to allow dynamic sleep state */ 368 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 369 IRAM_HOST_ACCESS_EN, 0, 370 IRAM_RD_ADDR_AUTO_INC, 0); 371 372 /* Send MCP command message to DMCU to get version reply from FW. 373 * We expect this version should match the one in IRAM, otherwise 374 * something is wrong with DMCU and we should fail and disable UC. 375 */ 376 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 377 378 /* Set command to get DMCU version from microcontroller */ 379 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 380 MCP_DMCU_VERSION); 381 382 /* Notify microcontroller of new command */ 383 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 384 385 /* Ensure command has been executed before continuing */ 386 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 387 388 /* Somehow version does not match, so fail and return version 0 */ 389 if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH)) 390 dmcu->dmcu_version.interface_version = 0; 391 } 392 393 static bool dcn10_dmcu_init(struct dmcu *dmcu) 394 { 395 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 396 397 /* DMCU FW should populate the scratch register if running */ 398 if (REG_READ(DC_DMCU_SCRATCH) == 0) 399 return false; 400 401 /* Check state is uninitialized */ 402 dcn10_get_dmcu_state(dmcu); 403 404 /* If microcontroller is already initialized, do nothing */ 405 if (dmcu->dmcu_state == DMCU_RUNNING) 406 return true; 407 408 /* Retrieve and cache the DMCU firmware version. */ 409 dcn10_get_dmcu_version(dmcu); 410 411 /* Check interface version to confirm firmware is loaded and running */ 412 if (dmcu->dmcu_version.interface_version == 0) 413 return false; 414 415 /* Wait until microcontroller is ready to process interrupt */ 416 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 417 418 /* Set initialized ramping boundary value */ 419 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 420 421 /* Set command to initialize microcontroller */ 422 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 423 MCP_INIT_DMCU); 424 425 /* Notify microcontroller of new command */ 426 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 427 428 /* Ensure command has been executed before continuing */ 429 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 430 431 // Check state is initialized 432 dcn10_get_dmcu_state(dmcu); 433 434 // If microcontroller is not in running state, fail 435 if (dmcu->dmcu_state != DMCU_RUNNING) 436 return false; 437 438 return true; 439 } 440 441 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 442 unsigned int start_offset, 443 const char *src, 444 unsigned int bytes) 445 { 446 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 447 unsigned int count = 0; 448 449 /* If microcontroller is not running, do nothing */ 450 if (dmcu->dmcu_state != DMCU_RUNNING) 451 return false; 452 453 /* Enable write access to IRAM */ 454 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 455 IRAM_HOST_ACCESS_EN, 1, 456 IRAM_WR_ADDR_AUTO_INC, 1); 457 458 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 459 460 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 461 462 for (count = 0; count < bytes; count++) 463 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 464 465 /* Disable write access to IRAM to allow dynamic sleep state */ 466 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 467 IRAM_HOST_ACCESS_EN, 0, 468 IRAM_WR_ADDR_AUTO_INC, 0); 469 470 /* Wait until microcontroller is ready to process interrupt */ 471 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 472 473 /* Set command to signal IRAM is loaded and to initialize IRAM */ 474 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 475 MCP_INIT_IRAM); 476 477 /* Notify microcontroller of new command */ 478 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 479 480 /* Ensure command has been executed before continuing */ 481 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 482 483 return true; 484 } 485 486 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 487 { 488 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 489 490 uint32_t psr_state_offset = 0xf0; 491 492 /* If microcontroller is not running, do nothing */ 493 if (dmcu->dmcu_state != DMCU_RUNNING) 494 return; 495 496 /* Enable write access to IRAM */ 497 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 498 499 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 500 501 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 502 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 503 504 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 505 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 506 507 /* Disable write access to IRAM after finished using IRAM 508 * in order to allow dynamic sleep state 509 */ 510 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 511 } 512 513 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 514 { 515 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 516 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 517 unsigned int dmcu_wait_reg_ready_interval = 100; 518 519 unsigned int retryCount; 520 uint32_t psr_state = 0; 521 522 /* If microcontroller is not running, do nothing */ 523 if (dmcu->dmcu_state != DMCU_RUNNING) 524 return; 525 526 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 527 if (psr_state == 0 && !enable) 528 return; 529 /* waitDMCUReadyForCmd */ 530 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 531 dmcu_wait_reg_ready_interval, 532 dmcu_max_retry_on_wait_reg_ready); 533 534 /* setDMCUParam_Cmd */ 535 if (enable) 536 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 537 PSR_ENABLE); 538 else 539 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 540 PSR_EXIT); 541 542 /* notifyDMCUMsg */ 543 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 544 545 /* Below loops 1000 x 500us = 500 ms. 546 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 547 * least a few frames. Should never hit the max retry assert below. 548 */ 549 if (wait == true) { 550 for (retryCount = 0; retryCount <= 1000; retryCount++) { 551 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 552 if (enable) { 553 if (psr_state != 0) 554 break; 555 } else { 556 if (psr_state == 0) 557 break; 558 } 559 udelay(500); 560 } 561 562 /* assert if max retry hit */ 563 if (retryCount >= 1000) 564 ASSERT(0); 565 } 566 } 567 568 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 569 struct dc_link *link, 570 struct psr_context *psr_context) 571 { 572 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 573 574 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 575 unsigned int dmcu_wait_reg_ready_interval = 100; 576 577 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 578 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 579 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 580 581 /* If microcontroller is not running, do nothing */ 582 if (dmcu->dmcu_state != DMCU_RUNNING) 583 return false; 584 585 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 586 psr_context->psrExitLinkTrainingRequired); 587 588 /* Enable static screen interrupts for PSR supported display */ 589 /* Disable the interrupt coming from other displays. */ 590 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 591 STATIC_SCREEN1_INT_TO_UC_EN, 0, 592 STATIC_SCREEN2_INT_TO_UC_EN, 0, 593 STATIC_SCREEN3_INT_TO_UC_EN, 0, 594 STATIC_SCREEN4_INT_TO_UC_EN, 0); 595 596 switch (psr_context->controllerId) { 597 /* Driver uses case 1 for unconfigured */ 598 case 1: 599 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 600 STATIC_SCREEN1_INT_TO_UC_EN, 1); 601 break; 602 case 2: 603 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 604 STATIC_SCREEN2_INT_TO_UC_EN, 1); 605 break; 606 case 3: 607 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 608 STATIC_SCREEN3_INT_TO_UC_EN, 1); 609 break; 610 case 4: 611 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 612 STATIC_SCREEN4_INT_TO_UC_EN, 1); 613 break; 614 case 5: 615 /* CZ/NL only has 4 CRTC!! 616 * really valid. 617 * There is no interrupt enable mask for these instances. 618 */ 619 break; 620 case 6: 621 /* CZ/NL only has 4 CRTC!! 622 * These are here because they are defined in HW regspec, 623 * but not really valid. There is no interrupt enable mask 624 * for these instances. 625 */ 626 break; 627 default: 628 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 629 STATIC_SCREEN1_INT_TO_UC_EN, 1); 630 break; 631 } 632 633 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 634 psr_context->sdpTransmitLineNumDeadline); 635 636 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) 637 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 638 639 /* waitDMCUReadyForCmd */ 640 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 641 dmcu_wait_reg_ready_interval, 642 dmcu_max_retry_on_wait_reg_ready); 643 644 /* setDMCUParam_PSRHostConfigData */ 645 masterCmdData1.u32All = 0; 646 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 647 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 648 masterCmdData1.bits.rfb_update_auto_en = 649 psr_context->rfb_update_auto_en; 650 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 651 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 652 masterCmdData1.bits.phy_type = psr_context->phyType; 653 masterCmdData1.bits.frame_cap_ind = 654 psr_context->psrFrameCaptureIndicationReq; 655 masterCmdData1.bits.aux_chan = psr_context->channel; 656 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 657 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 658 masterCmdData1.u32All); 659 660 masterCmdData2.u32All = 0; 661 masterCmdData2.bits.dig_fe = psr_context->engineId; 662 masterCmdData2.bits.dig_be = psr_context->transmitterId; 663 masterCmdData2.bits.skip_wait_for_pll_lock = 664 psr_context->skipPsrWaitForPllLock; 665 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 666 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 667 masterCmdData2.bits.num_of_controllers = 668 psr_context->numberOfControllers; 669 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 670 masterCmdData2.u32All); 671 672 masterCmdData3.u32All = 0; 673 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 674 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 675 masterCmdData3.u32All); 676 677 /* setDMCUParam_Cmd */ 678 REG_UPDATE(MASTER_COMM_CMD_REG, 679 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 680 681 /* notifyDMCUMsg */ 682 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 683 684 /* waitDMCUReadyForCmd */ 685 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 686 687 return true; 688 } 689 690 static void dcn10_psr_wait_loop( 691 struct dmcu *dmcu, 692 unsigned int wait_loop_number) 693 { 694 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 695 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 696 697 /* If microcontroller is not running, do nothing */ 698 if (dmcu->dmcu_state != DMCU_RUNNING) 699 return; 700 701 if (wait_loop_number != 0) { 702 /* waitDMCUReadyForCmd */ 703 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 704 705 masterCmdData1.u32 = 0; 706 masterCmdData1.bits.wait_loop = wait_loop_number; 707 dmcu->cached_wait_loop_number = wait_loop_number; 708 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 709 710 /* setDMCUParam_Cmd */ 711 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 712 713 /* notifyDMCUMsg */ 714 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 715 } 716 } 717 718 static void dcn10_get_psr_wait_loop( 719 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 720 { 721 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 722 return; 723 } 724 725 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 726 { 727 /* microcontroller is not running */ 728 if (dmcu->dmcu_state != DMCU_RUNNING) 729 return false; 730 return true; 731 } 732 733 #endif 734 735 static const struct dmcu_funcs dce_funcs = { 736 .dmcu_init = dce_dmcu_init, 737 .load_iram = dce_dmcu_load_iram, 738 .set_psr_enable = dce_dmcu_set_psr_enable, 739 .setup_psr = dce_dmcu_setup_psr, 740 .get_psr_state = dce_get_dmcu_psr_state, 741 .set_psr_wait_loop = dce_psr_wait_loop, 742 .get_psr_wait_loop = dce_get_psr_wait_loop, 743 .is_dmcu_initialized = dce_is_dmcu_initialized 744 }; 745 746 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 747 static const struct dmcu_funcs dcn10_funcs = { 748 .dmcu_init = dcn10_dmcu_init, 749 .load_iram = dcn10_dmcu_load_iram, 750 .set_psr_enable = dcn10_dmcu_set_psr_enable, 751 .setup_psr = dcn10_dmcu_setup_psr, 752 .get_psr_state = dcn10_get_dmcu_psr_state, 753 .set_psr_wait_loop = dcn10_psr_wait_loop, 754 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 755 .is_dmcu_initialized = dcn10_is_dmcu_initialized 756 }; 757 #endif 758 759 static void dce_dmcu_construct( 760 struct dce_dmcu *dmcu_dce, 761 struct dc_context *ctx, 762 const struct dce_dmcu_registers *regs, 763 const struct dce_dmcu_shift *dmcu_shift, 764 const struct dce_dmcu_mask *dmcu_mask) 765 { 766 struct dmcu *base = &dmcu_dce->base; 767 768 base->ctx = ctx; 769 base->funcs = &dce_funcs; 770 base->cached_wait_loop_number = 0; 771 772 dmcu_dce->regs = regs; 773 dmcu_dce->dmcu_shift = dmcu_shift; 774 dmcu_dce->dmcu_mask = dmcu_mask; 775 } 776 777 struct dmcu *dce_dmcu_create( 778 struct dc_context *ctx, 779 const struct dce_dmcu_registers *regs, 780 const struct dce_dmcu_shift *dmcu_shift, 781 const struct dce_dmcu_mask *dmcu_mask) 782 { 783 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 784 785 if (dmcu_dce == NULL) { 786 BREAK_TO_DEBUGGER(); 787 return NULL; 788 } 789 790 dce_dmcu_construct( 791 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 792 793 dmcu_dce->base.funcs = &dce_funcs; 794 795 return &dmcu_dce->base; 796 } 797 798 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 799 struct dmcu *dcn10_dmcu_create( 800 struct dc_context *ctx, 801 const struct dce_dmcu_registers *regs, 802 const struct dce_dmcu_shift *dmcu_shift, 803 const struct dce_dmcu_mask *dmcu_mask) 804 { 805 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 806 807 if (dmcu_dce == NULL) { 808 BREAK_TO_DEBUGGER(); 809 return NULL; 810 } 811 812 dce_dmcu_construct( 813 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 814 815 dmcu_dce->base.funcs = &dcn10_funcs; 816 817 return &dmcu_dce->base; 818 } 819 #endif 820 821 void dce_dmcu_destroy(struct dmcu **dmcu) 822 { 823 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 824 825 kfree(dmcu_dce); 826 *dmcu = NULL; 827 } 828