1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "link_encoder.h" 28 #include "dce_dmcu.h" 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 #include "fixed32_32.h" 32 #include "dc.h" 33 34 #define TO_DCE_DMCU(dmcu)\ 35 container_of(dmcu, struct dce_dmcu, base) 36 37 #define REG(reg) \ 38 (dmcu_dce->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 43 44 #define CTX \ 45 dmcu_dce->base.ctx 46 47 /* PSR related commands */ 48 #define PSR_ENABLE 0x20 49 #define PSR_EXIT 0x21 50 #define PSR_SET 0x23 51 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 52 53 bool dce_dmcu_load_iram(struct dmcu *dmcu, 54 unsigned int start_offset, 55 const char *src, 56 unsigned int bytes) 57 { 58 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 59 unsigned int count = 0; 60 61 /* Enable write access to IRAM */ 62 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 63 IRAM_HOST_ACCESS_EN, 1, 64 IRAM_WR_ADDR_AUTO_INC, 1); 65 66 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 67 68 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 69 70 for (count = 0; count < bytes; count++) 71 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 72 73 /* Disable write access to IRAM to allow dynamic sleep state */ 74 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 75 IRAM_HOST_ACCESS_EN, 0, 76 IRAM_WR_ADDR_AUTO_INC, 0); 77 78 return true; 79 } 80 81 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 82 { 83 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 84 85 uint32_t psrStateOffset = 0xf0; 86 87 /* Enable write access to IRAM */ 88 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 89 90 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 91 92 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 93 REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); 94 95 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 96 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 97 98 /* Disable write access to IRAM after finished using IRAM 99 * in order to allow dynamic sleep state 100 */ 101 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 102 } 103 104 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) 105 { 106 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 107 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 108 unsigned int dmcu_wait_reg_ready_interval = 100; 109 110 unsigned int retryCount; 111 uint32_t psr_state = 0; 112 113 /* waitDMCUReadyForCmd */ 114 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 115 dmcu_wait_reg_ready_interval, 116 dmcu_max_retry_on_wait_reg_ready); 117 118 /* setDMCUParam_Cmd */ 119 if (enable) 120 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 121 PSR_ENABLE); 122 else 123 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 124 PSR_EXIT); 125 126 /* notifyDMCUMsg */ 127 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 128 129 for (retryCount = 0; retryCount <= 100; retryCount++) { 130 dce_get_dmcu_psr_state(dmcu, &psr_state); 131 if (enable) { 132 if (psr_state != 0) 133 break; 134 } else { 135 if (psr_state == 0) 136 break; 137 } 138 dm_delay_in_microseconds(dmcu->ctx, 10); 139 } 140 } 141 142 static void dce_dmcu_setup_psr(struct dmcu *dmcu, 143 struct core_link *link, 144 struct psr_context *psr_context) 145 { 146 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 147 148 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 149 unsigned int dmcu_wait_reg_ready_interval = 100; 150 151 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 152 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 153 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 154 155 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 156 psr_context->psrExitLinkTrainingRequired); 157 158 /* Enable static screen interrupts for PSR supported display */ 159 /* Disable the interrupt coming from other displays. */ 160 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 161 STATIC_SCREEN1_INT_TO_UC_EN, 0, 162 STATIC_SCREEN2_INT_TO_UC_EN, 0, 163 STATIC_SCREEN3_INT_TO_UC_EN, 0, 164 STATIC_SCREEN4_INT_TO_UC_EN, 0); 165 166 switch (psr_context->controllerId) { 167 /* Driver uses case 1 for unconfigured */ 168 case 1: 169 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 170 STATIC_SCREEN1_INT_TO_UC_EN, 1); 171 break; 172 case 2: 173 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 174 STATIC_SCREEN2_INT_TO_UC_EN, 1); 175 break; 176 case 3: 177 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 178 STATIC_SCREEN3_INT_TO_UC_EN, 1); 179 break; 180 case 4: 181 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 182 STATIC_SCREEN4_INT_TO_UC_EN, 1); 183 break; 184 case 5: 185 /* CZ/NL only has 4 CRTC!! 186 * really valid. 187 * There is no interrupt enable mask for these instances. 188 */ 189 break; 190 case 6: 191 /* CZ/NL only has 4 CRTC!! 192 * These are here because they are defined in HW regspec, 193 * but not really valid. There is no interrupt enable mask 194 * for these instances. 195 */ 196 break; 197 default: 198 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 199 STATIC_SCREEN1_INT_TO_UC_EN, 1); 200 break; 201 } 202 203 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 204 psr_context->sdpTransmitLineNumDeadline); 205 206 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) 207 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 208 209 /* waitDMCUReadyForCmd */ 210 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 211 dmcu_wait_reg_ready_interval, 212 dmcu_max_retry_on_wait_reg_ready); 213 214 /* setDMCUParam_PSRHostConfigData */ 215 masterCmdData1.u32All = 0; 216 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 217 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 218 masterCmdData1.bits.rfb_update_auto_en = 219 psr_context->rfb_update_auto_en; 220 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 221 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 222 masterCmdData1.bits.phy_type = psr_context->phyType; 223 masterCmdData1.bits.frame_cap_ind = 224 psr_context->psrFrameCaptureIndicationReq; 225 masterCmdData1.bits.aux_chan = psr_context->channel; 226 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 227 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 228 masterCmdData1.u32All); 229 230 masterCmdData2.u32All = 0; 231 masterCmdData2.bits.dig_fe = psr_context->engineId; 232 masterCmdData2.bits.dig_be = psr_context->transmitterId; 233 masterCmdData2.bits.skip_wait_for_pll_lock = 234 psr_context->skipPsrWaitForPllLock; 235 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 236 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 237 masterCmdData2.bits.num_of_controllers = 238 psr_context->numberOfControllers; 239 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 240 masterCmdData2.u32All); 241 242 masterCmdData3.u32All = 0; 243 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 244 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 245 masterCmdData3.u32All); 246 247 /* setDMCUParam_Cmd */ 248 REG_UPDATE(MASTER_COMM_CMD_REG, 249 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 250 251 /* notifyDMCUMsg */ 252 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 253 } 254 255 static const struct dmcu_funcs dce_funcs = { 256 .load_iram = dce_dmcu_load_iram, 257 .set_psr_enable = dce_dmcu_set_psr_enable, 258 .setup_psr = dce_dmcu_setup_psr, 259 }; 260 261 static void dce_dmcu_construct( 262 struct dce_dmcu *dmcu_dce, 263 struct dc_context *ctx, 264 const struct dce_dmcu_registers *regs, 265 const struct dce_dmcu_shift *dmcu_shift, 266 const struct dce_dmcu_mask *dmcu_mask) 267 { 268 struct dmcu *base = &dmcu_dce->base; 269 270 base->ctx = ctx; 271 base->funcs = &dce_funcs; 272 273 dmcu_dce->regs = regs; 274 dmcu_dce->dmcu_shift = dmcu_shift; 275 dmcu_dce->dmcu_mask = dmcu_mask; 276 } 277 278 struct dmcu *dce_dmcu_create( 279 struct dc_context *ctx, 280 const struct dce_dmcu_registers *regs, 281 const struct dce_dmcu_shift *dmcu_shift, 282 const struct dce_dmcu_mask *dmcu_mask) 283 { 284 struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); 285 286 if (dmcu_dce == NULL) { 287 BREAK_TO_DEBUGGER(); 288 return NULL; 289 } 290 291 dce_dmcu_construct( 292 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 293 294 dmcu_dce->base.funcs = &dce_funcs; 295 296 return &dmcu_dce->base; 297 } 298 299 void dce_dmcu_destroy(struct dmcu **dmcu) 300 { 301 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 302 303 dm_free(dmcu_dce); 304 *dmcu = NULL; 305 } 306