1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "core_types.h" 30 #include "link_encoder.h" 31 #include "dce_dmcu.h" 32 #include "dm_services.h" 33 #include "reg_helper.h" 34 #include "fixed31_32.h" 35 #include "dc.h" 36 37 #define TO_DCE_DMCU(dmcu)\ 38 container_of(dmcu, struct dce_dmcu, base) 39 40 #define REG(reg) \ 41 (dmcu_dce->regs->reg) 42 43 #undef FN 44 #define FN(reg_name, field_name) \ 45 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 46 47 #define CTX \ 48 dmcu_dce->base.ctx 49 50 /* PSR related commands */ 51 #define PSR_ENABLE 0x20 52 #define PSR_EXIT 0x21 53 #define PSR_SET 0x23 54 #define PSR_SET_WAITLOOP 0x31 55 #define MCP_INIT_DMCU 0x88 56 #define MCP_INIT_IRAM 0x89 57 #define MCP_SYNC_PHY_LOCK 0x90 58 #define MCP_SYNC_PHY_UNLOCK 0x91 59 #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */ 60 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 61 62 // PSP FW version 63 #define mmMP0_SMN_C2PMSG_58 0x1607A 64 65 //Register access policy version 66 #define mmMP0_SMN_C2PMSG_91 0x1609B 67 68 static bool dce_dmcu_init(struct dmcu *dmcu) 69 { 70 // Do nothing 71 return true; 72 } 73 74 bool dce_dmcu_load_iram(struct dmcu *dmcu, 75 unsigned int start_offset, 76 const char *src, 77 unsigned int bytes) 78 { 79 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 80 unsigned int count = 0; 81 82 /* Enable write access to IRAM */ 83 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 84 IRAM_HOST_ACCESS_EN, 1, 85 IRAM_WR_ADDR_AUTO_INC, 1); 86 87 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 88 89 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 90 91 for (count = 0; count < bytes; count++) 92 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 93 94 /* Disable write access to IRAM to allow dynamic sleep state */ 95 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 96 IRAM_HOST_ACCESS_EN, 0, 97 IRAM_WR_ADDR_AUTO_INC, 0); 98 99 return true; 100 } 101 102 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 103 { 104 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 105 106 uint32_t psr_state_offset = 0xf0; 107 108 /* Enable write access to IRAM */ 109 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 110 111 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 112 113 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 114 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 115 116 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 117 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 118 119 /* Disable write access to IRAM after finished using IRAM 120 * in order to allow dynamic sleep state 121 */ 122 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 123 } 124 125 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 126 { 127 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 128 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 129 unsigned int dmcu_wait_reg_ready_interval = 100; 130 131 unsigned int retryCount; 132 enum dc_psr_state state = PSR_STATE0; 133 134 /* waitDMCUReadyForCmd */ 135 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 136 dmcu_wait_reg_ready_interval, 137 dmcu_max_retry_on_wait_reg_ready); 138 139 /* setDMCUParam_Cmd */ 140 if (enable) 141 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 142 PSR_ENABLE); 143 else 144 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 145 PSR_EXIT); 146 147 /* notifyDMCUMsg */ 148 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 149 if (wait == true) { 150 for (retryCount = 0; retryCount <= 100; retryCount++) { 151 dce_get_dmcu_psr_state(dmcu, &state); 152 if (enable) { 153 if (state != PSR_STATE0) 154 break; 155 } else { 156 if (state == PSR_STATE0) 157 break; 158 } 159 udelay(10); 160 } 161 } 162 } 163 164 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 165 struct dc_link *link, 166 struct psr_context *psr_context) 167 { 168 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 169 170 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 171 unsigned int dmcu_wait_reg_ready_interval = 100; 172 173 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 174 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 175 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 176 177 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 178 psr_context->psrExitLinkTrainingRequired); 179 180 /* Enable static screen interrupts for PSR supported display */ 181 /* Disable the interrupt coming from other displays. */ 182 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 183 STATIC_SCREEN1_INT_TO_UC_EN, 0, 184 STATIC_SCREEN2_INT_TO_UC_EN, 0, 185 STATIC_SCREEN3_INT_TO_UC_EN, 0, 186 STATIC_SCREEN4_INT_TO_UC_EN, 0); 187 188 switch (psr_context->controllerId) { 189 /* Driver uses case 1 for unconfigured */ 190 case 1: 191 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 192 STATIC_SCREEN1_INT_TO_UC_EN, 1); 193 break; 194 case 2: 195 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 196 STATIC_SCREEN2_INT_TO_UC_EN, 1); 197 break; 198 case 3: 199 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 200 STATIC_SCREEN3_INT_TO_UC_EN, 1); 201 break; 202 case 4: 203 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 204 STATIC_SCREEN4_INT_TO_UC_EN, 1); 205 break; 206 case 5: 207 /* CZ/NL only has 4 CRTC!! 208 * really valid. 209 * There is no interrupt enable mask for these instances. 210 */ 211 break; 212 case 6: 213 /* CZ/NL only has 4 CRTC!! 214 * These are here because they are defined in HW regspec, 215 * but not really valid. There is no interrupt enable mask 216 * for these instances. 217 */ 218 break; 219 default: 220 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 221 STATIC_SCREEN1_INT_TO_UC_EN, 1); 222 break; 223 } 224 225 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 226 psr_context->sdpTransmitLineNumDeadline); 227 228 /* waitDMCUReadyForCmd */ 229 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 230 dmcu_wait_reg_ready_interval, 231 dmcu_max_retry_on_wait_reg_ready); 232 233 /* setDMCUParam_PSRHostConfigData */ 234 masterCmdData1.u32All = 0; 235 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 236 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 237 masterCmdData1.bits.rfb_update_auto_en = 238 psr_context->rfb_update_auto_en; 239 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 240 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 241 masterCmdData1.bits.phy_type = psr_context->phyType; 242 masterCmdData1.bits.frame_cap_ind = 243 psr_context->psrFrameCaptureIndicationReq; 244 masterCmdData1.bits.aux_chan = psr_context->channel; 245 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 246 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 247 masterCmdData1.u32All); 248 249 masterCmdData2.u32All = 0; 250 masterCmdData2.bits.dig_fe = psr_context->engineId; 251 masterCmdData2.bits.dig_be = psr_context->transmitterId; 252 masterCmdData2.bits.skip_wait_for_pll_lock = 253 psr_context->skipPsrWaitForPllLock; 254 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 255 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 256 masterCmdData2.bits.num_of_controllers = 257 psr_context->numberOfControllers; 258 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 259 masterCmdData2.u32All); 260 261 masterCmdData3.u32All = 0; 262 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 263 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 264 masterCmdData3.u32All); 265 266 /* setDMCUParam_Cmd */ 267 REG_UPDATE(MASTER_COMM_CMD_REG, 268 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 269 270 /* notifyDMCUMsg */ 271 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 272 273 return true; 274 } 275 276 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 277 { 278 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 279 unsigned int dmcu_uc_reset; 280 281 /* microcontroller is not running */ 282 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 283 284 /* DMCU is not running */ 285 if (dmcu_uc_reset) 286 return false; 287 288 return true; 289 } 290 291 static void dce_psr_wait_loop( 292 struct dmcu *dmcu, 293 unsigned int wait_loop_number) 294 { 295 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 296 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 297 298 if (dmcu->cached_wait_loop_number == wait_loop_number) 299 return; 300 301 /* DMCU is not running */ 302 if (!dce_is_dmcu_initialized(dmcu)) 303 return; 304 305 /* waitDMCUReadyForCmd */ 306 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 307 308 masterCmdData1.u32 = 0; 309 masterCmdData1.bits.wait_loop = wait_loop_number; 310 dmcu->cached_wait_loop_number = wait_loop_number; 311 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 312 313 /* setDMCUParam_Cmd */ 314 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 315 316 /* notifyDMCUMsg */ 317 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 318 } 319 320 static void dce_get_psr_wait_loop( 321 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 322 { 323 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 324 return; 325 } 326 327 #if defined(CONFIG_DRM_AMD_DC_DCN) 328 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 329 { 330 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 331 uint32_t dmcu_version_offset = 0xf1; 332 333 /* Enable write access to IRAM */ 334 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 335 IRAM_HOST_ACCESS_EN, 1, 336 IRAM_RD_ADDR_AUTO_INC, 1); 337 338 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 339 340 /* Write address to IRAM_RD_ADDR and read from DATA register */ 341 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 342 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 343 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 344 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 345 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 346 REG_READ(DMCU_IRAM_RD_DATA)); 347 348 /* Disable write access to IRAM to allow dynamic sleep state */ 349 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 350 IRAM_HOST_ACCESS_EN, 0, 351 IRAM_RD_ADDR_AUTO_INC, 0); 352 } 353 354 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu, 355 uint32_t fractional_pwm) 356 { 357 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 358 359 /* Wait until microcontroller is ready to process interrupt */ 360 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 361 362 /* Set PWM fractional enable/disable */ 363 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); 364 365 /* Set command to enable or disable fractional PWM microcontroller */ 366 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 367 MCP_BL_SET_PWM_FRAC); 368 369 /* Notify microcontroller of new command */ 370 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 371 372 /* Ensure command has been executed before continuing */ 373 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 374 } 375 376 static bool dcn10_dmcu_init(struct dmcu *dmcu) 377 { 378 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 379 const struct dc_config *config = &dmcu->ctx->dc->config; 380 bool status = false; 381 struct dc_context *ctx = dmcu->ctx; 382 unsigned int i; 383 // 5 4 3 2 1 0 384 // F E D C B A - bit 0 is A, bit 5 is F 385 unsigned int tx_interrupt_mask = 0; 386 387 PERF_TRACE(); 388 /* Definition of DC_DMCU_SCRATCH 389 * 0 : firmare not loaded 390 * 1 : PSP load DMCU FW but not initialized 391 * 2 : Firmware already initialized 392 */ 393 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 394 395 for (i = 0; i < ctx->dc->link_count; i++) { 396 if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) { 397 if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A && 398 ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) { 399 tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter; 400 } 401 } 402 } 403 404 switch (dmcu->dmcu_state) { 405 case DMCU_UNLOADED: 406 status = false; 407 break; 408 case DMCU_LOADED_UNINITIALIZED: 409 /* Wait until microcontroller is ready to process interrupt */ 410 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 411 412 /* Set initialized ramping boundary value */ 413 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 414 415 /* Set backlight ramping stepsize */ 416 REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize); 417 418 REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask); 419 420 /* Set command to initialize microcontroller */ 421 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 422 MCP_INIT_DMCU); 423 424 /* Notify microcontroller of new command */ 425 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 426 427 /* Ensure command has been executed before continuing */ 428 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 429 430 // Check state is initialized 431 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 432 433 // If microcontroller is not in running state, fail 434 if (dmcu->dmcu_state == DMCU_RUNNING) { 435 /* Retrieve and cache the DMCU firmware version. */ 436 dcn10_get_dmcu_version(dmcu); 437 438 /* Initialize DMCU to use fractional PWM or not */ 439 dcn10_dmcu_enable_fractional_pwm(dmcu, 440 (config->disable_fractional_pwm == false) ? 1 : 0); 441 status = true; 442 } else { 443 status = false; 444 } 445 446 break; 447 case DMCU_RUNNING: 448 status = true; 449 break; 450 default: 451 status = false; 452 break; 453 } 454 455 PERF_TRACE(); 456 return status; 457 } 458 459 static bool dcn21_dmcu_init(struct dmcu *dmcu) 460 { 461 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 462 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15); 463 464 if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) { 465 return false; 466 } 467 468 return dcn10_dmcu_init(dmcu); 469 } 470 471 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 472 unsigned int start_offset, 473 const char *src, 474 unsigned int bytes) 475 { 476 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 477 unsigned int count = 0; 478 479 /* If microcontroller is not running, do nothing */ 480 if (dmcu->dmcu_state != DMCU_RUNNING) 481 return false; 482 483 /* Enable write access to IRAM */ 484 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 485 IRAM_HOST_ACCESS_EN, 1, 486 IRAM_WR_ADDR_AUTO_INC, 1); 487 488 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 489 490 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 491 492 for (count = 0; count < bytes; count++) 493 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 494 495 /* Disable write access to IRAM to allow dynamic sleep state */ 496 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 497 IRAM_HOST_ACCESS_EN, 0, 498 IRAM_WR_ADDR_AUTO_INC, 0); 499 500 /* Wait until microcontroller is ready to process interrupt */ 501 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 502 503 /* Set command to signal IRAM is loaded and to initialize IRAM */ 504 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 505 MCP_INIT_IRAM); 506 507 /* Notify microcontroller of new command */ 508 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 509 510 /* Ensure command has been executed before continuing */ 511 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 512 513 return true; 514 } 515 516 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 517 { 518 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 519 520 uint32_t psr_state_offset = 0xf0; 521 522 /* If microcontroller is not running, do nothing */ 523 if (dmcu->dmcu_state != DMCU_RUNNING) 524 return; 525 526 /* Enable write access to IRAM */ 527 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 528 529 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 530 531 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 532 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 533 534 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 535 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 536 537 /* Disable write access to IRAM after finished using IRAM 538 * in order to allow dynamic sleep state 539 */ 540 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 541 } 542 543 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 544 { 545 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 546 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 547 unsigned int dmcu_wait_reg_ready_interval = 100; 548 549 unsigned int retryCount; 550 enum dc_psr_state state = PSR_STATE0; 551 552 /* If microcontroller is not running, do nothing */ 553 if (dmcu->dmcu_state != DMCU_RUNNING) 554 return; 555 556 /* waitDMCUReadyForCmd */ 557 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 558 dmcu_wait_reg_ready_interval, 559 dmcu_max_retry_on_wait_reg_ready); 560 561 /* setDMCUParam_Cmd */ 562 if (enable) 563 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 564 PSR_ENABLE); 565 else 566 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 567 PSR_EXIT); 568 569 /* notifyDMCUMsg */ 570 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 571 572 /* Below loops 1000 x 500us = 500 ms. 573 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 574 * least a few frames. Should never hit the max retry assert below. 575 */ 576 if (wait == true) { 577 for (retryCount = 0; retryCount <= 1000; retryCount++) { 578 dcn10_get_dmcu_psr_state(dmcu, &state); 579 if (enable) { 580 if (state != PSR_STATE0) 581 break; 582 } else { 583 if (state == PSR_STATE0) 584 break; 585 } 586 udelay(500); 587 } 588 589 /* assert if max retry hit */ 590 if (retryCount >= 1000) 591 ASSERT(0); 592 } 593 } 594 595 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 596 struct dc_link *link, 597 struct psr_context *psr_context) 598 { 599 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 600 601 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 602 unsigned int dmcu_wait_reg_ready_interval = 100; 603 604 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 605 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 606 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 607 608 /* If microcontroller is not running, do nothing */ 609 if (dmcu->dmcu_state != DMCU_RUNNING) 610 return false; 611 612 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 613 psr_context->psrExitLinkTrainingRequired); 614 615 /* Enable static screen interrupts for PSR supported display */ 616 /* Disable the interrupt coming from other displays. */ 617 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 618 STATIC_SCREEN1_INT_TO_UC_EN, 0, 619 STATIC_SCREEN2_INT_TO_UC_EN, 0, 620 STATIC_SCREEN3_INT_TO_UC_EN, 0, 621 STATIC_SCREEN4_INT_TO_UC_EN, 0); 622 623 switch (psr_context->controllerId) { 624 /* Driver uses case 1 for unconfigured */ 625 case 1: 626 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 627 STATIC_SCREEN1_INT_TO_UC_EN, 1); 628 break; 629 case 2: 630 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 631 STATIC_SCREEN2_INT_TO_UC_EN, 1); 632 break; 633 case 3: 634 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 635 STATIC_SCREEN3_INT_TO_UC_EN, 1); 636 break; 637 case 4: 638 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 639 STATIC_SCREEN4_INT_TO_UC_EN, 1); 640 break; 641 case 5: 642 /* CZ/NL only has 4 CRTC!! 643 * really valid. 644 * There is no interrupt enable mask for these instances. 645 */ 646 break; 647 case 6: 648 /* CZ/NL only has 4 CRTC!! 649 * These are here because they are defined in HW regspec, 650 * but not really valid. There is no interrupt enable mask 651 * for these instances. 652 */ 653 break; 654 default: 655 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 656 STATIC_SCREEN1_INT_TO_UC_EN, 1); 657 break; 658 } 659 660 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 661 psr_context->sdpTransmitLineNumDeadline); 662 663 if (psr_context->allow_smu_optimizations) 664 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 665 666 /* waitDMCUReadyForCmd */ 667 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 668 dmcu_wait_reg_ready_interval, 669 dmcu_max_retry_on_wait_reg_ready); 670 671 /* setDMCUParam_PSRHostConfigData */ 672 masterCmdData1.u32All = 0; 673 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 674 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 675 masterCmdData1.bits.rfb_update_auto_en = 676 psr_context->rfb_update_auto_en; 677 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 678 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 679 masterCmdData1.bits.phy_type = psr_context->phyType; 680 masterCmdData1.bits.frame_cap_ind = 681 psr_context->psrFrameCaptureIndicationReq; 682 masterCmdData1.bits.aux_chan = psr_context->channel; 683 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 684 masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations; 685 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 686 masterCmdData1.u32All); 687 688 masterCmdData2.u32All = 0; 689 masterCmdData2.bits.dig_fe = psr_context->engineId; 690 masterCmdData2.bits.dig_be = psr_context->transmitterId; 691 masterCmdData2.bits.skip_wait_for_pll_lock = 692 psr_context->skipPsrWaitForPllLock; 693 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 694 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 695 masterCmdData2.bits.num_of_controllers = 696 psr_context->numberOfControllers; 697 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 698 masterCmdData2.u32All); 699 700 masterCmdData3.u32All = 0; 701 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 702 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 703 masterCmdData3.u32All); 704 705 706 /* setDMCUParam_Cmd */ 707 REG_UPDATE(MASTER_COMM_CMD_REG, 708 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 709 710 /* notifyDMCUMsg */ 711 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 712 713 /* waitDMCUReadyForCmd */ 714 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 715 716 return true; 717 } 718 719 static void dcn10_psr_wait_loop( 720 struct dmcu *dmcu, 721 unsigned int wait_loop_number) 722 { 723 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 724 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 725 726 /* If microcontroller is not running, do nothing */ 727 if (dmcu->dmcu_state != DMCU_RUNNING) 728 return; 729 730 if (wait_loop_number != 0) { 731 /* waitDMCUReadyForCmd */ 732 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 733 734 masterCmdData1.u32 = 0; 735 masterCmdData1.bits.wait_loop = wait_loop_number; 736 dmcu->cached_wait_loop_number = wait_loop_number; 737 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 738 739 /* setDMCUParam_Cmd */ 740 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 741 742 /* notifyDMCUMsg */ 743 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 744 } 745 } 746 747 static void dcn10_get_psr_wait_loop( 748 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 749 { 750 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 751 return; 752 } 753 754 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 755 { 756 /* microcontroller is not running */ 757 if (dmcu->dmcu_state != DMCU_RUNNING) 758 return false; 759 return true; 760 } 761 762 763 764 static bool dcn20_lock_phy(struct dmcu *dmcu) 765 { 766 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 767 768 /* If microcontroller is not running, do nothing */ 769 if (dmcu->dmcu_state != DMCU_RUNNING) 770 return false; 771 772 /* waitDMCUReadyForCmd */ 773 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 774 775 /* setDMCUParam_Cmd */ 776 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK); 777 778 /* notifyDMCUMsg */ 779 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 780 781 /* waitDMCUReadyForCmd */ 782 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 783 784 return true; 785 } 786 787 static bool dcn20_unlock_phy(struct dmcu *dmcu) 788 { 789 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 790 791 /* If microcontroller is not running, do nothing */ 792 if (dmcu->dmcu_state != DMCU_RUNNING) 793 return false; 794 795 /* waitDMCUReadyForCmd */ 796 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 797 798 /* setDMCUParam_Cmd */ 799 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK); 800 801 /* notifyDMCUMsg */ 802 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 803 804 /* waitDMCUReadyForCmd */ 805 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 806 807 return true; 808 } 809 810 #endif //(CONFIG_DRM_AMD_DC_DCN) 811 812 static const struct dmcu_funcs dce_funcs = { 813 .dmcu_init = dce_dmcu_init, 814 .load_iram = dce_dmcu_load_iram, 815 .set_psr_enable = dce_dmcu_set_psr_enable, 816 .setup_psr = dce_dmcu_setup_psr, 817 .get_psr_state = dce_get_dmcu_psr_state, 818 .set_psr_wait_loop = dce_psr_wait_loop, 819 .get_psr_wait_loop = dce_get_psr_wait_loop, 820 .is_dmcu_initialized = dce_is_dmcu_initialized 821 }; 822 823 #if defined(CONFIG_DRM_AMD_DC_DCN) 824 static const struct dmcu_funcs dcn10_funcs = { 825 .dmcu_init = dcn10_dmcu_init, 826 .load_iram = dcn10_dmcu_load_iram, 827 .set_psr_enable = dcn10_dmcu_set_psr_enable, 828 .setup_psr = dcn10_dmcu_setup_psr, 829 .get_psr_state = dcn10_get_dmcu_psr_state, 830 .set_psr_wait_loop = dcn10_psr_wait_loop, 831 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 832 .is_dmcu_initialized = dcn10_is_dmcu_initialized 833 }; 834 835 static const struct dmcu_funcs dcn20_funcs = { 836 .dmcu_init = dcn10_dmcu_init, 837 .load_iram = dcn10_dmcu_load_iram, 838 .set_psr_enable = dcn10_dmcu_set_psr_enable, 839 .setup_psr = dcn10_dmcu_setup_psr, 840 .get_psr_state = dcn10_get_dmcu_psr_state, 841 .set_psr_wait_loop = dcn10_psr_wait_loop, 842 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 843 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 844 .lock_phy = dcn20_lock_phy, 845 .unlock_phy = dcn20_unlock_phy 846 }; 847 848 static const struct dmcu_funcs dcn21_funcs = { 849 .dmcu_init = dcn21_dmcu_init, 850 .load_iram = dcn10_dmcu_load_iram, 851 .set_psr_enable = dcn10_dmcu_set_psr_enable, 852 .setup_psr = dcn10_dmcu_setup_psr, 853 .get_psr_state = dcn10_get_dmcu_psr_state, 854 .set_psr_wait_loop = dcn10_psr_wait_loop, 855 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 856 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 857 .lock_phy = dcn20_lock_phy, 858 .unlock_phy = dcn20_unlock_phy 859 }; 860 #endif 861 862 static void dce_dmcu_construct( 863 struct dce_dmcu *dmcu_dce, 864 struct dc_context *ctx, 865 const struct dce_dmcu_registers *regs, 866 const struct dce_dmcu_shift *dmcu_shift, 867 const struct dce_dmcu_mask *dmcu_mask) 868 { 869 struct dmcu *base = &dmcu_dce->base; 870 871 base->ctx = ctx; 872 base->funcs = &dce_funcs; 873 base->cached_wait_loop_number = 0; 874 875 dmcu_dce->regs = regs; 876 dmcu_dce->dmcu_shift = dmcu_shift; 877 dmcu_dce->dmcu_mask = dmcu_mask; 878 } 879 880 #if defined(CONFIG_DRM_AMD_DC_DCN) 881 static void dcn21_dmcu_construct( 882 struct dce_dmcu *dmcu_dce, 883 struct dc_context *ctx, 884 const struct dce_dmcu_registers *regs, 885 const struct dce_dmcu_shift *dmcu_shift, 886 const struct dce_dmcu_mask *dmcu_mask) 887 { 888 uint32_t psp_version = 0; 889 890 dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 891 892 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 893 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); 894 dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029); 895 dmcu_dce->base.psp_version = psp_version; 896 } 897 } 898 #endif 899 900 struct dmcu *dce_dmcu_create( 901 struct dc_context *ctx, 902 const struct dce_dmcu_registers *regs, 903 const struct dce_dmcu_shift *dmcu_shift, 904 const struct dce_dmcu_mask *dmcu_mask) 905 { 906 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 907 908 if (dmcu_dce == NULL) { 909 BREAK_TO_DEBUGGER(); 910 return NULL; 911 } 912 913 dce_dmcu_construct( 914 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 915 916 dmcu_dce->base.funcs = &dce_funcs; 917 918 return &dmcu_dce->base; 919 } 920 921 #if defined(CONFIG_DRM_AMD_DC_DCN) 922 struct dmcu *dcn10_dmcu_create( 923 struct dc_context *ctx, 924 const struct dce_dmcu_registers *regs, 925 const struct dce_dmcu_shift *dmcu_shift, 926 const struct dce_dmcu_mask *dmcu_mask) 927 { 928 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 929 930 if (dmcu_dce == NULL) { 931 BREAK_TO_DEBUGGER(); 932 return NULL; 933 } 934 935 dce_dmcu_construct( 936 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 937 938 dmcu_dce->base.funcs = &dcn10_funcs; 939 940 return &dmcu_dce->base; 941 } 942 943 struct dmcu *dcn20_dmcu_create( 944 struct dc_context *ctx, 945 const struct dce_dmcu_registers *regs, 946 const struct dce_dmcu_shift *dmcu_shift, 947 const struct dce_dmcu_mask *dmcu_mask) 948 { 949 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 950 951 if (dmcu_dce == NULL) { 952 BREAK_TO_DEBUGGER(); 953 return NULL; 954 } 955 956 dce_dmcu_construct( 957 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 958 959 dmcu_dce->base.funcs = &dcn20_funcs; 960 961 return &dmcu_dce->base; 962 } 963 964 struct dmcu *dcn21_dmcu_create( 965 struct dc_context *ctx, 966 const struct dce_dmcu_registers *regs, 967 const struct dce_dmcu_shift *dmcu_shift, 968 const struct dce_dmcu_mask *dmcu_mask) 969 { 970 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 971 972 if (dmcu_dce == NULL) { 973 BREAK_TO_DEBUGGER(); 974 return NULL; 975 } 976 977 dcn21_dmcu_construct( 978 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 979 980 dmcu_dce->base.funcs = &dcn21_funcs; 981 982 return &dmcu_dce->base; 983 } 984 #endif 985 986 void dce_dmcu_destroy(struct dmcu **dmcu) 987 { 988 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 989 990 kfree(dmcu_dce); 991 *dmcu = NULL; 992 } 993