1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "core_types.h" 30 #include "link_encoder.h" 31 #include "dce_dmcu.h" 32 #include "dm_services.h" 33 #include "reg_helper.h" 34 #include "fixed31_32.h" 35 #include "dc.h" 36 37 #define TO_DCE_DMCU(dmcu)\ 38 container_of(dmcu, struct dce_dmcu, base) 39 40 #define REG(reg) \ 41 (dmcu_dce->regs->reg) 42 43 #undef FN 44 #define FN(reg_name, field_name) \ 45 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 46 47 #define CTX \ 48 dmcu_dce->base.ctx 49 50 /* PSR related commands */ 51 #define PSR_ENABLE 0x20 52 #define PSR_EXIT 0x21 53 #define PSR_SET 0x23 54 #define PSR_SET_WAITLOOP 0x31 55 #define MCP_INIT_DMCU 0x88 56 #define MCP_INIT_IRAM 0x89 57 #define MCP_SYNC_PHY_LOCK 0x90 58 #define MCP_SYNC_PHY_UNLOCK 0x91 59 #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */ 60 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 61 62 // PSP FW version 63 #define mmMP0_SMN_C2PMSG_58 0x1607A 64 65 //Register access policy version 66 #define mmMP0_SMN_C2PMSG_91 0x1609B 67 68 #if defined(CONFIG_DRM_AMD_DC_DCN) 69 static const uint32_t abm_gain_stepsize = 0x0060; 70 #endif 71 72 static bool dce_dmcu_init(struct dmcu *dmcu) 73 { 74 // Do nothing 75 return true; 76 } 77 78 static bool dce_dmcu_load_iram(struct dmcu *dmcu, 79 unsigned int start_offset, 80 const char *src, 81 unsigned int bytes) 82 { 83 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 84 unsigned int count = 0; 85 86 /* Enable write access to IRAM */ 87 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 88 IRAM_HOST_ACCESS_EN, 1, 89 IRAM_WR_ADDR_AUTO_INC, 1); 90 91 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 92 93 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 94 95 for (count = 0; count < bytes; count++) 96 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 97 98 /* Disable write access to IRAM to allow dynamic sleep state */ 99 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 100 IRAM_HOST_ACCESS_EN, 0, 101 IRAM_WR_ADDR_AUTO_INC, 0); 102 103 return true; 104 } 105 106 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 107 { 108 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 109 110 uint32_t psr_state_offset = 0xf0; 111 112 /* Enable write access to IRAM */ 113 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 114 115 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 116 117 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 118 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 119 120 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 121 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 122 123 /* Disable write access to IRAM after finished using IRAM 124 * in order to allow dynamic sleep state 125 */ 126 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 127 } 128 129 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 130 { 131 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 132 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 133 unsigned int dmcu_wait_reg_ready_interval = 100; 134 135 unsigned int retryCount; 136 enum dc_psr_state state = PSR_STATE0; 137 138 /* waitDMCUReadyForCmd */ 139 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 140 dmcu_wait_reg_ready_interval, 141 dmcu_max_retry_on_wait_reg_ready); 142 143 /* setDMCUParam_Cmd */ 144 if (enable) 145 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 146 PSR_ENABLE); 147 else 148 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 149 PSR_EXIT); 150 151 /* notifyDMCUMsg */ 152 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 153 if (wait == true) { 154 for (retryCount = 0; retryCount <= 100; retryCount++) { 155 dce_get_dmcu_psr_state(dmcu, &state); 156 if (enable) { 157 if (state != PSR_STATE0) 158 break; 159 } else { 160 if (state == PSR_STATE0) 161 break; 162 } 163 udelay(10); 164 } 165 } 166 } 167 168 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 169 struct dc_link *link, 170 struct psr_context *psr_context) 171 { 172 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 173 174 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 175 unsigned int dmcu_wait_reg_ready_interval = 100; 176 177 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 178 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 179 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 180 181 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 182 psr_context->psrExitLinkTrainingRequired); 183 184 /* Enable static screen interrupts for PSR supported display */ 185 /* Disable the interrupt coming from other displays. */ 186 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 187 STATIC_SCREEN1_INT_TO_UC_EN, 0, 188 STATIC_SCREEN2_INT_TO_UC_EN, 0, 189 STATIC_SCREEN3_INT_TO_UC_EN, 0, 190 STATIC_SCREEN4_INT_TO_UC_EN, 0); 191 192 switch (psr_context->controllerId) { 193 /* Driver uses case 1 for unconfigured */ 194 case 1: 195 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 196 STATIC_SCREEN1_INT_TO_UC_EN, 1); 197 break; 198 case 2: 199 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 200 STATIC_SCREEN2_INT_TO_UC_EN, 1); 201 break; 202 case 3: 203 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 204 STATIC_SCREEN3_INT_TO_UC_EN, 1); 205 break; 206 case 4: 207 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 208 STATIC_SCREEN4_INT_TO_UC_EN, 1); 209 break; 210 case 5: 211 /* CZ/NL only has 4 CRTC!! 212 * really valid. 213 * There is no interrupt enable mask for these instances. 214 */ 215 break; 216 case 6: 217 /* CZ/NL only has 4 CRTC!! 218 * These are here because they are defined in HW regspec, 219 * but not really valid. There is no interrupt enable mask 220 * for these instances. 221 */ 222 break; 223 default: 224 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 225 STATIC_SCREEN1_INT_TO_UC_EN, 1); 226 break; 227 } 228 229 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 230 psr_context->sdpTransmitLineNumDeadline); 231 232 /* waitDMCUReadyForCmd */ 233 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 234 dmcu_wait_reg_ready_interval, 235 dmcu_max_retry_on_wait_reg_ready); 236 237 /* setDMCUParam_PSRHostConfigData */ 238 masterCmdData1.u32All = 0; 239 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 240 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 241 masterCmdData1.bits.rfb_update_auto_en = 242 psr_context->rfb_update_auto_en; 243 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 244 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 245 masterCmdData1.bits.phy_type = psr_context->phyType; 246 masterCmdData1.bits.frame_cap_ind = 247 psr_context->psrFrameCaptureIndicationReq; 248 masterCmdData1.bits.aux_chan = psr_context->channel; 249 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 250 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 251 masterCmdData1.u32All); 252 253 masterCmdData2.u32All = 0; 254 masterCmdData2.bits.dig_fe = psr_context->engineId; 255 masterCmdData2.bits.dig_be = psr_context->transmitterId; 256 masterCmdData2.bits.skip_wait_for_pll_lock = 257 psr_context->skipPsrWaitForPllLock; 258 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 259 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 260 masterCmdData2.bits.num_of_controllers = 261 psr_context->numberOfControllers; 262 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 263 masterCmdData2.u32All); 264 265 masterCmdData3.u32All = 0; 266 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 267 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 268 masterCmdData3.u32All); 269 270 /* setDMCUParam_Cmd */ 271 REG_UPDATE(MASTER_COMM_CMD_REG, 272 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 273 274 /* notifyDMCUMsg */ 275 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 276 277 return true; 278 } 279 280 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 281 { 282 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 283 unsigned int dmcu_uc_reset; 284 285 /* microcontroller is not running */ 286 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 287 288 /* DMCU is not running */ 289 if (dmcu_uc_reset) 290 return false; 291 292 return true; 293 } 294 295 static void dce_psr_wait_loop( 296 struct dmcu *dmcu, 297 unsigned int wait_loop_number) 298 { 299 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 300 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 301 302 if (dmcu->cached_wait_loop_number == wait_loop_number) 303 return; 304 305 /* DMCU is not running */ 306 if (!dce_is_dmcu_initialized(dmcu)) 307 return; 308 309 /* waitDMCUReadyForCmd */ 310 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 311 312 masterCmdData1.u32 = 0; 313 masterCmdData1.bits.wait_loop = wait_loop_number; 314 dmcu->cached_wait_loop_number = wait_loop_number; 315 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 316 317 /* setDMCUParam_Cmd */ 318 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 319 320 /* notifyDMCUMsg */ 321 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 322 } 323 324 static void dce_get_psr_wait_loop( 325 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 326 { 327 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 328 return; 329 } 330 331 #if defined(CONFIG_DRM_AMD_DC_DCN) 332 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 333 { 334 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 335 uint32_t dmcu_version_offset = 0xf1; 336 337 /* Enable write access to IRAM */ 338 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 339 IRAM_HOST_ACCESS_EN, 1, 340 IRAM_RD_ADDR_AUTO_INC, 1); 341 342 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 343 344 /* Write address to IRAM_RD_ADDR and read from DATA register */ 345 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 346 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 347 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 348 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 349 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 350 REG_READ(DMCU_IRAM_RD_DATA)); 351 352 /* Disable write access to IRAM to allow dynamic sleep state */ 353 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 354 IRAM_HOST_ACCESS_EN, 0, 355 IRAM_RD_ADDR_AUTO_INC, 0); 356 } 357 358 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu, 359 uint32_t fractional_pwm) 360 { 361 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 362 363 /* Wait until microcontroller is ready to process interrupt */ 364 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 365 366 /* Set PWM fractional enable/disable */ 367 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); 368 369 /* Set command to enable or disable fractional PWM microcontroller */ 370 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 371 MCP_BL_SET_PWM_FRAC); 372 373 /* Notify microcontroller of new command */ 374 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 375 376 /* Ensure command has been executed before continuing */ 377 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 378 } 379 380 static bool dcn10_dmcu_init(struct dmcu *dmcu) 381 { 382 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 383 const struct dc_config *config = &dmcu->ctx->dc->config; 384 bool status = false; 385 struct dc_context *ctx = dmcu->ctx; 386 unsigned int i; 387 // 5 4 3 2 1 0 388 // F E D C B A - bit 0 is A, bit 5 is F 389 unsigned int tx_interrupt_mask = 0; 390 391 PERF_TRACE(); 392 /* Definition of DC_DMCU_SCRATCH 393 * 0 : firmare not loaded 394 * 1 : PSP load DMCU FW but not initialized 395 * 2 : Firmware already initialized 396 */ 397 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 398 399 for (i = 0; i < ctx->dc->link_count; i++) { 400 if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) { 401 if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A && 402 ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) { 403 tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter; 404 } 405 } 406 } 407 408 switch (dmcu->dmcu_state) { 409 case DMCU_UNLOADED: 410 status = false; 411 break; 412 case DMCU_LOADED_UNINITIALIZED: 413 /* Wait until microcontroller is ready to process interrupt */ 414 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 415 416 /* Set initialized ramping boundary value */ 417 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 418 419 /* Set backlight ramping stepsize */ 420 REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize); 421 422 REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask); 423 424 /* Set command to initialize microcontroller */ 425 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 426 MCP_INIT_DMCU); 427 428 /* Notify microcontroller of new command */ 429 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 430 431 /* Ensure command has been executed before continuing */ 432 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 433 434 // Check state is initialized 435 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 436 437 // If microcontroller is not in running state, fail 438 if (dmcu->dmcu_state == DMCU_RUNNING) { 439 /* Retrieve and cache the DMCU firmware version. */ 440 dcn10_get_dmcu_version(dmcu); 441 442 /* Initialize DMCU to use fractional PWM or not */ 443 dcn10_dmcu_enable_fractional_pwm(dmcu, 444 (config->disable_fractional_pwm == false) ? 1 : 0); 445 status = true; 446 } else { 447 status = false; 448 } 449 450 break; 451 case DMCU_RUNNING: 452 status = true; 453 break; 454 default: 455 status = false; 456 break; 457 } 458 459 PERF_TRACE(); 460 return status; 461 } 462 463 static bool dcn21_dmcu_init(struct dmcu *dmcu) 464 { 465 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 466 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15); 467 468 if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) { 469 return false; 470 } 471 472 return dcn10_dmcu_init(dmcu); 473 } 474 475 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 476 unsigned int start_offset, 477 const char *src, 478 unsigned int bytes) 479 { 480 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 481 unsigned int count = 0; 482 483 /* If microcontroller is not running, do nothing */ 484 if (dmcu->dmcu_state != DMCU_RUNNING) 485 return false; 486 487 /* Enable write access to IRAM */ 488 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 489 IRAM_HOST_ACCESS_EN, 1, 490 IRAM_WR_ADDR_AUTO_INC, 1); 491 492 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 493 494 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 495 496 for (count = 0; count < bytes; count++) 497 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 498 499 /* Disable write access to IRAM to allow dynamic sleep state */ 500 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 501 IRAM_HOST_ACCESS_EN, 0, 502 IRAM_WR_ADDR_AUTO_INC, 0); 503 504 /* Wait until microcontroller is ready to process interrupt */ 505 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 506 507 /* Set command to signal IRAM is loaded and to initialize IRAM */ 508 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 509 MCP_INIT_IRAM); 510 511 /* Notify microcontroller of new command */ 512 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 513 514 /* Ensure command has been executed before continuing */ 515 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 516 517 return true; 518 } 519 520 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 521 { 522 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 523 524 uint32_t psr_state_offset = 0xf0; 525 526 /* If microcontroller is not running, do nothing */ 527 if (dmcu->dmcu_state != DMCU_RUNNING) 528 return; 529 530 /* Enable write access to IRAM */ 531 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 532 533 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 534 535 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 536 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 537 538 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 539 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 540 541 /* Disable write access to IRAM after finished using IRAM 542 * in order to allow dynamic sleep state 543 */ 544 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 545 } 546 547 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 548 { 549 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 550 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 551 unsigned int dmcu_wait_reg_ready_interval = 100; 552 553 unsigned int retryCount; 554 enum dc_psr_state state = PSR_STATE0; 555 556 /* If microcontroller is not running, do nothing */ 557 if (dmcu->dmcu_state != DMCU_RUNNING) 558 return; 559 560 /* waitDMCUReadyForCmd */ 561 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 562 dmcu_wait_reg_ready_interval, 563 dmcu_max_retry_on_wait_reg_ready); 564 565 /* setDMCUParam_Cmd */ 566 if (enable) 567 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 568 PSR_ENABLE); 569 else 570 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 571 PSR_EXIT); 572 573 /* notifyDMCUMsg */ 574 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 575 576 /* Below loops 1000 x 500us = 500 ms. 577 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 578 * least a few frames. Should never hit the max retry assert below. 579 */ 580 if (wait == true) { 581 for (retryCount = 0; retryCount <= 1000; retryCount++) { 582 dcn10_get_dmcu_psr_state(dmcu, &state); 583 if (enable) { 584 if (state != PSR_STATE0) 585 break; 586 } else { 587 if (state == PSR_STATE0) 588 break; 589 } 590 udelay(500); 591 } 592 593 /* assert if max retry hit */ 594 if (retryCount >= 1000) 595 ASSERT(0); 596 } 597 } 598 599 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 600 struct dc_link *link, 601 struct psr_context *psr_context) 602 { 603 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 604 605 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 606 unsigned int dmcu_wait_reg_ready_interval = 100; 607 608 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 609 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 610 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 611 612 /* If microcontroller is not running, do nothing */ 613 if (dmcu->dmcu_state != DMCU_RUNNING) 614 return false; 615 616 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 617 psr_context->psrExitLinkTrainingRequired); 618 619 /* Enable static screen interrupts for PSR supported display */ 620 /* Disable the interrupt coming from other displays. */ 621 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 622 STATIC_SCREEN1_INT_TO_UC_EN, 0, 623 STATIC_SCREEN2_INT_TO_UC_EN, 0, 624 STATIC_SCREEN3_INT_TO_UC_EN, 0, 625 STATIC_SCREEN4_INT_TO_UC_EN, 0); 626 627 switch (psr_context->controllerId) { 628 /* Driver uses case 1 for unconfigured */ 629 case 1: 630 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 631 STATIC_SCREEN1_INT_TO_UC_EN, 1); 632 break; 633 case 2: 634 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 635 STATIC_SCREEN2_INT_TO_UC_EN, 1); 636 break; 637 case 3: 638 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 639 STATIC_SCREEN3_INT_TO_UC_EN, 1); 640 break; 641 case 4: 642 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 643 STATIC_SCREEN4_INT_TO_UC_EN, 1); 644 break; 645 case 5: 646 /* CZ/NL only has 4 CRTC!! 647 * really valid. 648 * There is no interrupt enable mask for these instances. 649 */ 650 break; 651 case 6: 652 /* CZ/NL only has 4 CRTC!! 653 * These are here because they are defined in HW regspec, 654 * but not really valid. There is no interrupt enable mask 655 * for these instances. 656 */ 657 break; 658 default: 659 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 660 STATIC_SCREEN1_INT_TO_UC_EN, 1); 661 break; 662 } 663 664 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 665 psr_context->sdpTransmitLineNumDeadline); 666 667 if (psr_context->allow_smu_optimizations) 668 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 669 670 /* waitDMCUReadyForCmd */ 671 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 672 dmcu_wait_reg_ready_interval, 673 dmcu_max_retry_on_wait_reg_ready); 674 675 /* setDMCUParam_PSRHostConfigData */ 676 masterCmdData1.u32All = 0; 677 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 678 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 679 masterCmdData1.bits.rfb_update_auto_en = 680 psr_context->rfb_update_auto_en; 681 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 682 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 683 masterCmdData1.bits.phy_type = psr_context->phyType; 684 masterCmdData1.bits.frame_cap_ind = 685 psr_context->psrFrameCaptureIndicationReq; 686 masterCmdData1.bits.aux_chan = psr_context->channel; 687 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 688 masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations; 689 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 690 masterCmdData1.u32All); 691 692 masterCmdData2.u32All = 0; 693 masterCmdData2.bits.dig_fe = psr_context->engineId; 694 masterCmdData2.bits.dig_be = psr_context->transmitterId; 695 masterCmdData2.bits.skip_wait_for_pll_lock = 696 psr_context->skipPsrWaitForPllLock; 697 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 698 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 699 masterCmdData2.bits.num_of_controllers = 700 psr_context->numberOfControllers; 701 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 702 masterCmdData2.u32All); 703 704 masterCmdData3.u32All = 0; 705 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 706 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 707 masterCmdData3.u32All); 708 709 710 /* setDMCUParam_Cmd */ 711 REG_UPDATE(MASTER_COMM_CMD_REG, 712 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 713 714 /* notifyDMCUMsg */ 715 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 716 717 /* waitDMCUReadyForCmd */ 718 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 719 720 return true; 721 } 722 723 static void dcn10_psr_wait_loop( 724 struct dmcu *dmcu, 725 unsigned int wait_loop_number) 726 { 727 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 728 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 729 730 /* If microcontroller is not running, do nothing */ 731 if (dmcu->dmcu_state != DMCU_RUNNING) 732 return; 733 734 if (wait_loop_number != 0) { 735 /* waitDMCUReadyForCmd */ 736 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 737 738 masterCmdData1.u32 = 0; 739 masterCmdData1.bits.wait_loop = wait_loop_number; 740 dmcu->cached_wait_loop_number = wait_loop_number; 741 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 742 743 /* setDMCUParam_Cmd */ 744 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 745 746 /* notifyDMCUMsg */ 747 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 748 } 749 } 750 751 static void dcn10_get_psr_wait_loop( 752 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 753 { 754 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 755 return; 756 } 757 758 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 759 { 760 /* microcontroller is not running */ 761 if (dmcu->dmcu_state != DMCU_RUNNING) 762 return false; 763 return true; 764 } 765 766 767 768 static bool dcn20_lock_phy(struct dmcu *dmcu) 769 { 770 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 771 772 /* If microcontroller is not running, do nothing */ 773 if (dmcu->dmcu_state != DMCU_RUNNING) 774 return false; 775 776 /* waitDMCUReadyForCmd */ 777 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 778 779 /* setDMCUParam_Cmd */ 780 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK); 781 782 /* notifyDMCUMsg */ 783 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 784 785 /* waitDMCUReadyForCmd */ 786 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 787 788 return true; 789 } 790 791 static bool dcn20_unlock_phy(struct dmcu *dmcu) 792 { 793 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 794 795 /* If microcontroller is not running, do nothing */ 796 if (dmcu->dmcu_state != DMCU_RUNNING) 797 return false; 798 799 /* waitDMCUReadyForCmd */ 800 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 801 802 /* setDMCUParam_Cmd */ 803 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK); 804 805 /* notifyDMCUMsg */ 806 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 807 808 /* waitDMCUReadyForCmd */ 809 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 810 811 return true; 812 } 813 814 #endif //(CONFIG_DRM_AMD_DC_DCN) 815 816 static const struct dmcu_funcs dce_funcs = { 817 .dmcu_init = dce_dmcu_init, 818 .load_iram = dce_dmcu_load_iram, 819 .set_psr_enable = dce_dmcu_set_psr_enable, 820 .setup_psr = dce_dmcu_setup_psr, 821 .get_psr_state = dce_get_dmcu_psr_state, 822 .set_psr_wait_loop = dce_psr_wait_loop, 823 .get_psr_wait_loop = dce_get_psr_wait_loop, 824 .is_dmcu_initialized = dce_is_dmcu_initialized 825 }; 826 827 #if defined(CONFIG_DRM_AMD_DC_DCN) 828 static const struct dmcu_funcs dcn10_funcs = { 829 .dmcu_init = dcn10_dmcu_init, 830 .load_iram = dcn10_dmcu_load_iram, 831 .set_psr_enable = dcn10_dmcu_set_psr_enable, 832 .setup_psr = dcn10_dmcu_setup_psr, 833 .get_psr_state = dcn10_get_dmcu_psr_state, 834 .set_psr_wait_loop = dcn10_psr_wait_loop, 835 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 836 .is_dmcu_initialized = dcn10_is_dmcu_initialized 837 }; 838 839 static const struct dmcu_funcs dcn20_funcs = { 840 .dmcu_init = dcn10_dmcu_init, 841 .load_iram = dcn10_dmcu_load_iram, 842 .set_psr_enable = dcn10_dmcu_set_psr_enable, 843 .setup_psr = dcn10_dmcu_setup_psr, 844 .get_psr_state = dcn10_get_dmcu_psr_state, 845 .set_psr_wait_loop = dcn10_psr_wait_loop, 846 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 847 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 848 .lock_phy = dcn20_lock_phy, 849 .unlock_phy = dcn20_unlock_phy 850 }; 851 852 static const struct dmcu_funcs dcn21_funcs = { 853 .dmcu_init = dcn21_dmcu_init, 854 .load_iram = dcn10_dmcu_load_iram, 855 .set_psr_enable = dcn10_dmcu_set_psr_enable, 856 .setup_psr = dcn10_dmcu_setup_psr, 857 .get_psr_state = dcn10_get_dmcu_psr_state, 858 .set_psr_wait_loop = dcn10_psr_wait_loop, 859 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 860 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 861 .lock_phy = dcn20_lock_phy, 862 .unlock_phy = dcn20_unlock_phy 863 }; 864 #endif 865 866 static void dce_dmcu_construct( 867 struct dce_dmcu *dmcu_dce, 868 struct dc_context *ctx, 869 const struct dce_dmcu_registers *regs, 870 const struct dce_dmcu_shift *dmcu_shift, 871 const struct dce_dmcu_mask *dmcu_mask) 872 { 873 struct dmcu *base = &dmcu_dce->base; 874 875 base->ctx = ctx; 876 base->funcs = &dce_funcs; 877 base->cached_wait_loop_number = 0; 878 879 dmcu_dce->regs = regs; 880 dmcu_dce->dmcu_shift = dmcu_shift; 881 dmcu_dce->dmcu_mask = dmcu_mask; 882 } 883 884 #if defined(CONFIG_DRM_AMD_DC_DCN) 885 static void dcn21_dmcu_construct( 886 struct dce_dmcu *dmcu_dce, 887 struct dc_context *ctx, 888 const struct dce_dmcu_registers *regs, 889 const struct dce_dmcu_shift *dmcu_shift, 890 const struct dce_dmcu_mask *dmcu_mask) 891 { 892 uint32_t psp_version = 0; 893 894 dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 895 896 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 897 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); 898 dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029); 899 dmcu_dce->base.psp_version = psp_version; 900 } 901 } 902 #endif 903 904 struct dmcu *dce_dmcu_create( 905 struct dc_context *ctx, 906 const struct dce_dmcu_registers *regs, 907 const struct dce_dmcu_shift *dmcu_shift, 908 const struct dce_dmcu_mask *dmcu_mask) 909 { 910 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 911 912 if (dmcu_dce == NULL) { 913 BREAK_TO_DEBUGGER(); 914 return NULL; 915 } 916 917 dce_dmcu_construct( 918 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 919 920 dmcu_dce->base.funcs = &dce_funcs; 921 922 return &dmcu_dce->base; 923 } 924 925 #if defined(CONFIG_DRM_AMD_DC_DCN) 926 struct dmcu *dcn10_dmcu_create( 927 struct dc_context *ctx, 928 const struct dce_dmcu_registers *regs, 929 const struct dce_dmcu_shift *dmcu_shift, 930 const struct dce_dmcu_mask *dmcu_mask) 931 { 932 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 933 934 if (dmcu_dce == NULL) { 935 BREAK_TO_DEBUGGER(); 936 return NULL; 937 } 938 939 dce_dmcu_construct( 940 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 941 942 dmcu_dce->base.funcs = &dcn10_funcs; 943 944 return &dmcu_dce->base; 945 } 946 947 struct dmcu *dcn20_dmcu_create( 948 struct dc_context *ctx, 949 const struct dce_dmcu_registers *regs, 950 const struct dce_dmcu_shift *dmcu_shift, 951 const struct dce_dmcu_mask *dmcu_mask) 952 { 953 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 954 955 if (dmcu_dce == NULL) { 956 BREAK_TO_DEBUGGER(); 957 return NULL; 958 } 959 960 dce_dmcu_construct( 961 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 962 963 dmcu_dce->base.funcs = &dcn20_funcs; 964 965 return &dmcu_dce->base; 966 } 967 968 struct dmcu *dcn21_dmcu_create( 969 struct dc_context *ctx, 970 const struct dce_dmcu_registers *regs, 971 const struct dce_dmcu_shift *dmcu_shift, 972 const struct dce_dmcu_mask *dmcu_mask) 973 { 974 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 975 976 if (dmcu_dce == NULL) { 977 BREAK_TO_DEBUGGER(); 978 return NULL; 979 } 980 981 dcn21_dmcu_construct( 982 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 983 984 dmcu_dce->base.funcs = &dcn21_funcs; 985 986 return &dmcu_dce->base; 987 } 988 #endif 989 990 void dce_dmcu_destroy(struct dmcu **dmcu) 991 { 992 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 993 994 kfree(dmcu_dce); 995 *dmcu = NULL; 996 } 997