1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "link_encoder.h" 28 #include "dce_dmcu.h" 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 #include "fixed32_32.h" 32 #include "dc.h" 33 34 #define TO_DCE_DMCU(dmcu)\ 35 container_of(dmcu, struct dce_dmcu, base) 36 37 #define REG(reg) \ 38 (dmcu_dce->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 43 44 #define CTX \ 45 dmcu_dce->base.ctx 46 47 /* PSR related commands */ 48 #define PSR_ENABLE 0x20 49 #define PSR_EXIT 0x21 50 #define PSR_SET 0x23 51 #define PSR_SET_WAITLOOP 0x31 52 #define MCP_INIT_DMCU 0x88 53 #define MCP_INIT_IRAM 0x89 54 #define MCP_DMCU_VERSION 0x90 55 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 56 57 static bool dce_dmcu_init(struct dmcu *dmcu) 58 { 59 // Do nothing 60 return true; 61 } 62 63 bool dce_dmcu_load_iram(struct dmcu *dmcu, 64 unsigned int start_offset, 65 const char *src, 66 unsigned int bytes) 67 { 68 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 69 unsigned int count = 0; 70 71 /* Enable write access to IRAM */ 72 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 73 IRAM_HOST_ACCESS_EN, 1, 74 IRAM_WR_ADDR_AUTO_INC, 1); 75 76 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 77 78 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 79 80 for (count = 0; count < bytes; count++) 81 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 82 83 /* Disable write access to IRAM to allow dynamic sleep state */ 84 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 85 IRAM_HOST_ACCESS_EN, 0, 86 IRAM_WR_ADDR_AUTO_INC, 0); 87 88 return true; 89 } 90 91 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 92 { 93 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 94 95 uint32_t psr_state_offset = 0xf0; 96 97 /* Enable write access to IRAM */ 98 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 99 100 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 101 102 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 103 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 104 105 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 106 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 107 108 /* Disable write access to IRAM after finished using IRAM 109 * in order to allow dynamic sleep state 110 */ 111 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 112 } 113 114 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 115 { 116 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 117 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 118 unsigned int dmcu_wait_reg_ready_interval = 100; 119 120 unsigned int retryCount; 121 uint32_t psr_state = 0; 122 123 /* waitDMCUReadyForCmd */ 124 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 125 dmcu_wait_reg_ready_interval, 126 dmcu_max_retry_on_wait_reg_ready); 127 128 /* setDMCUParam_Cmd */ 129 if (enable) 130 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 131 PSR_ENABLE); 132 else 133 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 134 PSR_EXIT); 135 136 /* notifyDMCUMsg */ 137 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 138 if (wait == true) { 139 for (retryCount = 0; retryCount <= 100; retryCount++) { 140 dce_get_dmcu_psr_state(dmcu, &psr_state); 141 if (enable) { 142 if (psr_state != 0) 143 break; 144 } else { 145 if (psr_state == 0) 146 break; 147 } 148 udelay(10); 149 } 150 } 151 } 152 153 static void dce_dmcu_setup_psr(struct dmcu *dmcu, 154 struct dc_link *link, 155 struct psr_context *psr_context) 156 { 157 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 158 159 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 160 unsigned int dmcu_wait_reg_ready_interval = 100; 161 162 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 163 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 164 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 165 166 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 167 psr_context->psrExitLinkTrainingRequired); 168 169 /* Enable static screen interrupts for PSR supported display */ 170 /* Disable the interrupt coming from other displays. */ 171 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 172 STATIC_SCREEN1_INT_TO_UC_EN, 0, 173 STATIC_SCREEN2_INT_TO_UC_EN, 0, 174 STATIC_SCREEN3_INT_TO_UC_EN, 0, 175 STATIC_SCREEN4_INT_TO_UC_EN, 0); 176 177 switch (psr_context->controllerId) { 178 /* Driver uses case 1 for unconfigured */ 179 case 1: 180 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 181 STATIC_SCREEN1_INT_TO_UC_EN, 1); 182 break; 183 case 2: 184 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 185 STATIC_SCREEN2_INT_TO_UC_EN, 1); 186 break; 187 case 3: 188 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 189 STATIC_SCREEN3_INT_TO_UC_EN, 1); 190 break; 191 case 4: 192 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 193 STATIC_SCREEN4_INT_TO_UC_EN, 1); 194 break; 195 case 5: 196 /* CZ/NL only has 4 CRTC!! 197 * really valid. 198 * There is no interrupt enable mask for these instances. 199 */ 200 break; 201 case 6: 202 /* CZ/NL only has 4 CRTC!! 203 * These are here because they are defined in HW regspec, 204 * but not really valid. There is no interrupt enable mask 205 * for these instances. 206 */ 207 break; 208 default: 209 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 210 STATIC_SCREEN1_INT_TO_UC_EN, 1); 211 break; 212 } 213 214 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 215 psr_context->sdpTransmitLineNumDeadline); 216 217 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) 218 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 219 220 /* waitDMCUReadyForCmd */ 221 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 222 dmcu_wait_reg_ready_interval, 223 dmcu_max_retry_on_wait_reg_ready); 224 225 /* setDMCUParam_PSRHostConfigData */ 226 masterCmdData1.u32All = 0; 227 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 228 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 229 masterCmdData1.bits.rfb_update_auto_en = 230 psr_context->rfb_update_auto_en; 231 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 232 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 233 masterCmdData1.bits.phy_type = psr_context->phyType; 234 masterCmdData1.bits.frame_cap_ind = 235 psr_context->psrFrameCaptureIndicationReq; 236 masterCmdData1.bits.aux_chan = psr_context->channel; 237 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 238 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 239 masterCmdData1.u32All); 240 241 masterCmdData2.u32All = 0; 242 masterCmdData2.bits.dig_fe = psr_context->engineId; 243 masterCmdData2.bits.dig_be = psr_context->transmitterId; 244 masterCmdData2.bits.skip_wait_for_pll_lock = 245 psr_context->skipPsrWaitForPllLock; 246 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 247 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 248 masterCmdData2.bits.num_of_controllers = 249 psr_context->numberOfControllers; 250 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 251 masterCmdData2.u32All); 252 253 masterCmdData3.u32All = 0; 254 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 255 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 256 masterCmdData3.u32All); 257 258 /* setDMCUParam_Cmd */ 259 REG_UPDATE(MASTER_COMM_CMD_REG, 260 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 261 262 /* notifyDMCUMsg */ 263 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 264 } 265 266 static void dce_psr_wait_loop( 267 struct dmcu *dmcu, 268 unsigned int wait_loop_number) 269 { 270 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 271 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 272 if (dmcu->cached_wait_loop_number == wait_loop_number) 273 return; 274 275 /* waitDMCUReadyForCmd */ 276 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 277 278 masterCmdData1.u32 = 0; 279 masterCmdData1.bits.wait_loop = wait_loop_number; 280 dmcu->cached_wait_loop_number = wait_loop_number; 281 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 282 283 /* setDMCUParam_Cmd */ 284 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 285 286 /* notifyDMCUMsg */ 287 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 288 } 289 290 static void dce_get_psr_wait_loop( 291 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 292 { 293 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 294 return; 295 } 296 297 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 298 static void dcn10_get_dmcu_state(struct dmcu *dmcu) 299 { 300 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 301 uint32_t dmcu_state_offset = 0xf6; 302 303 /* Enable write access to IRAM */ 304 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 305 IRAM_HOST_ACCESS_EN, 1, 306 IRAM_RD_ADDR_AUTO_INC, 1); 307 308 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 309 310 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 311 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset); 312 313 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 314 dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA); 315 316 /* Disable write access to IRAM to allow dynamic sleep state */ 317 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 318 IRAM_HOST_ACCESS_EN, 0, 319 IRAM_RD_ADDR_AUTO_INC, 0); 320 } 321 322 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 323 { 324 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 325 uint32_t dmcu_version_offset = 0xf1; 326 327 /* Clear scratch */ 328 REG_WRITE(DC_DMCU_SCRATCH, 0); 329 330 /* Enable write access to IRAM */ 331 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 332 IRAM_HOST_ACCESS_EN, 1, 333 IRAM_RD_ADDR_AUTO_INC, 1); 334 335 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 336 337 /* Write address to IRAM_RD_ADDR and read from DATA register */ 338 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 339 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 340 dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 341 REG_READ(DMCU_IRAM_RD_DATA)); 342 dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA); 343 dmcu->dmcu_version.day = REG_READ(DMCU_IRAM_RD_DATA); 344 345 /* Disable write access to IRAM to allow dynamic sleep state */ 346 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 347 IRAM_HOST_ACCESS_EN, 0, 348 IRAM_RD_ADDR_AUTO_INC, 0); 349 350 /* Send MCP command message to DMCU to get version reply from FW. 351 * We expect this version should match the one in IRAM, otherwise 352 * something is wrong with DMCU and we should fail and disable UC. 353 */ 354 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 355 356 /* Set command to get DMCU version from microcontroller */ 357 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 358 MCP_DMCU_VERSION); 359 360 /* Notify microcontroller of new command */ 361 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 362 363 /* Ensure command has been executed before continuing */ 364 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 365 366 /* Somehow version does not match, so fail and return version 0 */ 367 if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH)) 368 dmcu->dmcu_version.interface_version = 0; 369 } 370 371 static bool dcn10_dmcu_init(struct dmcu *dmcu) 372 { 373 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 374 375 /* DMCU FW should populate the scratch register if running */ 376 if (REG_READ(DC_DMCU_SCRATCH) == 0) 377 return false; 378 379 /* Check state is uninitialized */ 380 dcn10_get_dmcu_state(dmcu); 381 382 /* If microcontroller is already initialized, do nothing */ 383 if (dmcu->dmcu_state == DMCU_RUNNING) 384 return true; 385 386 /* Retrieve and cache the DMCU firmware version. */ 387 dcn10_get_dmcu_version(dmcu); 388 389 /* Check interface version to confirm firmware is loaded and running */ 390 if (dmcu->dmcu_version.interface_version == 0) 391 return false; 392 393 /* Wait until microcontroller is ready to process interrupt */ 394 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 395 396 /* Set initialized ramping boundary value */ 397 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 398 399 /* Set command to initialize microcontroller */ 400 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 401 MCP_INIT_DMCU); 402 403 /* Notify microcontroller of new command */ 404 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 405 406 /* Ensure command has been executed before continuing */ 407 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 408 409 // Check state is initialized 410 dcn10_get_dmcu_state(dmcu); 411 412 // If microcontroller is not in running state, fail 413 if (dmcu->dmcu_state != DMCU_RUNNING) 414 return false; 415 416 return true; 417 } 418 419 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 420 unsigned int start_offset, 421 const char *src, 422 unsigned int bytes) 423 { 424 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 425 unsigned int count = 0; 426 427 /* If microcontroller is not running, do nothing */ 428 if (dmcu->dmcu_state != DMCU_RUNNING) 429 return false; 430 431 /* Enable write access to IRAM */ 432 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 433 IRAM_HOST_ACCESS_EN, 1, 434 IRAM_WR_ADDR_AUTO_INC, 1); 435 436 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 437 438 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 439 440 for (count = 0; count < bytes; count++) 441 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 442 443 /* Disable write access to IRAM to allow dynamic sleep state */ 444 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 445 IRAM_HOST_ACCESS_EN, 0, 446 IRAM_WR_ADDR_AUTO_INC, 0); 447 448 /* Wait until microcontroller is ready to process interrupt */ 449 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 450 451 /* Set command to signal IRAM is loaded and to initialize IRAM */ 452 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 453 MCP_INIT_IRAM); 454 455 /* Notify microcontroller of new command */ 456 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 457 458 /* Ensure command has been executed before continuing */ 459 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 460 461 return true; 462 } 463 464 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 465 { 466 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 467 468 uint32_t psr_state_offset = 0xf0; 469 470 /* If microcontroller is not running, do nothing */ 471 if (dmcu->dmcu_state != DMCU_RUNNING) 472 return; 473 474 /* Enable write access to IRAM */ 475 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 476 477 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 478 479 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 480 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 481 482 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 483 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 484 485 /* Disable write access to IRAM after finished using IRAM 486 * in order to allow dynamic sleep state 487 */ 488 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 489 } 490 491 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 492 { 493 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 494 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 495 unsigned int dmcu_wait_reg_ready_interval = 100; 496 497 unsigned int retryCount; 498 uint32_t psr_state = 0; 499 500 /* If microcontroller is not running, do nothing */ 501 if (dmcu->dmcu_state != DMCU_RUNNING) 502 return; 503 504 /* waitDMCUReadyForCmd */ 505 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 506 dmcu_wait_reg_ready_interval, 507 dmcu_max_retry_on_wait_reg_ready); 508 509 /* setDMCUParam_Cmd */ 510 if (enable) 511 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 512 PSR_ENABLE); 513 else 514 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 515 PSR_EXIT); 516 517 /* notifyDMCUMsg */ 518 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 519 520 /* Below loops 1000 x 500us = 500 ms. 521 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 522 * least a few frames. Should never hit the max retry assert below. 523 */ 524 if (wait == true) { 525 for (retryCount = 0; retryCount <= 1000; retryCount++) { 526 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 527 if (enable) { 528 if (psr_state != 0) 529 break; 530 } else { 531 if (psr_state == 0) 532 break; 533 } 534 udelay(500); 535 } 536 537 /* assert if max retry hit */ 538 ASSERT(retryCount <= 1000); 539 } 540 } 541 542 static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, 543 struct dc_link *link, 544 struct psr_context *psr_context) 545 { 546 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 547 548 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 549 unsigned int dmcu_wait_reg_ready_interval = 100; 550 551 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 552 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 553 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 554 555 /* If microcontroller is not running, do nothing */ 556 if (dmcu->dmcu_state != DMCU_RUNNING) 557 return; 558 559 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 560 psr_context->psrExitLinkTrainingRequired); 561 562 /* Enable static screen interrupts for PSR supported display */ 563 /* Disable the interrupt coming from other displays. */ 564 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 565 STATIC_SCREEN1_INT_TO_UC_EN, 0, 566 STATIC_SCREEN2_INT_TO_UC_EN, 0, 567 STATIC_SCREEN3_INT_TO_UC_EN, 0, 568 STATIC_SCREEN4_INT_TO_UC_EN, 0); 569 570 switch (psr_context->controllerId) { 571 /* Driver uses case 1 for unconfigured */ 572 case 1: 573 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 574 STATIC_SCREEN1_INT_TO_UC_EN, 1); 575 break; 576 case 2: 577 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 578 STATIC_SCREEN2_INT_TO_UC_EN, 1); 579 break; 580 case 3: 581 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 582 STATIC_SCREEN3_INT_TO_UC_EN, 1); 583 break; 584 case 4: 585 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 586 STATIC_SCREEN4_INT_TO_UC_EN, 1); 587 break; 588 case 5: 589 /* CZ/NL only has 4 CRTC!! 590 * really valid. 591 * There is no interrupt enable mask for these instances. 592 */ 593 break; 594 case 6: 595 /* CZ/NL only has 4 CRTC!! 596 * These are here because they are defined in HW regspec, 597 * but not really valid. There is no interrupt enable mask 598 * for these instances. 599 */ 600 break; 601 default: 602 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 603 STATIC_SCREEN1_INT_TO_UC_EN, 1); 604 break; 605 } 606 607 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 608 psr_context->sdpTransmitLineNumDeadline); 609 610 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) 611 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 612 613 /* waitDMCUReadyForCmd */ 614 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 615 dmcu_wait_reg_ready_interval, 616 dmcu_max_retry_on_wait_reg_ready); 617 618 /* setDMCUParam_PSRHostConfigData */ 619 masterCmdData1.u32All = 0; 620 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 621 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 622 masterCmdData1.bits.rfb_update_auto_en = 623 psr_context->rfb_update_auto_en; 624 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 625 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 626 masterCmdData1.bits.phy_type = psr_context->phyType; 627 masterCmdData1.bits.frame_cap_ind = 628 psr_context->psrFrameCaptureIndicationReq; 629 masterCmdData1.bits.aux_chan = psr_context->channel; 630 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 631 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 632 masterCmdData1.u32All); 633 634 masterCmdData2.u32All = 0; 635 masterCmdData2.bits.dig_fe = psr_context->engineId; 636 masterCmdData2.bits.dig_be = psr_context->transmitterId; 637 masterCmdData2.bits.skip_wait_for_pll_lock = 638 psr_context->skipPsrWaitForPllLock; 639 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 640 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 641 masterCmdData2.bits.num_of_controllers = 642 psr_context->numberOfControllers; 643 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 644 masterCmdData2.u32All); 645 646 masterCmdData3.u32All = 0; 647 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 648 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 649 masterCmdData3.u32All); 650 651 /* setDMCUParam_Cmd */ 652 REG_UPDATE(MASTER_COMM_CMD_REG, 653 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 654 655 /* notifyDMCUMsg */ 656 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 657 } 658 659 static void dcn10_psr_wait_loop( 660 struct dmcu *dmcu, 661 unsigned int wait_loop_number) 662 { 663 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 664 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 665 666 /* If microcontroller is not running, do nothing */ 667 if (dmcu->dmcu_state != DMCU_RUNNING) 668 return; 669 670 if (wait_loop_number != 0) { 671 /* waitDMCUReadyForCmd */ 672 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 673 674 masterCmdData1.u32 = 0; 675 masterCmdData1.bits.wait_loop = wait_loop_number; 676 dmcu->cached_wait_loop_number = wait_loop_number; 677 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 678 679 /* setDMCUParam_Cmd */ 680 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 681 682 /* notifyDMCUMsg */ 683 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 684 } 685 } 686 687 static void dcn10_get_psr_wait_loop( 688 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 689 { 690 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 691 return; 692 } 693 694 #endif 695 696 static const struct dmcu_funcs dce_funcs = { 697 .dmcu_init = dce_dmcu_init, 698 .load_iram = dce_dmcu_load_iram, 699 .set_psr_enable = dce_dmcu_set_psr_enable, 700 .setup_psr = dce_dmcu_setup_psr, 701 .get_psr_state = dce_get_dmcu_psr_state, 702 .set_psr_wait_loop = dce_psr_wait_loop, 703 .get_psr_wait_loop = dce_get_psr_wait_loop 704 }; 705 706 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 707 static const struct dmcu_funcs dcn10_funcs = { 708 .dmcu_init = dcn10_dmcu_init, 709 .load_iram = dcn10_dmcu_load_iram, 710 .set_psr_enable = dcn10_dmcu_set_psr_enable, 711 .setup_psr = dcn10_dmcu_setup_psr, 712 .get_psr_state = dcn10_get_dmcu_psr_state, 713 .set_psr_wait_loop = dcn10_psr_wait_loop, 714 .get_psr_wait_loop = dcn10_get_psr_wait_loop 715 }; 716 #endif 717 718 static void dce_dmcu_construct( 719 struct dce_dmcu *dmcu_dce, 720 struct dc_context *ctx, 721 const struct dce_dmcu_registers *regs, 722 const struct dce_dmcu_shift *dmcu_shift, 723 const struct dce_dmcu_mask *dmcu_mask) 724 { 725 struct dmcu *base = &dmcu_dce->base; 726 727 base->ctx = ctx; 728 base->funcs = &dce_funcs; 729 base->cached_wait_loop_number = 0; 730 731 dmcu_dce->regs = regs; 732 dmcu_dce->dmcu_shift = dmcu_shift; 733 dmcu_dce->dmcu_mask = dmcu_mask; 734 } 735 736 struct dmcu *dce_dmcu_create( 737 struct dc_context *ctx, 738 const struct dce_dmcu_registers *regs, 739 const struct dce_dmcu_shift *dmcu_shift, 740 const struct dce_dmcu_mask *dmcu_mask) 741 { 742 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 743 744 if (dmcu_dce == NULL) { 745 BREAK_TO_DEBUGGER(); 746 return NULL; 747 } 748 749 dce_dmcu_construct( 750 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 751 752 dmcu_dce->base.funcs = &dce_funcs; 753 754 return &dmcu_dce->base; 755 } 756 757 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 758 struct dmcu *dcn10_dmcu_create( 759 struct dc_context *ctx, 760 const struct dce_dmcu_registers *regs, 761 const struct dce_dmcu_shift *dmcu_shift, 762 const struct dce_dmcu_mask *dmcu_mask) 763 { 764 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 765 766 if (dmcu_dce == NULL) { 767 BREAK_TO_DEBUGGER(); 768 return NULL; 769 } 770 771 dce_dmcu_construct( 772 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 773 774 dmcu_dce->base.funcs = &dcn10_funcs; 775 776 return &dmcu_dce->base; 777 } 778 #endif 779 780 void dce_dmcu_destroy(struct dmcu **dmcu) 781 { 782 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 783 784 kfree(dmcu_dce); 785 *dmcu = NULL; 786 } 787