1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "link_encoder.h" 28 #include "dce_dmcu.h" 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 #include "fixed31_32.h" 32 #include "dc.h" 33 34 #define TO_DCE_DMCU(dmcu)\ 35 container_of(dmcu, struct dce_dmcu, base) 36 37 #define REG(reg) \ 38 (dmcu_dce->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 43 44 #define CTX \ 45 dmcu_dce->base.ctx 46 47 /* PSR related commands */ 48 #define PSR_ENABLE 0x20 49 #define PSR_EXIT 0x21 50 #define PSR_SET 0x23 51 #define PSR_SET_WAITLOOP 0x31 52 #define MCP_INIT_DMCU 0x88 53 #define MCP_INIT_IRAM 0x89 54 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 55 56 static bool dce_dmcu_init(struct dmcu *dmcu) 57 { 58 // Do nothing 59 return true; 60 } 61 62 bool dce_dmcu_load_iram(struct dmcu *dmcu, 63 unsigned int start_offset, 64 const char *src, 65 unsigned int bytes) 66 { 67 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 68 unsigned int count = 0; 69 70 /* Enable write access to IRAM */ 71 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 72 IRAM_HOST_ACCESS_EN, 1, 73 IRAM_WR_ADDR_AUTO_INC, 1); 74 75 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 76 77 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 78 79 for (count = 0; count < bytes; count++) 80 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 81 82 /* Disable write access to IRAM to allow dynamic sleep state */ 83 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 84 IRAM_HOST_ACCESS_EN, 0, 85 IRAM_WR_ADDR_AUTO_INC, 0); 86 87 return true; 88 } 89 90 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 91 { 92 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 93 94 uint32_t psr_state_offset = 0xf0; 95 96 /* Enable write access to IRAM */ 97 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 98 99 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 100 101 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 102 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 103 104 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 105 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 106 107 /* Disable write access to IRAM after finished using IRAM 108 * in order to allow dynamic sleep state 109 */ 110 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 111 } 112 113 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 114 { 115 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 116 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 117 unsigned int dmcu_wait_reg_ready_interval = 100; 118 119 unsigned int retryCount; 120 uint32_t psr_state = 0; 121 122 /* waitDMCUReadyForCmd */ 123 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 124 dmcu_wait_reg_ready_interval, 125 dmcu_max_retry_on_wait_reg_ready); 126 127 /* setDMCUParam_Cmd */ 128 if (enable) 129 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 130 PSR_ENABLE); 131 else 132 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 133 PSR_EXIT); 134 135 /* notifyDMCUMsg */ 136 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 137 if (wait == true) { 138 for (retryCount = 0; retryCount <= 100; retryCount++) { 139 dce_get_dmcu_psr_state(dmcu, &psr_state); 140 if (enable) { 141 if (psr_state != 0) 142 break; 143 } else { 144 if (psr_state == 0) 145 break; 146 } 147 udelay(10); 148 } 149 } 150 } 151 152 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 153 struct dc_link *link, 154 struct psr_context *psr_context) 155 { 156 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 157 158 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 159 unsigned int dmcu_wait_reg_ready_interval = 100; 160 161 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 162 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 163 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 164 165 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 166 psr_context->psrExitLinkTrainingRequired); 167 168 /* Enable static screen interrupts for PSR supported display */ 169 /* Disable the interrupt coming from other displays. */ 170 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 171 STATIC_SCREEN1_INT_TO_UC_EN, 0, 172 STATIC_SCREEN2_INT_TO_UC_EN, 0, 173 STATIC_SCREEN3_INT_TO_UC_EN, 0, 174 STATIC_SCREEN4_INT_TO_UC_EN, 0); 175 176 switch (psr_context->controllerId) { 177 /* Driver uses case 1 for unconfigured */ 178 case 1: 179 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 180 STATIC_SCREEN1_INT_TO_UC_EN, 1); 181 break; 182 case 2: 183 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 184 STATIC_SCREEN2_INT_TO_UC_EN, 1); 185 break; 186 case 3: 187 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 188 STATIC_SCREEN3_INT_TO_UC_EN, 1); 189 break; 190 case 4: 191 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 192 STATIC_SCREEN4_INT_TO_UC_EN, 1); 193 break; 194 case 5: 195 /* CZ/NL only has 4 CRTC!! 196 * really valid. 197 * There is no interrupt enable mask for these instances. 198 */ 199 break; 200 case 6: 201 /* CZ/NL only has 4 CRTC!! 202 * These are here because they are defined in HW regspec, 203 * but not really valid. There is no interrupt enable mask 204 * for these instances. 205 */ 206 break; 207 default: 208 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 209 STATIC_SCREEN1_INT_TO_UC_EN, 1); 210 break; 211 } 212 213 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 214 psr_context->sdpTransmitLineNumDeadline); 215 216 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) 217 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 218 219 /* waitDMCUReadyForCmd */ 220 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 221 dmcu_wait_reg_ready_interval, 222 dmcu_max_retry_on_wait_reg_ready); 223 224 /* setDMCUParam_PSRHostConfigData */ 225 masterCmdData1.u32All = 0; 226 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 227 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 228 masterCmdData1.bits.rfb_update_auto_en = 229 psr_context->rfb_update_auto_en; 230 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 231 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 232 masterCmdData1.bits.phy_type = psr_context->phyType; 233 masterCmdData1.bits.frame_cap_ind = 234 psr_context->psrFrameCaptureIndicationReq; 235 masterCmdData1.bits.aux_chan = psr_context->channel; 236 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 237 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 238 masterCmdData1.u32All); 239 240 masterCmdData2.u32All = 0; 241 masterCmdData2.bits.dig_fe = psr_context->engineId; 242 masterCmdData2.bits.dig_be = psr_context->transmitterId; 243 masterCmdData2.bits.skip_wait_for_pll_lock = 244 psr_context->skipPsrWaitForPllLock; 245 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 246 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 247 masterCmdData2.bits.num_of_controllers = 248 psr_context->numberOfControllers; 249 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 250 masterCmdData2.u32All); 251 252 masterCmdData3.u32All = 0; 253 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 254 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 255 masterCmdData3.u32All); 256 257 /* setDMCUParam_Cmd */ 258 REG_UPDATE(MASTER_COMM_CMD_REG, 259 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 260 261 /* notifyDMCUMsg */ 262 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 263 264 return true; 265 } 266 267 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 268 { 269 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 270 unsigned int dmcu_uc_reset; 271 272 /* microcontroller is not running */ 273 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 274 275 /* DMCU is not running */ 276 if (dmcu_uc_reset) 277 return false; 278 279 return true; 280 } 281 282 static void dce_psr_wait_loop( 283 struct dmcu *dmcu, 284 unsigned int wait_loop_number) 285 { 286 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 287 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 288 289 if (dmcu->cached_wait_loop_number == wait_loop_number) 290 return; 291 292 /* DMCU is not running */ 293 if (!dce_is_dmcu_initialized(dmcu)) 294 return; 295 296 /* waitDMCUReadyForCmd */ 297 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 298 299 masterCmdData1.u32 = 0; 300 masterCmdData1.bits.wait_loop = wait_loop_number; 301 dmcu->cached_wait_loop_number = wait_loop_number; 302 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 303 304 /* setDMCUParam_Cmd */ 305 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 306 307 /* notifyDMCUMsg */ 308 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 309 } 310 311 static void dce_get_psr_wait_loop( 312 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 313 { 314 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 315 return; 316 } 317 318 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 319 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 320 { 321 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 322 uint32_t dmcu_version_offset = 0xf1; 323 324 /* Enable write access to IRAM */ 325 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 326 IRAM_HOST_ACCESS_EN, 1, 327 IRAM_RD_ADDR_AUTO_INC, 1); 328 329 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 330 331 /* Write address to IRAM_RD_ADDR and read from DATA register */ 332 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 333 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 334 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 335 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 336 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 337 REG_READ(DMCU_IRAM_RD_DATA)); 338 339 /* Disable write access to IRAM to allow dynamic sleep state */ 340 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 341 IRAM_HOST_ACCESS_EN, 0, 342 IRAM_RD_ADDR_AUTO_INC, 0); 343 } 344 345 static bool dcn10_dmcu_init(struct dmcu *dmcu) 346 { 347 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 348 bool status = false; 349 350 /* Definition of DC_DMCU_SCRATCH 351 * 0 : firmare not loaded 352 * 1 : PSP load DMCU FW but not initialized 353 * 2 : Firmware already initialized 354 */ 355 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 356 357 switch (dmcu->dmcu_state) { 358 case DMCU_UNLOADED: 359 status = false; 360 break; 361 case DMCU_LOADED_UNINITIALIZED: 362 /* Wait until microcontroller is ready to process interrupt */ 363 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 364 365 /* Set initialized ramping boundary value */ 366 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 367 368 /* Set command to initialize microcontroller */ 369 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 370 MCP_INIT_DMCU); 371 372 /* Notify microcontroller of new command */ 373 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 374 375 /* Ensure command has been executed before continuing */ 376 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 377 378 // Check state is initialized 379 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 380 381 // If microcontroller is not in running state, fail 382 if (dmcu->dmcu_state == DMCU_RUNNING) { 383 /* Retrieve and cache the DMCU firmware version. */ 384 dcn10_get_dmcu_version(dmcu); 385 status = true; 386 } else 387 status = false; 388 389 break; 390 case DMCU_RUNNING: 391 status = true; 392 break; 393 default: 394 status = false; 395 break; 396 } 397 398 return status; 399 } 400 401 402 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 403 unsigned int start_offset, 404 const char *src, 405 unsigned int bytes) 406 { 407 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 408 unsigned int count = 0; 409 410 /* If microcontroller is not running, do nothing */ 411 if (dmcu->dmcu_state != DMCU_RUNNING) 412 return false; 413 414 /* Enable write access to IRAM */ 415 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 416 IRAM_HOST_ACCESS_EN, 1, 417 IRAM_WR_ADDR_AUTO_INC, 1); 418 419 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 420 421 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 422 423 for (count = 0; count < bytes; count++) 424 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 425 426 /* Disable write access to IRAM to allow dynamic sleep state */ 427 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 428 IRAM_HOST_ACCESS_EN, 0, 429 IRAM_WR_ADDR_AUTO_INC, 0); 430 431 /* Wait until microcontroller is ready to process interrupt */ 432 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 433 434 /* Set command to signal IRAM is loaded and to initialize IRAM */ 435 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 436 MCP_INIT_IRAM); 437 438 /* Notify microcontroller of new command */ 439 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 440 441 /* Ensure command has been executed before continuing */ 442 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 443 444 return true; 445 } 446 447 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 448 { 449 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 450 451 uint32_t psr_state_offset = 0xf0; 452 453 /* If microcontroller is not running, do nothing */ 454 if (dmcu->dmcu_state != DMCU_RUNNING) 455 return; 456 457 /* Enable write access to IRAM */ 458 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 459 460 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 461 462 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 463 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 464 465 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 466 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 467 468 /* Disable write access to IRAM after finished using IRAM 469 * in order to allow dynamic sleep state 470 */ 471 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 472 } 473 474 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 475 { 476 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 477 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 478 unsigned int dmcu_wait_reg_ready_interval = 100; 479 480 unsigned int retryCount; 481 uint32_t psr_state = 0; 482 483 /* If microcontroller is not running, do nothing */ 484 if (dmcu->dmcu_state != DMCU_RUNNING) 485 return; 486 487 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 488 if (psr_state == 0 && !enable) 489 return; 490 /* waitDMCUReadyForCmd */ 491 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 492 dmcu_wait_reg_ready_interval, 493 dmcu_max_retry_on_wait_reg_ready); 494 495 /* setDMCUParam_Cmd */ 496 if (enable) 497 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 498 PSR_ENABLE); 499 else 500 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 501 PSR_EXIT); 502 503 /* notifyDMCUMsg */ 504 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 505 506 /* Below loops 1000 x 500us = 500 ms. 507 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 508 * least a few frames. Should never hit the max retry assert below. 509 */ 510 if (wait == true) { 511 for (retryCount = 0; retryCount <= 1000; retryCount++) { 512 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 513 if (enable) { 514 if (psr_state != 0) 515 break; 516 } else { 517 if (psr_state == 0) 518 break; 519 } 520 udelay(500); 521 } 522 523 /* assert if max retry hit */ 524 if (retryCount >= 1000) 525 ASSERT(0); 526 } 527 } 528 529 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 530 struct dc_link *link, 531 struct psr_context *psr_context) 532 { 533 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 534 535 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 536 unsigned int dmcu_wait_reg_ready_interval = 100; 537 538 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 539 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 540 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 541 542 /* If microcontroller is not running, do nothing */ 543 if (dmcu->dmcu_state != DMCU_RUNNING) 544 return false; 545 546 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 547 psr_context->psrExitLinkTrainingRequired); 548 549 /* Enable static screen interrupts for PSR supported display */ 550 /* Disable the interrupt coming from other displays. */ 551 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 552 STATIC_SCREEN1_INT_TO_UC_EN, 0, 553 STATIC_SCREEN2_INT_TO_UC_EN, 0, 554 STATIC_SCREEN3_INT_TO_UC_EN, 0, 555 STATIC_SCREEN4_INT_TO_UC_EN, 0); 556 557 switch (psr_context->controllerId) { 558 /* Driver uses case 1 for unconfigured */ 559 case 1: 560 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 561 STATIC_SCREEN1_INT_TO_UC_EN, 1); 562 break; 563 case 2: 564 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 565 STATIC_SCREEN2_INT_TO_UC_EN, 1); 566 break; 567 case 3: 568 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 569 STATIC_SCREEN3_INT_TO_UC_EN, 1); 570 break; 571 case 4: 572 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 573 STATIC_SCREEN4_INT_TO_UC_EN, 1); 574 break; 575 case 5: 576 /* CZ/NL only has 4 CRTC!! 577 * really valid. 578 * There is no interrupt enable mask for these instances. 579 */ 580 break; 581 case 6: 582 /* CZ/NL only has 4 CRTC!! 583 * These are here because they are defined in HW regspec, 584 * but not really valid. There is no interrupt enable mask 585 * for these instances. 586 */ 587 break; 588 default: 589 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 590 STATIC_SCREEN1_INT_TO_UC_EN, 1); 591 break; 592 } 593 594 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 595 psr_context->sdpTransmitLineNumDeadline); 596 597 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) 598 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 599 600 /* waitDMCUReadyForCmd */ 601 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 602 dmcu_wait_reg_ready_interval, 603 dmcu_max_retry_on_wait_reg_ready); 604 605 /* setDMCUParam_PSRHostConfigData */ 606 masterCmdData1.u32All = 0; 607 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 608 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 609 masterCmdData1.bits.rfb_update_auto_en = 610 psr_context->rfb_update_auto_en; 611 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 612 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 613 masterCmdData1.bits.phy_type = psr_context->phyType; 614 masterCmdData1.bits.frame_cap_ind = 615 psr_context->psrFrameCaptureIndicationReq; 616 masterCmdData1.bits.aux_chan = psr_context->channel; 617 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 618 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 619 masterCmdData1.u32All); 620 621 masterCmdData2.u32All = 0; 622 masterCmdData2.bits.dig_fe = psr_context->engineId; 623 masterCmdData2.bits.dig_be = psr_context->transmitterId; 624 masterCmdData2.bits.skip_wait_for_pll_lock = 625 psr_context->skipPsrWaitForPllLock; 626 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 627 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 628 masterCmdData2.bits.num_of_controllers = 629 psr_context->numberOfControllers; 630 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 631 masterCmdData2.u32All); 632 633 masterCmdData3.u32All = 0; 634 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 635 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 636 masterCmdData3.u32All); 637 638 /* setDMCUParam_Cmd */ 639 REG_UPDATE(MASTER_COMM_CMD_REG, 640 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 641 642 /* notifyDMCUMsg */ 643 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 644 645 /* waitDMCUReadyForCmd */ 646 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 647 648 return true; 649 } 650 651 static void dcn10_psr_wait_loop( 652 struct dmcu *dmcu, 653 unsigned int wait_loop_number) 654 { 655 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 656 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 657 658 /* If microcontroller is not running, do nothing */ 659 if (dmcu->dmcu_state != DMCU_RUNNING) 660 return; 661 662 if (wait_loop_number != 0) { 663 /* waitDMCUReadyForCmd */ 664 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 665 666 masterCmdData1.u32 = 0; 667 masterCmdData1.bits.wait_loop = wait_loop_number; 668 dmcu->cached_wait_loop_number = wait_loop_number; 669 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 670 671 /* setDMCUParam_Cmd */ 672 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 673 674 /* notifyDMCUMsg */ 675 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 676 } 677 } 678 679 static void dcn10_get_psr_wait_loop( 680 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 681 { 682 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 683 return; 684 } 685 686 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 687 { 688 /* microcontroller is not running */ 689 if (dmcu->dmcu_state != DMCU_RUNNING) 690 return false; 691 return true; 692 } 693 694 #endif 695 696 static const struct dmcu_funcs dce_funcs = { 697 .dmcu_init = dce_dmcu_init, 698 .load_iram = dce_dmcu_load_iram, 699 .set_psr_enable = dce_dmcu_set_psr_enable, 700 .setup_psr = dce_dmcu_setup_psr, 701 .get_psr_state = dce_get_dmcu_psr_state, 702 .set_psr_wait_loop = dce_psr_wait_loop, 703 .get_psr_wait_loop = dce_get_psr_wait_loop, 704 .is_dmcu_initialized = dce_is_dmcu_initialized 705 }; 706 707 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 708 static const struct dmcu_funcs dcn10_funcs = { 709 .dmcu_init = dcn10_dmcu_init, 710 .load_iram = dcn10_dmcu_load_iram, 711 .set_psr_enable = dcn10_dmcu_set_psr_enable, 712 .setup_psr = dcn10_dmcu_setup_psr, 713 .get_psr_state = dcn10_get_dmcu_psr_state, 714 .set_psr_wait_loop = dcn10_psr_wait_loop, 715 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 716 .is_dmcu_initialized = dcn10_is_dmcu_initialized 717 }; 718 #endif 719 720 static void dce_dmcu_construct( 721 struct dce_dmcu *dmcu_dce, 722 struct dc_context *ctx, 723 const struct dce_dmcu_registers *regs, 724 const struct dce_dmcu_shift *dmcu_shift, 725 const struct dce_dmcu_mask *dmcu_mask) 726 { 727 struct dmcu *base = &dmcu_dce->base; 728 729 base->ctx = ctx; 730 base->funcs = &dce_funcs; 731 base->cached_wait_loop_number = 0; 732 733 dmcu_dce->regs = regs; 734 dmcu_dce->dmcu_shift = dmcu_shift; 735 dmcu_dce->dmcu_mask = dmcu_mask; 736 } 737 738 struct dmcu *dce_dmcu_create( 739 struct dc_context *ctx, 740 const struct dce_dmcu_registers *regs, 741 const struct dce_dmcu_shift *dmcu_shift, 742 const struct dce_dmcu_mask *dmcu_mask) 743 { 744 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 745 746 if (dmcu_dce == NULL) { 747 BREAK_TO_DEBUGGER(); 748 return NULL; 749 } 750 751 dce_dmcu_construct( 752 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 753 754 dmcu_dce->base.funcs = &dce_funcs; 755 756 return &dmcu_dce->base; 757 } 758 759 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 760 struct dmcu *dcn10_dmcu_create( 761 struct dc_context *ctx, 762 const struct dce_dmcu_registers *regs, 763 const struct dce_dmcu_shift *dmcu_shift, 764 const struct dce_dmcu_mask *dmcu_mask) 765 { 766 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 767 768 if (dmcu_dce == NULL) { 769 BREAK_TO_DEBUGGER(); 770 return NULL; 771 } 772 773 dce_dmcu_construct( 774 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 775 776 dmcu_dce->base.funcs = &dcn10_funcs; 777 778 return &dmcu_dce->base; 779 } 780 #endif 781 782 void dce_dmcu_destroy(struct dmcu **dmcu) 783 { 784 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 785 786 kfree(dmcu_dce); 787 *dmcu = NULL; 788 } 789