1 /*
2  * Copyright 2012-16 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "core_types.h"
27 #include "link_encoder.h"
28 #include "dce_dmcu.h"
29 #include "dm_services.h"
30 #include "reg_helper.h"
31 #include "fixed31_32.h"
32 #include "dc.h"
33 
34 #define TO_DCE_DMCU(dmcu)\
35 	container_of(dmcu, struct dce_dmcu, base)
36 
37 #define REG(reg) \
38 	(dmcu_dce->regs->reg)
39 
40 #undef FN
41 #define FN(reg_name, field_name) \
42 	dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
43 
44 #define CTX \
45 	dmcu_dce->base.ctx
46 
47 /* PSR related commands */
48 #define PSR_ENABLE 0x20
49 #define PSR_EXIT 0x21
50 #define PSR_SET 0x23
51 #define PSR_SET_WAITLOOP 0x31
52 #define MCP_INIT_DMCU 0x88
53 #define MCP_INIT_IRAM 0x89
54 #define MCP_SYNC_PHY_LOCK 0x90
55 #define MCP_SYNC_PHY_UNLOCK 0x91
56 #define MCP_BL_SET_PWM_FRAC 0x6A  /* Enable or disable Fractional PWM */
57 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
58 
59 static bool dce_dmcu_init(struct dmcu *dmcu)
60 {
61 	// Do nothing
62 	return true;
63 }
64 
65 bool dce_dmcu_load_iram(struct dmcu *dmcu,
66 		unsigned int start_offset,
67 		const char *src,
68 		unsigned int bytes)
69 {
70 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
71 	unsigned int count = 0;
72 
73 	/* Enable write access to IRAM */
74 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
75 			IRAM_HOST_ACCESS_EN, 1,
76 			IRAM_WR_ADDR_AUTO_INC, 1);
77 
78 	REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
79 
80 	REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
81 
82 	for (count = 0; count < bytes; count++)
83 		REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
84 
85 	/* Disable write access to IRAM to allow dynamic sleep state */
86 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
87 			IRAM_HOST_ACCESS_EN, 0,
88 			IRAM_WR_ADDR_AUTO_INC, 0);
89 
90 	return true;
91 }
92 
93 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
94 {
95 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
96 
97 	uint32_t psr_state_offset = 0xf0;
98 
99 	/* Enable write access to IRAM */
100 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
101 
102 	REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
103 
104 	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
105 	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
106 
107 	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
108 	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
109 
110 	/* Disable write access to IRAM after finished using IRAM
111 	 * in order to allow dynamic sleep state
112 	 */
113 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
114 }
115 
116 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
117 {
118 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
119 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
120 	unsigned int dmcu_wait_reg_ready_interval = 100;
121 
122 	unsigned int retryCount;
123 	uint32_t psr_state = 0;
124 
125 	/* waitDMCUReadyForCmd */
126 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
127 				dmcu_wait_reg_ready_interval,
128 				dmcu_max_retry_on_wait_reg_ready);
129 
130 	/* setDMCUParam_Cmd */
131 	if (enable)
132 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
133 				PSR_ENABLE);
134 	else
135 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
136 				PSR_EXIT);
137 
138 	/* notifyDMCUMsg */
139 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
140 	if (wait == true) {
141 		for (retryCount = 0; retryCount <= 100; retryCount++) {
142 			dce_get_dmcu_psr_state(dmcu, &psr_state);
143 			if (enable) {
144 				if (psr_state != 0)
145 					break;
146 			} else {
147 				if (psr_state == 0)
148 					break;
149 			}
150 			udelay(10);
151 		}
152 	}
153 }
154 
155 static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
156 		struct dc_link *link,
157 		struct psr_context *psr_context)
158 {
159 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
160 
161 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
162 	unsigned int dmcu_wait_reg_ready_interval = 100;
163 
164 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
165 	union dce_dmcu_psr_config_data_reg2 masterCmdData2;
166 	union dce_dmcu_psr_config_data_reg3 masterCmdData3;
167 
168 	link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
169 			psr_context->psrExitLinkTrainingRequired);
170 
171 	/* Enable static screen interrupts for PSR supported display */
172 	/* Disable the interrupt coming from other displays. */
173 	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
174 			STATIC_SCREEN1_INT_TO_UC_EN, 0,
175 			STATIC_SCREEN2_INT_TO_UC_EN, 0,
176 			STATIC_SCREEN3_INT_TO_UC_EN, 0,
177 			STATIC_SCREEN4_INT_TO_UC_EN, 0);
178 
179 	switch (psr_context->controllerId) {
180 	/* Driver uses case 1 for unconfigured */
181 	case 1:
182 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
183 				STATIC_SCREEN1_INT_TO_UC_EN, 1);
184 		break;
185 	case 2:
186 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
187 				STATIC_SCREEN2_INT_TO_UC_EN, 1);
188 		break;
189 	case 3:
190 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
191 				STATIC_SCREEN3_INT_TO_UC_EN, 1);
192 		break;
193 	case 4:
194 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
195 				STATIC_SCREEN4_INT_TO_UC_EN, 1);
196 		break;
197 	case 5:
198 		/* CZ/NL only has 4 CRTC!!
199 		 * really valid.
200 		 * There is no interrupt enable mask for these instances.
201 		 */
202 		break;
203 	case 6:
204 		/* CZ/NL only has 4 CRTC!!
205 		 * These are here because they are defined in HW regspec,
206 		 * but not really valid. There is no interrupt enable mask
207 		 * for these instances.
208 		 */
209 		break;
210 	default:
211 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
212 				STATIC_SCREEN1_INT_TO_UC_EN, 1);
213 		break;
214 	}
215 
216 	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
217 			psr_context->sdpTransmitLineNumDeadline);
218 
219 	/* waitDMCUReadyForCmd */
220 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
221 					dmcu_wait_reg_ready_interval,
222 					dmcu_max_retry_on_wait_reg_ready);
223 
224 	/* setDMCUParam_PSRHostConfigData */
225 	masterCmdData1.u32All = 0;
226 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
227 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
228 	masterCmdData1.bits.rfb_update_auto_en =
229 			psr_context->rfb_update_auto_en;
230 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
231 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
232 	masterCmdData1.bits.phy_type  = psr_context->phyType;
233 	masterCmdData1.bits.frame_cap_ind =
234 			psr_context->psrFrameCaptureIndicationReq;
235 	masterCmdData1.bits.aux_chan = psr_context->channel;
236 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
237 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
238 					masterCmdData1.u32All);
239 
240 	masterCmdData2.u32All = 0;
241 	masterCmdData2.bits.dig_fe = psr_context->engineId;
242 	masterCmdData2.bits.dig_be = psr_context->transmitterId;
243 	masterCmdData2.bits.skip_wait_for_pll_lock =
244 			psr_context->skipPsrWaitForPllLock;
245 	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
246 	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
247 	masterCmdData2.bits.num_of_controllers =
248 			psr_context->numberOfControllers;
249 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
250 			masterCmdData2.u32All);
251 
252 	masterCmdData3.u32All = 0;
253 	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
254 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
255 			masterCmdData3.u32All);
256 
257 	/* setDMCUParam_Cmd */
258 	REG_UPDATE(MASTER_COMM_CMD_REG,
259 			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
260 
261 	/* notifyDMCUMsg */
262 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
263 
264 	return true;
265 }
266 
267 static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
268 {
269 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
270 	unsigned int dmcu_uc_reset;
271 
272 	/* microcontroller is not running */
273 	REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
274 
275 	/* DMCU is not running */
276 	if (dmcu_uc_reset)
277 		return false;
278 
279 	return true;
280 }
281 
282 static void dce_psr_wait_loop(
283 	struct dmcu *dmcu,
284 	unsigned int wait_loop_number)
285 {
286 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
287 	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
288 
289 	if (dmcu->cached_wait_loop_number == wait_loop_number)
290 		return;
291 
292 	/* DMCU is not running */
293 	if (!dce_is_dmcu_initialized(dmcu))
294 		return;
295 
296 	/* waitDMCUReadyForCmd */
297 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
298 
299 	masterCmdData1.u32 = 0;
300 	masterCmdData1.bits.wait_loop = wait_loop_number;
301 	dmcu->cached_wait_loop_number = wait_loop_number;
302 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
303 
304 	/* setDMCUParam_Cmd */
305 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
306 
307 	/* notifyDMCUMsg */
308 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
309 }
310 
311 static void dce_get_psr_wait_loop(
312 		struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
313 {
314 	*psr_wait_loop_number = dmcu->cached_wait_loop_number;
315 	return;
316 }
317 
318 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
319 static void dcn10_get_dmcu_version(struct dmcu *dmcu)
320 {
321 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
322 	uint32_t dmcu_version_offset = 0xf1;
323 
324 	/* Enable write access to IRAM */
325 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
326 			IRAM_HOST_ACCESS_EN, 1,
327 			IRAM_RD_ADDR_AUTO_INC, 1);
328 
329 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
330 
331 	/* Write address to IRAM_RD_ADDR and read from DATA register */
332 	REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
333 	dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
334 	dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
335 	dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
336 	dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
337 						REG_READ(DMCU_IRAM_RD_DATA));
338 
339 	/* Disable write access to IRAM to allow dynamic sleep state */
340 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
341 			IRAM_HOST_ACCESS_EN, 0,
342 			IRAM_RD_ADDR_AUTO_INC, 0);
343 }
344 
345 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu,
346 		uint32_t fractional_pwm)
347 {
348 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
349 
350 	/* Wait until microcontroller is ready to process interrupt */
351 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
352 
353 	/* Set PWM fractional enable/disable */
354 	REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm);
355 
356 	/* Set command to enable or disable fractional PWM microcontroller */
357 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
358 			MCP_BL_SET_PWM_FRAC);
359 
360 	/* Notify microcontroller of new command */
361 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
362 
363 	/* Ensure command has been executed before continuing */
364 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
365 }
366 
367 static bool dcn10_dmcu_init(struct dmcu *dmcu)
368 {
369 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
370 	const struct dc_config *config = &dmcu->ctx->dc->config;
371 	bool status = false;
372 
373 	/*  Definition of DC_DMCU_SCRATCH
374 	 *  0 : firmare not loaded
375 	 *  1 : PSP load DMCU FW but not initialized
376 	 *  2 : Firmware already initialized
377 	 */
378 	dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
379 
380 	switch (dmcu->dmcu_state) {
381 	case DMCU_UNLOADED:
382 		status = false;
383 		break;
384 	case DMCU_LOADED_UNINITIALIZED:
385 		/* Wait until microcontroller is ready to process interrupt */
386 		REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
387 
388 		/* Set initialized ramping boundary value */
389 		REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
390 
391 		/* Set command to initialize microcontroller */
392 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
393 			MCP_INIT_DMCU);
394 
395 		/* Notify microcontroller of new command */
396 		REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
397 
398 		/* Ensure command has been executed before continuing */
399 		REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
400 
401 		// Check state is initialized
402 		dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
403 
404 		// If microcontroller is not in running state, fail
405 		if (dmcu->dmcu_state == DMCU_RUNNING) {
406 			/* Retrieve and cache the DMCU firmware version. */
407 			dcn10_get_dmcu_version(dmcu);
408 
409 			/* Initialize DMCU to use fractional PWM or not */
410 			dcn10_dmcu_enable_fractional_pwm(dmcu,
411 				(config->disable_fractional_pwm == false) ? 1 : 0);
412 			status = true;
413 		} else {
414 			status = false;
415 		}
416 
417 		break;
418 	case DMCU_RUNNING:
419 		status = true;
420 		break;
421 	default:
422 		status = false;
423 		break;
424 	}
425 
426 	return status;
427 }
428 
429 
430 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
431 		unsigned int start_offset,
432 		const char *src,
433 		unsigned int bytes)
434 {
435 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
436 	unsigned int count = 0;
437 
438 	/* If microcontroller is not running, do nothing */
439 	if (dmcu->dmcu_state != DMCU_RUNNING)
440 		return false;
441 
442 	/* Enable write access to IRAM */
443 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
444 			IRAM_HOST_ACCESS_EN, 1,
445 			IRAM_WR_ADDR_AUTO_INC, 1);
446 
447 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
448 
449 	REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
450 
451 	for (count = 0; count < bytes; count++)
452 		REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
453 
454 	/* Disable write access to IRAM to allow dynamic sleep state */
455 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
456 			IRAM_HOST_ACCESS_EN, 0,
457 			IRAM_WR_ADDR_AUTO_INC, 0);
458 
459 	/* Wait until microcontroller is ready to process interrupt */
460 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
461 
462 	/* Set command to signal IRAM is loaded and to initialize IRAM */
463 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
464 			MCP_INIT_IRAM);
465 
466 	/* Notify microcontroller of new command */
467 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
468 
469 	/* Ensure command has been executed before continuing */
470 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
471 
472 	return true;
473 }
474 
475 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
476 {
477 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
478 
479 	uint32_t psr_state_offset = 0xf0;
480 
481 	/* If microcontroller is not running, do nothing */
482 	if (dmcu->dmcu_state != DMCU_RUNNING)
483 		return;
484 
485 	/* Enable write access to IRAM */
486 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
487 
488 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
489 
490 	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
491 	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
492 
493 	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
494 	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
495 
496 	/* Disable write access to IRAM after finished using IRAM
497 	 * in order to allow dynamic sleep state
498 	 */
499 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
500 }
501 
502 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
503 {
504 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
505 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
506 	unsigned int dmcu_wait_reg_ready_interval = 100;
507 
508 	unsigned int retryCount;
509 	uint32_t psr_state = 0;
510 
511 	/* If microcontroller is not running, do nothing */
512 	if (dmcu->dmcu_state != DMCU_RUNNING)
513 		return;
514 
515 	dcn10_get_dmcu_psr_state(dmcu, &psr_state);
516 	if (psr_state == 0 && !enable)
517 		return;
518 	/* waitDMCUReadyForCmd */
519 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
520 				dmcu_wait_reg_ready_interval,
521 				dmcu_max_retry_on_wait_reg_ready);
522 
523 	/* setDMCUParam_Cmd */
524 	if (enable)
525 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
526 				PSR_ENABLE);
527 	else
528 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
529 				PSR_EXIT);
530 
531 	/* notifyDMCUMsg */
532 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
533 
534 	/* Below loops 1000 x 500us = 500 ms.
535 	 *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
536 	 *  least a few frames. Should never hit the max retry assert below.
537 	 */
538 	if (wait == true) {
539 		for (retryCount = 0; retryCount <= 1000; retryCount++) {
540 			dcn10_get_dmcu_psr_state(dmcu, &psr_state);
541 			if (enable) {
542 				if (psr_state != 0)
543 					break;
544 			} else {
545 				if (psr_state == 0)
546 					break;
547 			}
548 			udelay(500);
549 		}
550 
551 		/* assert if max retry hit */
552 		if (retryCount >= 1000)
553 			ASSERT(0);
554 	}
555 }
556 
557 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
558 		struct dc_link *link,
559 		struct psr_context *psr_context)
560 {
561 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
562 
563 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
564 	unsigned int dmcu_wait_reg_ready_interval = 100;
565 
566 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
567 	union dce_dmcu_psr_config_data_reg2 masterCmdData2;
568 	union dce_dmcu_psr_config_data_reg3 masterCmdData3;
569 
570 	/* If microcontroller is not running, do nothing */
571 	if (dmcu->dmcu_state != DMCU_RUNNING)
572 		return false;
573 
574 	link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
575 			psr_context->psrExitLinkTrainingRequired);
576 
577 	/* Enable static screen interrupts for PSR supported display */
578 	/* Disable the interrupt coming from other displays. */
579 	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
580 			STATIC_SCREEN1_INT_TO_UC_EN, 0,
581 			STATIC_SCREEN2_INT_TO_UC_EN, 0,
582 			STATIC_SCREEN3_INT_TO_UC_EN, 0,
583 			STATIC_SCREEN4_INT_TO_UC_EN, 0);
584 
585 	switch (psr_context->controllerId) {
586 	/* Driver uses case 1 for unconfigured */
587 	case 1:
588 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
589 				STATIC_SCREEN1_INT_TO_UC_EN, 1);
590 		break;
591 	case 2:
592 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
593 				STATIC_SCREEN2_INT_TO_UC_EN, 1);
594 		break;
595 	case 3:
596 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
597 				STATIC_SCREEN3_INT_TO_UC_EN, 1);
598 		break;
599 	case 4:
600 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
601 				STATIC_SCREEN4_INT_TO_UC_EN, 1);
602 		break;
603 	case 5:
604 		/* CZ/NL only has 4 CRTC!!
605 		 * really valid.
606 		 * There is no interrupt enable mask for these instances.
607 		 */
608 		break;
609 	case 6:
610 		/* CZ/NL only has 4 CRTC!!
611 		 * These are here because they are defined in HW regspec,
612 		 * but not really valid. There is no interrupt enable mask
613 		 * for these instances.
614 		 */
615 		break;
616 	default:
617 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
618 				STATIC_SCREEN1_INT_TO_UC_EN, 1);
619 		break;
620 	}
621 
622 	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
623 			psr_context->sdpTransmitLineNumDeadline);
624 
625 	if (psr_context->allow_smu_optimizations)
626 		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
627 
628 	/* waitDMCUReadyForCmd */
629 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
630 			dmcu_wait_reg_ready_interval,
631 			dmcu_max_retry_on_wait_reg_ready);
632 
633 	/* setDMCUParam_PSRHostConfigData */
634 	masterCmdData1.u32All = 0;
635 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
636 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
637 	masterCmdData1.bits.rfb_update_auto_en =
638 			psr_context->rfb_update_auto_en;
639 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
640 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
641 	masterCmdData1.bits.phy_type  = psr_context->phyType;
642 	masterCmdData1.bits.frame_cap_ind =
643 			psr_context->psrFrameCaptureIndicationReq;
644 	masterCmdData1.bits.aux_chan = psr_context->channel;
645 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
646 	masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;
647 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
648 					masterCmdData1.u32All);
649 
650 	masterCmdData2.u32All = 0;
651 	masterCmdData2.bits.dig_fe = psr_context->engineId;
652 	masterCmdData2.bits.dig_be = psr_context->transmitterId;
653 	masterCmdData2.bits.skip_wait_for_pll_lock =
654 			psr_context->skipPsrWaitForPllLock;
655 	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
656 	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
657 	masterCmdData2.bits.num_of_controllers =
658 			psr_context->numberOfControllers;
659 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
660 			masterCmdData2.u32All);
661 
662 	masterCmdData3.u32All = 0;
663 	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
664 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
665 			masterCmdData3.u32All);
666 
667 
668 	/* setDMCUParam_Cmd */
669 	REG_UPDATE(MASTER_COMM_CMD_REG,
670 			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
671 
672 	/* notifyDMCUMsg */
673 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
674 
675 	/* waitDMCUReadyForCmd */
676 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
677 
678 	return true;
679 }
680 
681 static void dcn10_psr_wait_loop(
682 	struct dmcu *dmcu,
683 	unsigned int wait_loop_number)
684 {
685 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
686 	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
687 
688 	/* If microcontroller is not running, do nothing */
689 	if (dmcu->dmcu_state != DMCU_RUNNING)
690 		return;
691 
692 	if (wait_loop_number != 0) {
693 	/* waitDMCUReadyForCmd */
694 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
695 
696 	masterCmdData1.u32 = 0;
697 	masterCmdData1.bits.wait_loop = wait_loop_number;
698 	dmcu->cached_wait_loop_number = wait_loop_number;
699 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
700 
701 	/* setDMCUParam_Cmd */
702 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
703 
704 	/* notifyDMCUMsg */
705 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
706 	}
707 }
708 
709 static void dcn10_get_psr_wait_loop(
710 		struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
711 {
712 	*psr_wait_loop_number = dmcu->cached_wait_loop_number;
713 	return;
714 }
715 
716 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
717 {
718 	/* microcontroller is not running */
719 	if (dmcu->dmcu_state != DMCU_RUNNING)
720 		return false;
721 	return true;
722 }
723 
724 #endif //(CONFIG_DRM_AMD_DC_DCN1_0)
725 
726 static const struct dmcu_funcs dce_funcs = {
727 	.dmcu_init = dce_dmcu_init,
728 	.load_iram = dce_dmcu_load_iram,
729 	.set_psr_enable = dce_dmcu_set_psr_enable,
730 	.setup_psr = dce_dmcu_setup_psr,
731 	.get_psr_state = dce_get_dmcu_psr_state,
732 	.set_psr_wait_loop = dce_psr_wait_loop,
733 	.get_psr_wait_loop = dce_get_psr_wait_loop,
734 	.is_dmcu_initialized = dce_is_dmcu_initialized
735 };
736 
737 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
738 static const struct dmcu_funcs dcn10_funcs = {
739 	.dmcu_init = dcn10_dmcu_init,
740 	.load_iram = dcn10_dmcu_load_iram,
741 	.set_psr_enable = dcn10_dmcu_set_psr_enable,
742 	.setup_psr = dcn10_dmcu_setup_psr,
743 	.get_psr_state = dcn10_get_dmcu_psr_state,
744 	.set_psr_wait_loop = dcn10_psr_wait_loop,
745 	.get_psr_wait_loop = dcn10_get_psr_wait_loop,
746 	.is_dmcu_initialized = dcn10_is_dmcu_initialized
747 };
748 #endif
749 
750 static void dce_dmcu_construct(
751 	struct dce_dmcu *dmcu_dce,
752 	struct dc_context *ctx,
753 	const struct dce_dmcu_registers *regs,
754 	const struct dce_dmcu_shift *dmcu_shift,
755 	const struct dce_dmcu_mask *dmcu_mask)
756 {
757 	struct dmcu *base = &dmcu_dce->base;
758 
759 	base->ctx = ctx;
760 	base->funcs = &dce_funcs;
761 	base->cached_wait_loop_number = 0;
762 
763 	dmcu_dce->regs = regs;
764 	dmcu_dce->dmcu_shift = dmcu_shift;
765 	dmcu_dce->dmcu_mask = dmcu_mask;
766 }
767 
768 struct dmcu *dce_dmcu_create(
769 	struct dc_context *ctx,
770 	const struct dce_dmcu_registers *regs,
771 	const struct dce_dmcu_shift *dmcu_shift,
772 	const struct dce_dmcu_mask *dmcu_mask)
773 {
774 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
775 
776 	if (dmcu_dce == NULL) {
777 		BREAK_TO_DEBUGGER();
778 		return NULL;
779 	}
780 
781 	dce_dmcu_construct(
782 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
783 
784 	dmcu_dce->base.funcs = &dce_funcs;
785 
786 	return &dmcu_dce->base;
787 }
788 
789 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
790 struct dmcu *dcn10_dmcu_create(
791 	struct dc_context *ctx,
792 	const struct dce_dmcu_registers *regs,
793 	const struct dce_dmcu_shift *dmcu_shift,
794 	const struct dce_dmcu_mask *dmcu_mask)
795 {
796 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
797 
798 	if (dmcu_dce == NULL) {
799 		BREAK_TO_DEBUGGER();
800 		return NULL;
801 	}
802 
803 	dce_dmcu_construct(
804 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
805 
806 	dmcu_dce->base.funcs = &dcn10_funcs;
807 
808 	return &dmcu_dce->base;
809 }
810 #endif
811 
812 void dce_dmcu_destroy(struct dmcu **dmcu)
813 {
814 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
815 
816 	kfree(dmcu_dce);
817 	*dmcu = NULL;
818 }
819