1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "core_types.h" 30 #include "link_encoder.h" 31 #include "dce_dmcu.h" 32 #include "dm_services.h" 33 #include "reg_helper.h" 34 #include "fixed31_32.h" 35 #include "dc.h" 36 37 #define TO_DCE_DMCU(dmcu)\ 38 container_of(dmcu, struct dce_dmcu, base) 39 40 #define REG(reg) \ 41 (dmcu_dce->regs->reg) 42 43 #undef FN 44 #define FN(reg_name, field_name) \ 45 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 46 47 #define CTX \ 48 dmcu_dce->base.ctx 49 50 /* PSR related commands */ 51 #define PSR_ENABLE 0x20 52 #define PSR_EXIT 0x21 53 #define PSR_SET 0x23 54 #define PSR_SET_WAITLOOP 0x31 55 #define MCP_INIT_DMCU 0x88 56 #define MCP_INIT_IRAM 0x89 57 #define MCP_SYNC_PHY_LOCK 0x90 58 #define MCP_SYNC_PHY_UNLOCK 0x91 59 #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */ 60 #define CRC_WIN_NOTIFY 0x92 61 #define CRC_STOP_UPDATE 0x93 62 #define MCP_SEND_EDID_CEA 0xA0 63 #define EDID_CEA_CMD_ACK 1 64 #define EDID_CEA_CMD_NACK 2 65 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 66 67 // PSP FW version 68 #define mmMP0_SMN_C2PMSG_58 0x1607A 69 70 //Register access policy version 71 #define mmMP0_SMN_C2PMSG_91 0x1609B 72 73 static const uint32_t abm_gain_stepsize = 0x0060; 74 75 static bool dce_dmcu_init(struct dmcu *dmcu) 76 { 77 // Do nothing 78 return true; 79 } 80 81 static bool dce_dmcu_load_iram(struct dmcu *dmcu, 82 unsigned int start_offset, 83 const char *src, 84 unsigned int bytes) 85 { 86 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 87 unsigned int count = 0; 88 89 /* Enable write access to IRAM */ 90 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 91 IRAM_HOST_ACCESS_EN, 1, 92 IRAM_WR_ADDR_AUTO_INC, 1); 93 94 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 95 96 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 97 98 for (count = 0; count < bytes; count++) 99 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 100 101 /* Disable write access to IRAM to allow dynamic sleep state */ 102 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 103 IRAM_HOST_ACCESS_EN, 0, 104 IRAM_WR_ADDR_AUTO_INC, 0); 105 106 return true; 107 } 108 109 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 110 { 111 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 112 113 uint32_t psr_state_offset = 0xf0; 114 115 /* Enable write access to IRAM */ 116 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 117 118 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 119 120 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 121 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 122 123 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 124 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 125 126 /* Disable write access to IRAM after finished using IRAM 127 * in order to allow dynamic sleep state 128 */ 129 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 130 } 131 132 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 133 { 134 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 135 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 136 unsigned int dmcu_wait_reg_ready_interval = 100; 137 138 unsigned int retryCount; 139 enum dc_psr_state state = PSR_STATE0; 140 141 /* waitDMCUReadyForCmd */ 142 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 143 dmcu_wait_reg_ready_interval, 144 dmcu_max_retry_on_wait_reg_ready); 145 146 /* setDMCUParam_Cmd */ 147 if (enable) 148 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 149 PSR_ENABLE); 150 else 151 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 152 PSR_EXIT); 153 154 /* notifyDMCUMsg */ 155 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 156 if (wait == true) { 157 for (retryCount = 0; retryCount <= 100; retryCount++) { 158 dce_get_dmcu_psr_state(dmcu, &state); 159 if (enable) { 160 if (state != PSR_STATE0) 161 break; 162 } else { 163 if (state == PSR_STATE0) 164 break; 165 } 166 udelay(10); 167 } 168 } 169 } 170 171 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 172 struct dc_link *link, 173 struct psr_context *psr_context) 174 { 175 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 176 177 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 178 unsigned int dmcu_wait_reg_ready_interval = 100; 179 180 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 181 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 182 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 183 184 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 185 psr_context->psrExitLinkTrainingRequired); 186 187 /* Enable static screen interrupts for PSR supported display */ 188 /* Disable the interrupt coming from other displays. */ 189 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 190 STATIC_SCREEN1_INT_TO_UC_EN, 0, 191 STATIC_SCREEN2_INT_TO_UC_EN, 0, 192 STATIC_SCREEN3_INT_TO_UC_EN, 0, 193 STATIC_SCREEN4_INT_TO_UC_EN, 0); 194 195 switch (psr_context->controllerId) { 196 /* Driver uses case 1 for unconfigured */ 197 case 1: 198 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 199 STATIC_SCREEN1_INT_TO_UC_EN, 1); 200 break; 201 case 2: 202 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 203 STATIC_SCREEN2_INT_TO_UC_EN, 1); 204 break; 205 case 3: 206 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 207 STATIC_SCREEN3_INT_TO_UC_EN, 1); 208 break; 209 case 4: 210 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 211 STATIC_SCREEN4_INT_TO_UC_EN, 1); 212 break; 213 case 5: 214 /* CZ/NL only has 4 CRTC!! 215 * really valid. 216 * There is no interrupt enable mask for these instances. 217 */ 218 break; 219 case 6: 220 /* CZ/NL only has 4 CRTC!! 221 * These are here because they are defined in HW regspec, 222 * but not really valid. There is no interrupt enable mask 223 * for these instances. 224 */ 225 break; 226 default: 227 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 228 STATIC_SCREEN1_INT_TO_UC_EN, 1); 229 break; 230 } 231 232 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 233 psr_context->sdpTransmitLineNumDeadline); 234 235 /* waitDMCUReadyForCmd */ 236 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 237 dmcu_wait_reg_ready_interval, 238 dmcu_max_retry_on_wait_reg_ready); 239 240 /* setDMCUParam_PSRHostConfigData */ 241 masterCmdData1.u32All = 0; 242 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 243 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 244 masterCmdData1.bits.rfb_update_auto_en = 245 psr_context->rfb_update_auto_en; 246 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 247 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 248 masterCmdData1.bits.phy_type = psr_context->phyType; 249 masterCmdData1.bits.frame_cap_ind = 250 psr_context->psrFrameCaptureIndicationReq; 251 masterCmdData1.bits.aux_chan = psr_context->channel; 252 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 253 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 254 masterCmdData1.u32All); 255 256 masterCmdData2.u32All = 0; 257 masterCmdData2.bits.dig_fe = psr_context->engineId; 258 masterCmdData2.bits.dig_be = psr_context->transmitterId; 259 masterCmdData2.bits.skip_wait_for_pll_lock = 260 psr_context->skipPsrWaitForPllLock; 261 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 262 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 263 masterCmdData2.bits.num_of_controllers = 264 psr_context->numberOfControllers; 265 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 266 masterCmdData2.u32All); 267 268 masterCmdData3.u32All = 0; 269 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 270 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 271 masterCmdData3.u32All); 272 273 /* setDMCUParam_Cmd */ 274 REG_UPDATE(MASTER_COMM_CMD_REG, 275 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 276 277 /* notifyDMCUMsg */ 278 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 279 280 return true; 281 } 282 283 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 284 { 285 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 286 unsigned int dmcu_uc_reset; 287 288 /* microcontroller is not running */ 289 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 290 291 /* DMCU is not running */ 292 if (dmcu_uc_reset) 293 return false; 294 295 return true; 296 } 297 298 static void dce_psr_wait_loop( 299 struct dmcu *dmcu, 300 unsigned int wait_loop_number) 301 { 302 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 303 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 304 305 if (dmcu->cached_wait_loop_number == wait_loop_number) 306 return; 307 308 /* DMCU is not running */ 309 if (!dce_is_dmcu_initialized(dmcu)) 310 return; 311 312 /* waitDMCUReadyForCmd */ 313 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 314 315 masterCmdData1.u32 = 0; 316 masterCmdData1.bits.wait_loop = wait_loop_number; 317 dmcu->cached_wait_loop_number = wait_loop_number; 318 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 319 320 /* setDMCUParam_Cmd */ 321 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 322 323 /* notifyDMCUMsg */ 324 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 325 } 326 327 static void dce_get_psr_wait_loop( 328 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 329 { 330 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 331 return; 332 } 333 334 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 335 { 336 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 337 uint32_t dmcu_version_offset = 0xf1; 338 339 /* Enable write access to IRAM */ 340 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 341 IRAM_HOST_ACCESS_EN, 1, 342 IRAM_RD_ADDR_AUTO_INC, 1); 343 344 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 345 346 /* Write address to IRAM_RD_ADDR and read from DATA register */ 347 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 348 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 349 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 350 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 351 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 352 REG_READ(DMCU_IRAM_RD_DATA)); 353 354 /* Disable write access to IRAM to allow dynamic sleep state */ 355 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 356 IRAM_HOST_ACCESS_EN, 0, 357 IRAM_RD_ADDR_AUTO_INC, 0); 358 } 359 360 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu, 361 uint32_t fractional_pwm) 362 { 363 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 364 365 /* Wait until microcontroller is ready to process interrupt */ 366 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 367 368 /* Set PWM fractional enable/disable */ 369 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); 370 371 /* Set command to enable or disable fractional PWM microcontroller */ 372 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 373 MCP_BL_SET_PWM_FRAC); 374 375 /* Notify microcontroller of new command */ 376 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 377 378 /* Ensure command has been executed before continuing */ 379 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 380 } 381 382 static bool dcn10_dmcu_init(struct dmcu *dmcu) 383 { 384 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 385 const struct dc_config *config = &dmcu->ctx->dc->config; 386 bool status = false; 387 struct dc_context *ctx = dmcu->ctx; 388 unsigned int i; 389 // 5 4 3 2 1 0 390 // F E D C B A - bit 0 is A, bit 5 is F 391 unsigned int tx_interrupt_mask = 0; 392 393 PERF_TRACE(); 394 /* Definition of DC_DMCU_SCRATCH 395 * 0 : firmare not loaded 396 * 1 : PSP load DMCU FW but not initialized 397 * 2 : Firmware already initialized 398 */ 399 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 400 401 for (i = 0; i < ctx->dc->link_count; i++) { 402 if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) { 403 if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A && 404 ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) { 405 tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter; 406 } 407 } 408 } 409 410 switch (dmcu->dmcu_state) { 411 case DMCU_UNLOADED: 412 status = false; 413 break; 414 case DMCU_LOADED_UNINITIALIZED: 415 /* Wait until microcontroller is ready to process interrupt */ 416 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 417 418 /* Set initialized ramping boundary value */ 419 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 420 421 /* Set backlight ramping stepsize */ 422 REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize); 423 424 REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask); 425 426 /* Set command to initialize microcontroller */ 427 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 428 MCP_INIT_DMCU); 429 430 /* Notify microcontroller of new command */ 431 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 432 433 /* Ensure command has been executed before continuing */ 434 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 435 436 // Check state is initialized 437 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 438 439 // If microcontroller is not in running state, fail 440 if (dmcu->dmcu_state == DMCU_RUNNING) { 441 /* Retrieve and cache the DMCU firmware version. */ 442 dcn10_get_dmcu_version(dmcu); 443 444 /* Initialize DMCU to use fractional PWM or not */ 445 dcn10_dmcu_enable_fractional_pwm(dmcu, 446 (config->disable_fractional_pwm == false) ? 1 : 0); 447 status = true; 448 } else { 449 status = false; 450 } 451 452 break; 453 case DMCU_RUNNING: 454 status = true; 455 break; 456 default: 457 status = false; 458 break; 459 } 460 461 PERF_TRACE(); 462 return status; 463 } 464 465 static bool dcn21_dmcu_init(struct dmcu *dmcu) 466 { 467 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 468 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15); 469 470 if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) { 471 return false; 472 } 473 474 return dcn10_dmcu_init(dmcu); 475 } 476 477 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 478 unsigned int start_offset, 479 const char *src, 480 unsigned int bytes) 481 { 482 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 483 unsigned int count = 0; 484 485 /* If microcontroller is not running, do nothing */ 486 if (dmcu->dmcu_state != DMCU_RUNNING) 487 return false; 488 489 /* Enable write access to IRAM */ 490 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 491 IRAM_HOST_ACCESS_EN, 1, 492 IRAM_WR_ADDR_AUTO_INC, 1); 493 494 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 495 496 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 497 498 for (count = 0; count < bytes; count++) 499 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 500 501 /* Disable write access to IRAM to allow dynamic sleep state */ 502 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 503 IRAM_HOST_ACCESS_EN, 0, 504 IRAM_WR_ADDR_AUTO_INC, 0); 505 506 /* Wait until microcontroller is ready to process interrupt */ 507 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 508 509 /* Set command to signal IRAM is loaded and to initialize IRAM */ 510 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 511 MCP_INIT_IRAM); 512 513 /* Notify microcontroller of new command */ 514 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 515 516 /* Ensure command has been executed before continuing */ 517 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 518 519 return true; 520 } 521 522 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 523 { 524 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 525 526 uint32_t psr_state_offset = 0xf0; 527 528 /* If microcontroller is not running, do nothing */ 529 if (dmcu->dmcu_state != DMCU_RUNNING) 530 return; 531 532 /* Enable write access to IRAM */ 533 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 534 535 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 536 537 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 538 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 539 540 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 541 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 542 543 /* Disable write access to IRAM after finished using IRAM 544 * in order to allow dynamic sleep state 545 */ 546 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 547 } 548 549 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 550 { 551 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 552 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 553 unsigned int dmcu_wait_reg_ready_interval = 100; 554 555 unsigned int retryCount; 556 enum dc_psr_state state = PSR_STATE0; 557 558 /* If microcontroller is not running, do nothing */ 559 if (dmcu->dmcu_state != DMCU_RUNNING) 560 return; 561 562 /* waitDMCUReadyForCmd */ 563 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 564 dmcu_wait_reg_ready_interval, 565 dmcu_max_retry_on_wait_reg_ready); 566 567 /* setDMCUParam_Cmd */ 568 if (enable) 569 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 570 PSR_ENABLE); 571 else 572 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 573 PSR_EXIT); 574 575 /* notifyDMCUMsg */ 576 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 577 578 /* Below loops 1000 x 500us = 500 ms. 579 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 580 * least a few frames. Should never hit the max retry assert below. 581 */ 582 if (wait == true) { 583 for (retryCount = 0; retryCount <= 1000; retryCount++) { 584 dcn10_get_dmcu_psr_state(dmcu, &state); 585 if (enable) { 586 if (state != PSR_STATE0) 587 break; 588 } else { 589 if (state == PSR_STATE0) 590 break; 591 } 592 udelay(500); 593 } 594 595 /* assert if max retry hit */ 596 if (retryCount >= 1000) 597 ASSERT(0); 598 } 599 } 600 601 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 602 struct dc_link *link, 603 struct psr_context *psr_context) 604 { 605 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 606 607 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 608 unsigned int dmcu_wait_reg_ready_interval = 100; 609 610 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 611 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 612 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 613 614 /* If microcontroller is not running, do nothing */ 615 if (dmcu->dmcu_state != DMCU_RUNNING) 616 return false; 617 618 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 619 psr_context->psrExitLinkTrainingRequired); 620 621 /* Enable static screen interrupts for PSR supported display */ 622 /* Disable the interrupt coming from other displays. */ 623 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 624 STATIC_SCREEN1_INT_TO_UC_EN, 0, 625 STATIC_SCREEN2_INT_TO_UC_EN, 0, 626 STATIC_SCREEN3_INT_TO_UC_EN, 0, 627 STATIC_SCREEN4_INT_TO_UC_EN, 0); 628 629 switch (psr_context->controllerId) { 630 /* Driver uses case 1 for unconfigured */ 631 case 1: 632 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 633 STATIC_SCREEN1_INT_TO_UC_EN, 1); 634 break; 635 case 2: 636 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 637 STATIC_SCREEN2_INT_TO_UC_EN, 1); 638 break; 639 case 3: 640 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 641 STATIC_SCREEN3_INT_TO_UC_EN, 1); 642 break; 643 case 4: 644 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 645 STATIC_SCREEN4_INT_TO_UC_EN, 1); 646 break; 647 case 5: 648 /* CZ/NL only has 4 CRTC!! 649 * really valid. 650 * There is no interrupt enable mask for these instances. 651 */ 652 break; 653 case 6: 654 /* CZ/NL only has 4 CRTC!! 655 * These are here because they are defined in HW regspec, 656 * but not really valid. There is no interrupt enable mask 657 * for these instances. 658 */ 659 break; 660 default: 661 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 662 STATIC_SCREEN1_INT_TO_UC_EN, 1); 663 break; 664 } 665 666 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 667 psr_context->sdpTransmitLineNumDeadline); 668 669 if (psr_context->allow_smu_optimizations) 670 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 671 672 /* waitDMCUReadyForCmd */ 673 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 674 dmcu_wait_reg_ready_interval, 675 dmcu_max_retry_on_wait_reg_ready); 676 677 /* setDMCUParam_PSRHostConfigData */ 678 masterCmdData1.u32All = 0; 679 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 680 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 681 masterCmdData1.bits.rfb_update_auto_en = 682 psr_context->rfb_update_auto_en; 683 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 684 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 685 masterCmdData1.bits.phy_type = psr_context->phyType; 686 masterCmdData1.bits.frame_cap_ind = 687 psr_context->psrFrameCaptureIndicationReq; 688 masterCmdData1.bits.aux_chan = psr_context->channel; 689 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 690 masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations; 691 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 692 masterCmdData1.u32All); 693 694 masterCmdData2.u32All = 0; 695 masterCmdData2.bits.dig_fe = psr_context->engineId; 696 masterCmdData2.bits.dig_be = psr_context->transmitterId; 697 masterCmdData2.bits.skip_wait_for_pll_lock = 698 psr_context->skipPsrWaitForPllLock; 699 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 700 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 701 masterCmdData2.bits.num_of_controllers = 702 psr_context->numberOfControllers; 703 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 704 masterCmdData2.u32All); 705 706 masterCmdData3.u32All = 0; 707 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 708 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 709 masterCmdData3.u32All); 710 711 712 /* setDMCUParam_Cmd */ 713 REG_UPDATE(MASTER_COMM_CMD_REG, 714 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 715 716 /* notifyDMCUMsg */ 717 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 718 719 /* waitDMCUReadyForCmd */ 720 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 721 722 return true; 723 } 724 725 static void dcn10_psr_wait_loop( 726 struct dmcu *dmcu, 727 unsigned int wait_loop_number) 728 { 729 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 730 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 731 732 /* If microcontroller is not running, do nothing */ 733 if (dmcu->dmcu_state != DMCU_RUNNING) 734 return; 735 736 if (wait_loop_number != 0) { 737 /* waitDMCUReadyForCmd */ 738 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 739 740 masterCmdData1.u32 = 0; 741 masterCmdData1.bits.wait_loop = wait_loop_number; 742 dmcu->cached_wait_loop_number = wait_loop_number; 743 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 744 745 /* setDMCUParam_Cmd */ 746 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 747 748 /* notifyDMCUMsg */ 749 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 750 } 751 } 752 753 static void dcn10_get_psr_wait_loop( 754 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 755 { 756 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 757 return; 758 } 759 760 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 761 { 762 /* microcontroller is not running */ 763 if (dmcu->dmcu_state != DMCU_RUNNING) 764 return false; 765 return true; 766 } 767 768 769 770 static bool dcn20_lock_phy(struct dmcu *dmcu) 771 { 772 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 773 774 /* If microcontroller is not running, do nothing */ 775 if (dmcu->dmcu_state != DMCU_RUNNING) 776 return false; 777 778 /* waitDMCUReadyForCmd */ 779 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 780 781 /* setDMCUParam_Cmd */ 782 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK); 783 784 /* notifyDMCUMsg */ 785 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 786 787 /* waitDMCUReadyForCmd */ 788 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 789 790 return true; 791 } 792 793 static bool dcn20_unlock_phy(struct dmcu *dmcu) 794 { 795 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 796 797 /* If microcontroller is not running, do nothing */ 798 if (dmcu->dmcu_state != DMCU_RUNNING) 799 return false; 800 801 /* waitDMCUReadyForCmd */ 802 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 803 804 /* setDMCUParam_Cmd */ 805 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK); 806 807 /* notifyDMCUMsg */ 808 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 809 810 /* waitDMCUReadyForCmd */ 811 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 812 813 return true; 814 } 815 816 static bool dcn10_send_edid_cea(struct dmcu *dmcu, 817 int offset, 818 int total_length, 819 uint8_t *data, 820 int length) 821 { 822 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 823 uint32_t header, data1, data2; 824 825 /* If microcontroller is not running, do nothing */ 826 if (dmcu->dmcu_state != DMCU_RUNNING) 827 return false; 828 829 if (length > 8 || length <= 0) 830 return false; 831 832 header = ((uint32_t)offset & 0xFFFF) << 16 | (total_length & 0xFFFF); 833 data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) | 834 (((uint32_t)data[2]) << 8) | ((uint32_t)data[3]); 835 data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) | 836 (((uint32_t)data[6]) << 8) | ((uint32_t)data[7]); 837 838 /* waitDMCUReadyForCmd */ 839 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 840 841 /* setDMCUParam_Cmd */ 842 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SEND_EDID_CEA); 843 844 REG_WRITE(MASTER_COMM_DATA_REG1, header); 845 REG_WRITE(MASTER_COMM_DATA_REG2, data1); 846 REG_WRITE(MASTER_COMM_DATA_REG3, data2); 847 848 /* notifyDMCUMsg */ 849 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 850 851 /* waitDMCUReadyForCmd */ 852 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 853 854 return true; 855 } 856 857 static bool dcn10_get_scp_results(struct dmcu *dmcu, 858 uint32_t *cmd, 859 uint32_t *data1, 860 uint32_t *data2, 861 uint32_t *data3) 862 { 863 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 864 865 /* If microcontroller is not running, do nothing */ 866 if (dmcu->dmcu_state != DMCU_RUNNING) 867 return false; 868 869 *cmd = REG_READ(SLAVE_COMM_CMD_REG); 870 *data1 = REG_READ(SLAVE_COMM_DATA_REG1); 871 *data2 = REG_READ(SLAVE_COMM_DATA_REG2); 872 *data3 = REG_READ(SLAVE_COMM_DATA_REG3); 873 874 /* clear SCP interrupt */ 875 REG_UPDATE(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, 0); 876 877 return true; 878 } 879 880 static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu, 881 int *version, 882 int *min_frame_rate, 883 int *max_frame_rate) 884 { 885 uint32_t data[4]; 886 int cmd, ack, len; 887 888 if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3])) 889 return false; 890 891 cmd = data[0] & 0x3FF; 892 len = (data[0] >> 10) & 0x3F; 893 ack = data[1]; 894 895 if (cmd != MCP_SEND_EDID_CEA || ack != EDID_CEA_CMD_ACK || len != 12) 896 return false; 897 898 if ((data[2] & 0xFF)) { 899 *version = (data[2] >> 8) & 0xFF; 900 *min_frame_rate = (data[3] >> 16) & 0xFFFF; 901 *max_frame_rate = data[3] & 0xFFFF; 902 return true; 903 } 904 905 return false; 906 } 907 908 static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset) 909 { 910 uint32_t data[4]; 911 int cmd, ack; 912 913 if (!dcn10_get_scp_results(dmcu, 914 &data[0], &data[1], &data[2], &data[3])) 915 return false; 916 917 cmd = data[0] & 0x3FF; 918 ack = data[1]; 919 920 if (cmd != MCP_SEND_EDID_CEA) 921 return false; 922 923 if (ack == EDID_CEA_CMD_ACK) 924 return true; 925 926 *offset = data[2]; /* nack */ 927 return false; 928 } 929 930 931 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 932 static void dcn10_forward_crc_window(struct dmcu *dmcu, 933 struct crc_region *crc_win, 934 struct otg_phy_mux *mux_mapping) 935 { 936 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 937 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 938 unsigned int dmcu_wait_reg_ready_interval = 100; 939 unsigned int crc_start = 0, crc_end = 0, otg_phy_mux = 0; 940 941 /* If microcontroller is not running, do nothing */ 942 if (dmcu->dmcu_state != DMCU_RUNNING) 943 return; 944 945 if (!crc_win) 946 return; 947 948 /* waitDMCUReadyForCmd */ 949 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 950 dmcu_wait_reg_ready_interval, 951 dmcu_max_retry_on_wait_reg_ready); 952 953 /* build up nitification data */ 954 crc_start = (((unsigned int) crc_win->x_start) << 16) | crc_win->y_start; 955 crc_end = (((unsigned int) crc_win->x_end) << 16) | crc_win->y_end; 956 otg_phy_mux = 957 (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; 958 959 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 960 crc_start); 961 962 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 963 crc_end); 964 965 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 966 otg_phy_mux); 967 968 /* setDMCUParam_Cmd */ 969 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 970 CRC_WIN_NOTIFY); 971 972 /* notifyDMCUMsg */ 973 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 974 } 975 976 static void dcn10_stop_crc_win_update(struct dmcu *dmcu, 977 struct otg_phy_mux *mux_mapping) 978 { 979 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 980 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 981 unsigned int dmcu_wait_reg_ready_interval = 100; 982 unsigned int otg_phy_mux = 0; 983 984 /* If microcontroller is not running, do nothing */ 985 if (dmcu->dmcu_state != DMCU_RUNNING) 986 return; 987 988 /* waitDMCUReadyForCmd */ 989 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 990 dmcu_wait_reg_ready_interval, 991 dmcu_max_retry_on_wait_reg_ready); 992 993 /* build up nitification data */ 994 otg_phy_mux = 995 (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; 996 997 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 998 otg_phy_mux); 999 1000 /* setDMCUParam_Cmd */ 1001 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 1002 CRC_STOP_UPDATE); 1003 1004 /* notifyDMCUMsg */ 1005 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 1006 } 1007 #endif 1008 1009 static const struct dmcu_funcs dce_funcs = { 1010 .dmcu_init = dce_dmcu_init, 1011 .load_iram = dce_dmcu_load_iram, 1012 .set_psr_enable = dce_dmcu_set_psr_enable, 1013 .setup_psr = dce_dmcu_setup_psr, 1014 .get_psr_state = dce_get_dmcu_psr_state, 1015 .set_psr_wait_loop = dce_psr_wait_loop, 1016 .get_psr_wait_loop = dce_get_psr_wait_loop, 1017 .is_dmcu_initialized = dce_is_dmcu_initialized 1018 }; 1019 1020 static const struct dmcu_funcs dcn10_funcs = { 1021 .dmcu_init = dcn10_dmcu_init, 1022 .load_iram = dcn10_dmcu_load_iram, 1023 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1024 .setup_psr = dcn10_dmcu_setup_psr, 1025 .get_psr_state = dcn10_get_dmcu_psr_state, 1026 .set_psr_wait_loop = dcn10_psr_wait_loop, 1027 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1028 .send_edid_cea = dcn10_send_edid_cea, 1029 .recv_amd_vsdb = dcn10_recv_amd_vsdb, 1030 .recv_edid_cea_ack = dcn10_recv_edid_cea_ack, 1031 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1032 .forward_crc_window = dcn10_forward_crc_window, 1033 .stop_crc_win_update = dcn10_stop_crc_win_update, 1034 #endif 1035 .is_dmcu_initialized = dcn10_is_dmcu_initialized 1036 }; 1037 1038 static const struct dmcu_funcs dcn20_funcs = { 1039 .dmcu_init = dcn10_dmcu_init, 1040 .load_iram = dcn10_dmcu_load_iram, 1041 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1042 .setup_psr = dcn10_dmcu_setup_psr, 1043 .get_psr_state = dcn10_get_dmcu_psr_state, 1044 .set_psr_wait_loop = dcn10_psr_wait_loop, 1045 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1046 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 1047 .lock_phy = dcn20_lock_phy, 1048 .unlock_phy = dcn20_unlock_phy 1049 }; 1050 1051 static const struct dmcu_funcs dcn21_funcs = { 1052 .dmcu_init = dcn21_dmcu_init, 1053 .load_iram = dcn10_dmcu_load_iram, 1054 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1055 .setup_psr = dcn10_dmcu_setup_psr, 1056 .get_psr_state = dcn10_get_dmcu_psr_state, 1057 .set_psr_wait_loop = dcn10_psr_wait_loop, 1058 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1059 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 1060 .lock_phy = dcn20_lock_phy, 1061 .unlock_phy = dcn20_unlock_phy 1062 }; 1063 1064 static void dce_dmcu_construct( 1065 struct dce_dmcu *dmcu_dce, 1066 struct dc_context *ctx, 1067 const struct dce_dmcu_registers *regs, 1068 const struct dce_dmcu_shift *dmcu_shift, 1069 const struct dce_dmcu_mask *dmcu_mask) 1070 { 1071 struct dmcu *base = &dmcu_dce->base; 1072 1073 base->ctx = ctx; 1074 base->funcs = &dce_funcs; 1075 base->cached_wait_loop_number = 0; 1076 1077 dmcu_dce->regs = regs; 1078 dmcu_dce->dmcu_shift = dmcu_shift; 1079 dmcu_dce->dmcu_mask = dmcu_mask; 1080 } 1081 1082 static void dcn21_dmcu_construct( 1083 struct dce_dmcu *dmcu_dce, 1084 struct dc_context *ctx, 1085 const struct dce_dmcu_registers *regs, 1086 const struct dce_dmcu_shift *dmcu_shift, 1087 const struct dce_dmcu_mask *dmcu_mask) 1088 { 1089 uint32_t psp_version = 0; 1090 1091 dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1092 1093 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 1094 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); 1095 dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029); 1096 dmcu_dce->base.psp_version = psp_version; 1097 } 1098 } 1099 1100 struct dmcu *dce_dmcu_create( 1101 struct dc_context *ctx, 1102 const struct dce_dmcu_registers *regs, 1103 const struct dce_dmcu_shift *dmcu_shift, 1104 const struct dce_dmcu_mask *dmcu_mask) 1105 { 1106 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 1107 1108 if (dmcu_dce == NULL) { 1109 BREAK_TO_DEBUGGER(); 1110 return NULL; 1111 } 1112 1113 dce_dmcu_construct( 1114 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1115 1116 dmcu_dce->base.funcs = &dce_funcs; 1117 1118 return &dmcu_dce->base; 1119 } 1120 1121 struct dmcu *dcn10_dmcu_create( 1122 struct dc_context *ctx, 1123 const struct dce_dmcu_registers *regs, 1124 const struct dce_dmcu_shift *dmcu_shift, 1125 const struct dce_dmcu_mask *dmcu_mask) 1126 { 1127 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1128 1129 if (dmcu_dce == NULL) { 1130 BREAK_TO_DEBUGGER(); 1131 return NULL; 1132 } 1133 1134 dce_dmcu_construct( 1135 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1136 1137 dmcu_dce->base.funcs = &dcn10_funcs; 1138 1139 return &dmcu_dce->base; 1140 } 1141 1142 struct dmcu *dcn20_dmcu_create( 1143 struct dc_context *ctx, 1144 const struct dce_dmcu_registers *regs, 1145 const struct dce_dmcu_shift *dmcu_shift, 1146 const struct dce_dmcu_mask *dmcu_mask) 1147 { 1148 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1149 1150 if (dmcu_dce == NULL) { 1151 BREAK_TO_DEBUGGER(); 1152 return NULL; 1153 } 1154 1155 dce_dmcu_construct( 1156 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1157 1158 dmcu_dce->base.funcs = &dcn20_funcs; 1159 1160 return &dmcu_dce->base; 1161 } 1162 1163 struct dmcu *dcn21_dmcu_create( 1164 struct dc_context *ctx, 1165 const struct dce_dmcu_registers *regs, 1166 const struct dce_dmcu_shift *dmcu_shift, 1167 const struct dce_dmcu_mask *dmcu_mask) 1168 { 1169 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1170 1171 if (dmcu_dce == NULL) { 1172 BREAK_TO_DEBUGGER(); 1173 return NULL; 1174 } 1175 1176 dcn21_dmcu_construct( 1177 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1178 1179 dmcu_dce->base.funcs = &dcn21_funcs; 1180 1181 return &dmcu_dce->base; 1182 } 1183 1184 void dce_dmcu_destroy(struct dmcu **dmcu) 1185 { 1186 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 1187 1188 kfree(dmcu_dce); 1189 *dmcu = NULL; 1190 } 1191