1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "core_types.h" 30 #include "link_encoder.h" 31 #include "dce_dmcu.h" 32 #include "dm_services.h" 33 #include "reg_helper.h" 34 #include "fixed31_32.h" 35 #include "dc.h" 36 37 #define TO_DCE_DMCU(dmcu)\ 38 container_of(dmcu, struct dce_dmcu, base) 39 40 #define REG(reg) \ 41 (dmcu_dce->regs->reg) 42 43 #undef FN 44 #define FN(reg_name, field_name) \ 45 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 46 47 #define CTX \ 48 dmcu_dce->base.ctx 49 50 /* PSR related commands */ 51 #define PSR_ENABLE 0x20 52 #define PSR_EXIT 0x21 53 #define PSR_SET 0x23 54 #define PSR_SET_WAITLOOP 0x31 55 #define MCP_INIT_DMCU 0x88 56 #define MCP_INIT_IRAM 0x89 57 #define MCP_SYNC_PHY_LOCK 0x90 58 #define MCP_SYNC_PHY_UNLOCK 0x91 59 #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */ 60 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 61 62 // PSP FW version 63 #define mmMP0_SMN_C2PMSG_58 0x1607A 64 65 //Register access policy version 66 #define mmMP0_SMN_C2PMSG_91 0x1609B 67 68 static bool dce_dmcu_init(struct dmcu *dmcu) 69 { 70 // Do nothing 71 return true; 72 } 73 74 bool dce_dmcu_load_iram(struct dmcu *dmcu, 75 unsigned int start_offset, 76 const char *src, 77 unsigned int bytes) 78 { 79 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 80 unsigned int count = 0; 81 82 /* Enable write access to IRAM */ 83 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 84 IRAM_HOST_ACCESS_EN, 1, 85 IRAM_WR_ADDR_AUTO_INC, 1); 86 87 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 88 89 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 90 91 for (count = 0; count < bytes; count++) 92 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 93 94 /* Disable write access to IRAM to allow dynamic sleep state */ 95 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 96 IRAM_HOST_ACCESS_EN, 0, 97 IRAM_WR_ADDR_AUTO_INC, 0); 98 99 return true; 100 } 101 102 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 103 { 104 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 105 106 uint32_t psr_state_offset = 0xf0; 107 108 /* Enable write access to IRAM */ 109 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 110 111 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 112 113 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 114 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 115 116 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 117 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 118 119 /* Disable write access to IRAM after finished using IRAM 120 * in order to allow dynamic sleep state 121 */ 122 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 123 } 124 125 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 126 { 127 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 128 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 129 unsigned int dmcu_wait_reg_ready_interval = 100; 130 131 unsigned int retryCount; 132 uint32_t psr_state = 0; 133 134 /* waitDMCUReadyForCmd */ 135 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 136 dmcu_wait_reg_ready_interval, 137 dmcu_max_retry_on_wait_reg_ready); 138 139 /* setDMCUParam_Cmd */ 140 if (enable) 141 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 142 PSR_ENABLE); 143 else 144 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 145 PSR_EXIT); 146 147 /* notifyDMCUMsg */ 148 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 149 if (wait == true) { 150 for (retryCount = 0; retryCount <= 100; retryCount++) { 151 dce_get_dmcu_psr_state(dmcu, &psr_state); 152 if (enable) { 153 if (psr_state != 0) 154 break; 155 } else { 156 if (psr_state == 0) 157 break; 158 } 159 udelay(10); 160 } 161 } 162 } 163 164 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 165 struct dc_link *link, 166 struct psr_context *psr_context) 167 { 168 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 169 170 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 171 unsigned int dmcu_wait_reg_ready_interval = 100; 172 173 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 174 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 175 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 176 177 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 178 psr_context->psrExitLinkTrainingRequired); 179 180 /* Enable static screen interrupts for PSR supported display */ 181 /* Disable the interrupt coming from other displays. */ 182 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 183 STATIC_SCREEN1_INT_TO_UC_EN, 0, 184 STATIC_SCREEN2_INT_TO_UC_EN, 0, 185 STATIC_SCREEN3_INT_TO_UC_EN, 0, 186 STATIC_SCREEN4_INT_TO_UC_EN, 0); 187 188 switch (psr_context->controllerId) { 189 /* Driver uses case 1 for unconfigured */ 190 case 1: 191 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 192 STATIC_SCREEN1_INT_TO_UC_EN, 1); 193 break; 194 case 2: 195 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 196 STATIC_SCREEN2_INT_TO_UC_EN, 1); 197 break; 198 case 3: 199 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 200 STATIC_SCREEN3_INT_TO_UC_EN, 1); 201 break; 202 case 4: 203 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 204 STATIC_SCREEN4_INT_TO_UC_EN, 1); 205 break; 206 case 5: 207 /* CZ/NL only has 4 CRTC!! 208 * really valid. 209 * There is no interrupt enable mask for these instances. 210 */ 211 break; 212 case 6: 213 /* CZ/NL only has 4 CRTC!! 214 * These are here because they are defined in HW regspec, 215 * but not really valid. There is no interrupt enable mask 216 * for these instances. 217 */ 218 break; 219 default: 220 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 221 STATIC_SCREEN1_INT_TO_UC_EN, 1); 222 break; 223 } 224 225 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 226 psr_context->sdpTransmitLineNumDeadline); 227 228 /* waitDMCUReadyForCmd */ 229 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 230 dmcu_wait_reg_ready_interval, 231 dmcu_max_retry_on_wait_reg_ready); 232 233 /* setDMCUParam_PSRHostConfigData */ 234 masterCmdData1.u32All = 0; 235 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 236 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 237 masterCmdData1.bits.rfb_update_auto_en = 238 psr_context->rfb_update_auto_en; 239 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 240 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 241 masterCmdData1.bits.phy_type = psr_context->phyType; 242 masterCmdData1.bits.frame_cap_ind = 243 psr_context->psrFrameCaptureIndicationReq; 244 masterCmdData1.bits.aux_chan = psr_context->channel; 245 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 246 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 247 masterCmdData1.u32All); 248 249 masterCmdData2.u32All = 0; 250 masterCmdData2.bits.dig_fe = psr_context->engineId; 251 masterCmdData2.bits.dig_be = psr_context->transmitterId; 252 masterCmdData2.bits.skip_wait_for_pll_lock = 253 psr_context->skipPsrWaitForPllLock; 254 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 255 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 256 masterCmdData2.bits.num_of_controllers = 257 psr_context->numberOfControllers; 258 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 259 masterCmdData2.u32All); 260 261 masterCmdData3.u32All = 0; 262 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 263 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 264 masterCmdData3.u32All); 265 266 /* setDMCUParam_Cmd */ 267 REG_UPDATE(MASTER_COMM_CMD_REG, 268 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 269 270 /* notifyDMCUMsg */ 271 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 272 273 return true; 274 } 275 276 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 277 { 278 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 279 unsigned int dmcu_uc_reset; 280 281 /* microcontroller is not running */ 282 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 283 284 /* DMCU is not running */ 285 if (dmcu_uc_reset) 286 return false; 287 288 return true; 289 } 290 291 static void dce_psr_wait_loop( 292 struct dmcu *dmcu, 293 unsigned int wait_loop_number) 294 { 295 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 296 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 297 298 if (dmcu->cached_wait_loop_number == wait_loop_number) 299 return; 300 301 /* DMCU is not running */ 302 if (!dce_is_dmcu_initialized(dmcu)) 303 return; 304 305 /* waitDMCUReadyForCmd */ 306 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 307 308 masterCmdData1.u32 = 0; 309 masterCmdData1.bits.wait_loop = wait_loop_number; 310 dmcu->cached_wait_loop_number = wait_loop_number; 311 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 312 313 /* setDMCUParam_Cmd */ 314 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 315 316 /* notifyDMCUMsg */ 317 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 318 } 319 320 static void dce_get_psr_wait_loop( 321 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 322 { 323 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 324 return; 325 } 326 327 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 328 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 329 { 330 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 331 uint32_t dmcu_version_offset = 0xf1; 332 333 /* Enable write access to IRAM */ 334 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 335 IRAM_HOST_ACCESS_EN, 1, 336 IRAM_RD_ADDR_AUTO_INC, 1); 337 338 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 339 340 /* Write address to IRAM_RD_ADDR and read from DATA register */ 341 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 342 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 343 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 344 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 345 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 346 REG_READ(DMCU_IRAM_RD_DATA)); 347 348 /* Disable write access to IRAM to allow dynamic sleep state */ 349 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 350 IRAM_HOST_ACCESS_EN, 0, 351 IRAM_RD_ADDR_AUTO_INC, 0); 352 } 353 354 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu, 355 uint32_t fractional_pwm) 356 { 357 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 358 359 /* Wait until microcontroller is ready to process interrupt */ 360 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 361 362 /* Set PWM fractional enable/disable */ 363 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); 364 365 /* Set command to enable or disable fractional PWM microcontroller */ 366 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 367 MCP_BL_SET_PWM_FRAC); 368 369 /* Notify microcontroller of new command */ 370 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 371 372 /* Ensure command has been executed before continuing */ 373 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 374 } 375 376 static bool dcn10_dmcu_init(struct dmcu *dmcu) 377 { 378 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 379 const struct dc_config *config = &dmcu->ctx->dc->config; 380 bool status = false; 381 382 PERF_TRACE(); 383 /* Definition of DC_DMCU_SCRATCH 384 * 0 : firmare not loaded 385 * 1 : PSP load DMCU FW but not initialized 386 * 2 : Firmware already initialized 387 */ 388 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 389 390 switch (dmcu->dmcu_state) { 391 case DMCU_UNLOADED: 392 status = false; 393 break; 394 case DMCU_LOADED_UNINITIALIZED: 395 /* Wait until microcontroller is ready to process interrupt */ 396 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 397 398 /* Set initialized ramping boundary value */ 399 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 400 401 /* Set backlight ramping stepsize */ 402 REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize); 403 404 /* Set command to initialize microcontroller */ 405 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 406 MCP_INIT_DMCU); 407 408 /* Notify microcontroller of new command */ 409 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 410 411 /* Ensure command has been executed before continuing */ 412 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 413 414 // Check state is initialized 415 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 416 417 // If microcontroller is not in running state, fail 418 if (dmcu->dmcu_state == DMCU_RUNNING) { 419 /* Retrieve and cache the DMCU firmware version. */ 420 dcn10_get_dmcu_version(dmcu); 421 422 /* Initialize DMCU to use fractional PWM or not */ 423 dcn10_dmcu_enable_fractional_pwm(dmcu, 424 (config->disable_fractional_pwm == false) ? 1 : 0); 425 status = true; 426 } else { 427 status = false; 428 } 429 430 break; 431 case DMCU_RUNNING: 432 status = true; 433 break; 434 default: 435 status = false; 436 break; 437 } 438 439 PERF_TRACE(); 440 return status; 441 } 442 443 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 444 static bool dcn21_dmcu_init(struct dmcu *dmcu) 445 { 446 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 447 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15); 448 449 if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) { 450 return false; 451 } 452 453 return dcn10_dmcu_init(dmcu); 454 } 455 #endif 456 457 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 458 unsigned int start_offset, 459 const char *src, 460 unsigned int bytes) 461 { 462 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 463 unsigned int count = 0; 464 465 /* If microcontroller is not running, do nothing */ 466 if (dmcu->dmcu_state != DMCU_RUNNING) 467 return false; 468 469 /* Enable write access to IRAM */ 470 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 471 IRAM_HOST_ACCESS_EN, 1, 472 IRAM_WR_ADDR_AUTO_INC, 1); 473 474 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 475 476 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 477 478 for (count = 0; count < bytes; count++) 479 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 480 481 /* Disable write access to IRAM to allow dynamic sleep state */ 482 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 483 IRAM_HOST_ACCESS_EN, 0, 484 IRAM_WR_ADDR_AUTO_INC, 0); 485 486 /* Wait until microcontroller is ready to process interrupt */ 487 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 488 489 /* Set command to signal IRAM is loaded and to initialize IRAM */ 490 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 491 MCP_INIT_IRAM); 492 493 /* Notify microcontroller of new command */ 494 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 495 496 /* Ensure command has been executed before continuing */ 497 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 498 499 return true; 500 } 501 502 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 503 { 504 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 505 506 uint32_t psr_state_offset = 0xf0; 507 508 /* If microcontroller is not running, do nothing */ 509 if (dmcu->dmcu_state != DMCU_RUNNING) 510 return; 511 512 /* Enable write access to IRAM */ 513 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 514 515 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 516 517 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 518 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 519 520 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 521 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 522 523 /* Disable write access to IRAM after finished using IRAM 524 * in order to allow dynamic sleep state 525 */ 526 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 527 } 528 529 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 530 { 531 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 532 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 533 unsigned int dmcu_wait_reg_ready_interval = 100; 534 535 unsigned int retryCount; 536 uint32_t psr_state = 0; 537 538 /* If microcontroller is not running, do nothing */ 539 if (dmcu->dmcu_state != DMCU_RUNNING) 540 return; 541 542 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 543 if (psr_state == 0 && !enable) 544 return; 545 /* waitDMCUReadyForCmd */ 546 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 547 dmcu_wait_reg_ready_interval, 548 dmcu_max_retry_on_wait_reg_ready); 549 550 /* setDMCUParam_Cmd */ 551 if (enable) 552 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 553 PSR_ENABLE); 554 else 555 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 556 PSR_EXIT); 557 558 /* notifyDMCUMsg */ 559 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 560 561 /* Below loops 1000 x 500us = 500 ms. 562 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 563 * least a few frames. Should never hit the max retry assert below. 564 */ 565 if (wait == true) { 566 for (retryCount = 0; retryCount <= 1000; retryCount++) { 567 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 568 if (enable) { 569 if (psr_state != 0) 570 break; 571 } else { 572 if (psr_state == 0) 573 break; 574 } 575 udelay(500); 576 } 577 578 /* assert if max retry hit */ 579 if (retryCount >= 1000) 580 ASSERT(0); 581 } 582 } 583 584 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 585 struct dc_link *link, 586 struct psr_context *psr_context) 587 { 588 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 589 590 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 591 unsigned int dmcu_wait_reg_ready_interval = 100; 592 593 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 594 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 595 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 596 597 /* If microcontroller is not running, do nothing */ 598 if (dmcu->dmcu_state != DMCU_RUNNING) 599 return false; 600 601 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 602 psr_context->psrExitLinkTrainingRequired); 603 604 /* Enable static screen interrupts for PSR supported display */ 605 /* Disable the interrupt coming from other displays. */ 606 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 607 STATIC_SCREEN1_INT_TO_UC_EN, 0, 608 STATIC_SCREEN2_INT_TO_UC_EN, 0, 609 STATIC_SCREEN3_INT_TO_UC_EN, 0, 610 STATIC_SCREEN4_INT_TO_UC_EN, 0); 611 612 switch (psr_context->controllerId) { 613 /* Driver uses case 1 for unconfigured */ 614 case 1: 615 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 616 STATIC_SCREEN1_INT_TO_UC_EN, 1); 617 break; 618 case 2: 619 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 620 STATIC_SCREEN2_INT_TO_UC_EN, 1); 621 break; 622 case 3: 623 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 624 STATIC_SCREEN3_INT_TO_UC_EN, 1); 625 break; 626 case 4: 627 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 628 STATIC_SCREEN4_INT_TO_UC_EN, 1); 629 break; 630 case 5: 631 /* CZ/NL only has 4 CRTC!! 632 * really valid. 633 * There is no interrupt enable mask for these instances. 634 */ 635 break; 636 case 6: 637 /* CZ/NL only has 4 CRTC!! 638 * These are here because they are defined in HW regspec, 639 * but not really valid. There is no interrupt enable mask 640 * for these instances. 641 */ 642 break; 643 default: 644 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 645 STATIC_SCREEN1_INT_TO_UC_EN, 1); 646 break; 647 } 648 649 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 650 psr_context->sdpTransmitLineNumDeadline); 651 652 if (psr_context->allow_smu_optimizations) 653 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 654 655 /* waitDMCUReadyForCmd */ 656 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 657 dmcu_wait_reg_ready_interval, 658 dmcu_max_retry_on_wait_reg_ready); 659 660 /* setDMCUParam_PSRHostConfigData */ 661 masterCmdData1.u32All = 0; 662 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 663 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 664 masterCmdData1.bits.rfb_update_auto_en = 665 psr_context->rfb_update_auto_en; 666 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 667 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 668 masterCmdData1.bits.phy_type = psr_context->phyType; 669 masterCmdData1.bits.frame_cap_ind = 670 psr_context->psrFrameCaptureIndicationReq; 671 masterCmdData1.bits.aux_chan = psr_context->channel; 672 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 673 masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations; 674 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 675 masterCmdData1.u32All); 676 677 masterCmdData2.u32All = 0; 678 masterCmdData2.bits.dig_fe = psr_context->engineId; 679 masterCmdData2.bits.dig_be = psr_context->transmitterId; 680 masterCmdData2.bits.skip_wait_for_pll_lock = 681 psr_context->skipPsrWaitForPllLock; 682 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 683 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 684 masterCmdData2.bits.num_of_controllers = 685 psr_context->numberOfControllers; 686 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 687 masterCmdData2.u32All); 688 689 masterCmdData3.u32All = 0; 690 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 691 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 692 masterCmdData3.u32All); 693 694 695 /* setDMCUParam_Cmd */ 696 REG_UPDATE(MASTER_COMM_CMD_REG, 697 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 698 699 /* notifyDMCUMsg */ 700 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 701 702 /* waitDMCUReadyForCmd */ 703 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 704 705 return true; 706 } 707 708 static void dcn10_psr_wait_loop( 709 struct dmcu *dmcu, 710 unsigned int wait_loop_number) 711 { 712 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 713 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 714 715 /* If microcontroller is not running, do nothing */ 716 if (dmcu->dmcu_state != DMCU_RUNNING) 717 return; 718 719 if (wait_loop_number != 0) { 720 /* waitDMCUReadyForCmd */ 721 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 722 723 masterCmdData1.u32 = 0; 724 masterCmdData1.bits.wait_loop = wait_loop_number; 725 dmcu->cached_wait_loop_number = wait_loop_number; 726 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 727 728 /* setDMCUParam_Cmd */ 729 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 730 731 /* notifyDMCUMsg */ 732 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 733 } 734 } 735 736 static void dcn10_get_psr_wait_loop( 737 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 738 { 739 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 740 return; 741 } 742 743 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 744 { 745 /* microcontroller is not running */ 746 if (dmcu->dmcu_state != DMCU_RUNNING) 747 return false; 748 return true; 749 } 750 751 752 753 static bool dcn20_lock_phy(struct dmcu *dmcu) 754 { 755 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 756 757 /* If microcontroller is not running, do nothing */ 758 if (dmcu->dmcu_state != DMCU_RUNNING) 759 return false; 760 761 /* waitDMCUReadyForCmd */ 762 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 763 764 /* setDMCUParam_Cmd */ 765 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK); 766 767 /* notifyDMCUMsg */ 768 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 769 770 /* waitDMCUReadyForCmd */ 771 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 772 773 return true; 774 } 775 776 static bool dcn20_unlock_phy(struct dmcu *dmcu) 777 { 778 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 779 780 /* If microcontroller is not running, do nothing */ 781 if (dmcu->dmcu_state != DMCU_RUNNING) 782 return false; 783 784 /* waitDMCUReadyForCmd */ 785 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 786 787 /* setDMCUParam_Cmd */ 788 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK); 789 790 /* notifyDMCUMsg */ 791 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 792 793 /* waitDMCUReadyForCmd */ 794 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 795 796 return true; 797 } 798 799 #endif //(CONFIG_DRM_AMD_DC_DCN1_0) 800 801 static const struct dmcu_funcs dce_funcs = { 802 .dmcu_init = dce_dmcu_init, 803 .load_iram = dce_dmcu_load_iram, 804 .set_psr_enable = dce_dmcu_set_psr_enable, 805 .setup_psr = dce_dmcu_setup_psr, 806 .get_psr_state = dce_get_dmcu_psr_state, 807 .set_psr_wait_loop = dce_psr_wait_loop, 808 .get_psr_wait_loop = dce_get_psr_wait_loop, 809 .is_dmcu_initialized = dce_is_dmcu_initialized 810 }; 811 812 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 813 static const struct dmcu_funcs dcn10_funcs = { 814 .dmcu_init = dcn10_dmcu_init, 815 .load_iram = dcn10_dmcu_load_iram, 816 .set_psr_enable = dcn10_dmcu_set_psr_enable, 817 .setup_psr = dcn10_dmcu_setup_psr, 818 .get_psr_state = dcn10_get_dmcu_psr_state, 819 .set_psr_wait_loop = dcn10_psr_wait_loop, 820 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 821 .is_dmcu_initialized = dcn10_is_dmcu_initialized 822 }; 823 824 static const struct dmcu_funcs dcn20_funcs = { 825 .dmcu_init = dcn10_dmcu_init, 826 .load_iram = dcn10_dmcu_load_iram, 827 .set_psr_enable = dcn10_dmcu_set_psr_enable, 828 .setup_psr = dcn10_dmcu_setup_psr, 829 .get_psr_state = dcn10_get_dmcu_psr_state, 830 .set_psr_wait_loop = dcn10_psr_wait_loop, 831 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 832 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 833 .lock_phy = dcn20_lock_phy, 834 .unlock_phy = dcn20_unlock_phy 835 }; 836 837 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 838 static const struct dmcu_funcs dcn21_funcs = { 839 .dmcu_init = dcn21_dmcu_init, 840 .load_iram = dcn10_dmcu_load_iram, 841 .set_psr_enable = dcn10_dmcu_set_psr_enable, 842 .setup_psr = dcn10_dmcu_setup_psr, 843 .get_psr_state = dcn10_get_dmcu_psr_state, 844 .set_psr_wait_loop = dcn10_psr_wait_loop, 845 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 846 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 847 .lock_phy = dcn20_lock_phy, 848 .unlock_phy = dcn20_unlock_phy 849 }; 850 #endif 851 #endif 852 853 static void dce_dmcu_construct( 854 struct dce_dmcu *dmcu_dce, 855 struct dc_context *ctx, 856 const struct dce_dmcu_registers *regs, 857 const struct dce_dmcu_shift *dmcu_shift, 858 const struct dce_dmcu_mask *dmcu_mask) 859 { 860 struct dmcu *base = &dmcu_dce->base; 861 862 base->ctx = ctx; 863 base->funcs = &dce_funcs; 864 base->cached_wait_loop_number = 0; 865 866 dmcu_dce->regs = regs; 867 dmcu_dce->dmcu_shift = dmcu_shift; 868 dmcu_dce->dmcu_mask = dmcu_mask; 869 } 870 871 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 872 static void dcn21_dmcu_construct( 873 struct dce_dmcu *dmcu_dce, 874 struct dc_context *ctx, 875 const struct dce_dmcu_registers *regs, 876 const struct dce_dmcu_shift *dmcu_shift, 877 const struct dce_dmcu_mask *dmcu_mask) 878 { 879 uint32_t psp_version = 0; 880 881 dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 882 883 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 884 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); 885 dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029); 886 dmcu_dce->base.psp_version = psp_version; 887 } 888 } 889 #endif 890 891 struct dmcu *dce_dmcu_create( 892 struct dc_context *ctx, 893 const struct dce_dmcu_registers *regs, 894 const struct dce_dmcu_shift *dmcu_shift, 895 const struct dce_dmcu_mask *dmcu_mask) 896 { 897 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 898 899 if (dmcu_dce == NULL) { 900 BREAK_TO_DEBUGGER(); 901 return NULL; 902 } 903 904 dce_dmcu_construct( 905 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 906 907 dmcu_dce->base.funcs = &dce_funcs; 908 909 return &dmcu_dce->base; 910 } 911 912 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 913 struct dmcu *dcn10_dmcu_create( 914 struct dc_context *ctx, 915 const struct dce_dmcu_registers *regs, 916 const struct dce_dmcu_shift *dmcu_shift, 917 const struct dce_dmcu_mask *dmcu_mask) 918 { 919 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 920 921 if (dmcu_dce == NULL) { 922 BREAK_TO_DEBUGGER(); 923 return NULL; 924 } 925 926 dce_dmcu_construct( 927 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 928 929 dmcu_dce->base.funcs = &dcn10_funcs; 930 931 return &dmcu_dce->base; 932 } 933 934 struct dmcu *dcn20_dmcu_create( 935 struct dc_context *ctx, 936 const struct dce_dmcu_registers *regs, 937 const struct dce_dmcu_shift *dmcu_shift, 938 const struct dce_dmcu_mask *dmcu_mask) 939 { 940 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 941 942 if (dmcu_dce == NULL) { 943 BREAK_TO_DEBUGGER(); 944 return NULL; 945 } 946 947 dce_dmcu_construct( 948 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 949 950 dmcu_dce->base.funcs = &dcn20_funcs; 951 952 return &dmcu_dce->base; 953 } 954 955 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 956 struct dmcu *dcn21_dmcu_create( 957 struct dc_context *ctx, 958 const struct dce_dmcu_registers *regs, 959 const struct dce_dmcu_shift *dmcu_shift, 960 const struct dce_dmcu_mask *dmcu_mask) 961 { 962 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 963 964 if (dmcu_dce == NULL) { 965 BREAK_TO_DEBUGGER(); 966 return NULL; 967 } 968 969 dcn21_dmcu_construct( 970 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 971 972 dmcu_dce->base.funcs = &dcn21_funcs; 973 974 return &dmcu_dce->base; 975 } 976 #endif 977 #endif 978 979 void dce_dmcu_destroy(struct dmcu **dmcu) 980 { 981 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 982 983 kfree(dmcu_dce); 984 *dmcu = NULL; 985 } 986