1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_CLOCK_SOURCE_DCE_H__ 26 #define __DC_CLOCK_SOURCE_DCE_H__ 27 28 #include "../inc/clock_source.h" 29 30 #define TO_DCE110_CLK_SRC(clk_src)\ 31 container_of(clk_src, struct dce110_clk_src, base) 32 33 #define CS_COMMON_REG_LIST_DCE_100_110(id) \ 34 SRI(RESYNC_CNTL, PIXCLK, id), \ 35 SRI(PLL_CNTL, BPHYC_PLL, id) 36 37 #define CS_COMMON_REG_LIST_DCE_80(id) \ 38 SRI(RESYNC_CNTL, PIXCLK, id), \ 39 SRI(PLL_CNTL, DCCG_PLL, id) 40 41 #define CS_COMMON_REG_LIST_DCE_112(id) \ 42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) 43 44 45 #define CS_SF(reg_name, field_name, post_fix)\ 46 .field_name = reg_name ## __ ## field_name ## post_fix 47 48 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ 50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ 51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ 52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) 53 54 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) 57 58 #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \ 59 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 60 SRII(PHASE, DP_DTO, 0),\ 61 SRII(PHASE, DP_DTO, 1),\ 62 SRII(PHASE, DP_DTO, 2),\ 63 SRII(PHASE, DP_DTO, 3),\ 64 SRII(PHASE, DP_DTO, 4),\ 65 SRII(PHASE, DP_DTO, 5),\ 66 SRII(MODULO, DP_DTO, 0),\ 67 SRII(MODULO, DP_DTO, 1),\ 68 SRII(MODULO, DP_DTO, 2),\ 69 SRII(MODULO, DP_DTO, 3),\ 70 SRII(MODULO, DP_DTO, 4),\ 71 SRII(MODULO, DP_DTO, 5),\ 72 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 73 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 74 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 75 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 76 SRII(PIXEL_RATE_CNTL, OTG, 4),\ 77 SRII(PIXEL_RATE_CNTL, OTG, 5) 78 79 #define CS_COMMON_REG_LIST_DCN201(index, pllid) \ 80 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 81 SRII(PHASE, DP_DTO, 0),\ 82 SRII(PHASE, DP_DTO, 1),\ 83 SRII(MODULO, DP_DTO, 0),\ 84 SRII(MODULO, DP_DTO, 1),\ 85 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 86 SRII(PIXEL_RATE_CNTL, OTG, 1) 87 88 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ 89 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 90 SRII(PHASE, DP_DTO, 0),\ 91 SRII(PHASE, DP_DTO, 1),\ 92 SRII(PHASE, DP_DTO, 2),\ 93 SRII(PHASE, DP_DTO, 3),\ 94 SRII(MODULO, DP_DTO, 0),\ 95 SRII(MODULO, DP_DTO, 1),\ 96 SRII(MODULO, DP_DTO, 2),\ 97 SRII(MODULO, DP_DTO, 3),\ 98 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 99 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 100 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 101 SRII(PIXEL_RATE_CNTL, OTG, 3) 102 103 #if defined(CONFIG_DRM_AMD_DC_DCN) 104 #define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \ 105 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 106 SRII(PHASE, DP_DTO, 0),\ 107 SRII(PHASE, DP_DTO, 1),\ 108 SRII(PHASE, DP_DTO, 2),\ 109 SRII(PHASE, DP_DTO, 3),\ 110 SRII(MODULO, DP_DTO, 0),\ 111 SRII(MODULO, DP_DTO, 1),\ 112 SRII(MODULO, DP_DTO, 2),\ 113 SRII(MODULO, DP_DTO, 3),\ 114 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 115 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 116 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 117 SRII(PIXEL_RATE_CNTL, OTG, 3) 118 119 #define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \ 120 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 121 SRII(PHASE, DP_DTO, 0),\ 122 SRII(PHASE, DP_DTO, 1),\ 123 SRII(PHASE, DP_DTO, 2),\ 124 SRII(PHASE, DP_DTO, 3),\ 125 SRII(MODULO, DP_DTO, 0),\ 126 SRII(MODULO, DP_DTO, 1),\ 127 SRII(MODULO, DP_DTO, 2),\ 128 SRII(MODULO, DP_DTO, 3),\ 129 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 130 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 131 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 132 SRII(PIXEL_RATE_CNTL, OTG, 3) 133 #endif 134 135 #if defined(CONFIG_DRM_AMD_DC_DCN) 136 #define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \ 137 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 138 SRII(PHASE, DP_DTO, 0),\ 139 SRII(PHASE, DP_DTO, 1),\ 140 SRII(PHASE, DP_DTO, 2),\ 141 SRII(PHASE, DP_DTO, 3),\ 142 SRII(PHASE, DP_DTO, 4),\ 143 SRII(MODULO, DP_DTO, 0),\ 144 SRII(MODULO, DP_DTO, 1),\ 145 SRII(MODULO, DP_DTO, 2),\ 146 SRII(MODULO, DP_DTO, 3),\ 147 SRII(MODULO, DP_DTO, 4),\ 148 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 149 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 150 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 151 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 152 SRII(PIXEL_RATE_CNTL, OTG, 4) 153 154 #define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \ 155 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 156 SRII(PHASE, DP_DTO, 0),\ 157 SRII(PHASE, DP_DTO, 1),\ 158 SRII(MODULO, DP_DTO, 0),\ 159 SRII(MODULO, DP_DTO, 1),\ 160 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 161 SRII(PIXEL_RATE_CNTL, OTG, 1) 162 163 #endif 164 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ 165 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 166 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 167 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 168 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 169 170 #if defined(CONFIG_DRM_AMD_DC_DCN) 171 172 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ 173 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 174 SRII(PHASE, DP_DTO, 0),\ 175 SRII(PHASE, DP_DTO, 1),\ 176 SRII(PHASE, DP_DTO, 2),\ 177 SRII(PHASE, DP_DTO, 3),\ 178 SRII(MODULO, DP_DTO, 0),\ 179 SRII(MODULO, DP_DTO, 1),\ 180 SRII(MODULO, DP_DTO, 2),\ 181 SRII(MODULO, DP_DTO, 3),\ 182 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 183 SRII(PIXEL_RATE_CNTL, OTG, 1), \ 184 SRII(PIXEL_RATE_CNTL, OTG, 2), \ 185 SRII(PIXEL_RATE_CNTL, OTG, 3) 186 187 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 188 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 189 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 190 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 191 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 192 193 #endif 194 195 #define CS_REG_FIELD_LIST(type) \ 196 type PLL_REF_DIV_SRC; \ 197 type DCCG_DEEP_COLOR_CNTL1; \ 198 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \ 199 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ 200 type PLL_POST_DIV_PIXCLK; \ 201 type PLL_REF_DIV; \ 202 type DP_DTO0_PHASE; \ 203 type DP_DTO0_MODULO; \ 204 type DP_DTO0_ENABLE; 205 206 struct dce110_clk_src_shift { 207 CS_REG_FIELD_LIST(uint8_t) 208 }; 209 210 struct dce110_clk_src_mask{ 211 CS_REG_FIELD_LIST(uint32_t) 212 }; 213 214 struct dce110_clk_src_regs { 215 uint32_t RESYNC_CNTL; 216 uint32_t PIXCLK_RESYNC_CNTL; 217 uint32_t PLL_CNTL; 218 219 /* below are for DTO. 220 * todo: should probably use different struct to not waste space 221 */ 222 uint32_t PHASE[MAX_PIPES]; 223 uint32_t MODULO[MAX_PIPES]; 224 uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; 225 }; 226 227 struct dce110_clk_src { 228 struct clock_source base; 229 const struct dce110_clk_src_regs *regs; 230 const struct dce110_clk_src_mask *cs_mask; 231 const struct dce110_clk_src_shift *cs_shift; 232 struct dc_bios *bios; 233 234 struct spread_spectrum_data *dp_ss_params; 235 uint32_t dp_ss_params_cnt; 236 struct spread_spectrum_data *hdmi_ss_params; 237 uint32_t hdmi_ss_params_cnt; 238 struct spread_spectrum_data *dvi_ss_params; 239 uint32_t dvi_ss_params_cnt; 240 struct spread_spectrum_data *lvds_ss_params; 241 uint32_t lvds_ss_params_cnt; 242 243 uint32_t ext_clk_khz; 244 uint32_t ref_freq_khz; 245 246 struct calc_pll_clock_source calc_pll; 247 struct calc_pll_clock_source calc_pll_hdmi; 248 }; 249 250 bool dce110_clk_src_construct( 251 struct dce110_clk_src *clk_src, 252 struct dc_context *ctx, 253 struct dc_bios *bios, 254 enum clock_source_id, 255 const struct dce110_clk_src_regs *regs, 256 const struct dce110_clk_src_shift *cs_shift, 257 const struct dce110_clk_src_mask *cs_mask); 258 259 bool dce112_clk_src_construct( 260 struct dce110_clk_src *clk_src, 261 struct dc_context *ctx, 262 struct dc_bios *bios, 263 enum clock_source_id id, 264 const struct dce110_clk_src_regs *regs, 265 const struct dce110_clk_src_shift *cs_shift, 266 const struct dce110_clk_src_mask *cs_mask); 267 268 bool dcn20_clk_src_construct( 269 struct dce110_clk_src *clk_src, 270 struct dc_context *ctx, 271 struct dc_bios *bios, 272 enum clock_source_id id, 273 const struct dce110_clk_src_regs *regs, 274 const struct dce110_clk_src_shift *cs_shift, 275 const struct dce110_clk_src_mask *cs_mask); 276 277 #if defined(CONFIG_DRM_AMD_DC_DCN) 278 bool dcn3_clk_src_construct( 279 struct dce110_clk_src *clk_src, 280 struct dc_context *ctx, 281 struct dc_bios *bios, 282 enum clock_source_id id, 283 const struct dce110_clk_src_regs *regs, 284 const struct dce110_clk_src_shift *cs_shift, 285 const struct dce110_clk_src_mask *cs_mask); 286 287 bool dcn301_clk_src_construct( 288 struct dce110_clk_src *clk_src, 289 struct dc_context *ctx, 290 struct dc_bios *bios, 291 enum clock_source_id id, 292 const struct dce110_clk_src_regs *regs, 293 const struct dce110_clk_src_shift *cs_shift, 294 const struct dce110_clk_src_mask *cs_mask); 295 296 bool dcn31_clk_src_construct( 297 struct dce110_clk_src *clk_src, 298 struct dc_context *ctx, 299 struct dc_bios *bios, 300 enum clock_source_id id, 301 const struct dce110_clk_src_regs *regs, 302 const struct dce110_clk_src_shift *cs_shift, 303 const struct dce110_clk_src_mask *cs_mask); 304 #endif 305 306 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ 307 struct pixel_rate_range_table_entry { 308 unsigned int range_min_khz; 309 unsigned int range_max_khz; 310 unsigned int target_pixel_rate_khz; 311 unsigned short mult_factor; 312 unsigned short div_factor; 313 }; 314 315 #if defined(CONFIG_DRM_AMD_DC_DCN) 316 extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[]; 317 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( 318 unsigned int pixel_rate_khz); 319 #endif 320 321 #endif 322