1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_CLOCK_SOURCE_DCE_H__ 26 #define __DC_CLOCK_SOURCE_DCE_H__ 27 28 #include "../inc/clock_source.h" 29 30 #define TO_DCE110_CLK_SRC(clk_src)\ 31 container_of(clk_src, struct dce110_clk_src, base) 32 33 #define CS_COMMON_REG_LIST_DCE_100_110(id) \ 34 SRI(RESYNC_CNTL, PIXCLK, id), \ 35 SRI(PLL_CNTL, BPHYC_PLL, id) 36 37 #define CS_COMMON_REG_LIST_DCE_80(id) \ 38 SRI(RESYNC_CNTL, PIXCLK, id), \ 39 SRI(PLL_CNTL, DCCG_PLL, id) 40 41 #define CS_COMMON_REG_LIST_DCE_112(id) \ 42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) 43 44 45 #define CS_SF(reg_name, field_name, post_fix)\ 46 .field_name = reg_name ## __ ## field_name ## post_fix 47 48 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ 50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ 51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ 52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) 53 54 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) 57 58 #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \ 59 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 60 SRII(PHASE, DP_DTO, 0),\ 61 SRII(PHASE, DP_DTO, 1),\ 62 SRII(PHASE, DP_DTO, 2),\ 63 SRII(PHASE, DP_DTO, 3),\ 64 SRII(PHASE, DP_DTO, 4),\ 65 SRII(PHASE, DP_DTO, 5),\ 66 SRII(MODULO, DP_DTO, 0),\ 67 SRII(MODULO, DP_DTO, 1),\ 68 SRII(MODULO, DP_DTO, 2),\ 69 SRII(MODULO, DP_DTO, 3),\ 70 SRII(MODULO, DP_DTO, 4),\ 71 SRII(MODULO, DP_DTO, 5),\ 72 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 73 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 74 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 75 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 76 SRII(PIXEL_RATE_CNTL, OTG, 4),\ 77 SRII(PIXEL_RATE_CNTL, OTG, 5) 78 79 #define CS_COMMON_REG_LIST_DCN201(index, pllid) \ 80 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 81 SRII(PHASE, DP_DTO, 0),\ 82 SRII(PHASE, DP_DTO, 1),\ 83 SRII(MODULO, DP_DTO, 0),\ 84 SRII(MODULO, DP_DTO, 1),\ 85 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 86 SRII(PIXEL_RATE_CNTL, OTG, 1) 87 88 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ 89 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 90 SRII(PHASE, DP_DTO, 0),\ 91 SRII(PHASE, DP_DTO, 1),\ 92 SRII(PHASE, DP_DTO, 2),\ 93 SRII(PHASE, DP_DTO, 3),\ 94 SRII(MODULO, DP_DTO, 0),\ 95 SRII(MODULO, DP_DTO, 1),\ 96 SRII(MODULO, DP_DTO, 2),\ 97 SRII(MODULO, DP_DTO, 3),\ 98 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 99 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 100 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 101 SRII(PIXEL_RATE_CNTL, OTG, 3) 102 103 #define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \ 104 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 105 SRII(PHASE, DP_DTO, 0),\ 106 SRII(PHASE, DP_DTO, 1),\ 107 SRII(PHASE, DP_DTO, 2),\ 108 SRII(PHASE, DP_DTO, 3),\ 109 SRII(MODULO, DP_DTO, 0),\ 110 SRII(MODULO, DP_DTO, 1),\ 111 SRII(MODULO, DP_DTO, 2),\ 112 SRII(MODULO, DP_DTO, 3),\ 113 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 114 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 115 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 116 SRII(PIXEL_RATE_CNTL, OTG, 3) 117 118 #define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \ 119 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 120 SRII(PHASE, DP_DTO, 0),\ 121 SRII(PHASE, DP_DTO, 1),\ 122 SRII(PHASE, DP_DTO, 2),\ 123 SRII(PHASE, DP_DTO, 3),\ 124 SRII(MODULO, DP_DTO, 0),\ 125 SRII(MODULO, DP_DTO, 1),\ 126 SRII(MODULO, DP_DTO, 2),\ 127 SRII(MODULO, DP_DTO, 3),\ 128 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 129 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 130 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 131 SRII(PIXEL_RATE_CNTL, OTG, 3) 132 133 #define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \ 134 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 135 SRII(PHASE, DP_DTO, 0),\ 136 SRII(PHASE, DP_DTO, 1),\ 137 SRII(PHASE, DP_DTO, 2),\ 138 SRII(PHASE, DP_DTO, 3),\ 139 SRII(PHASE, DP_DTO, 4),\ 140 SRII(MODULO, DP_DTO, 0),\ 141 SRII(MODULO, DP_DTO, 1),\ 142 SRII(MODULO, DP_DTO, 2),\ 143 SRII(MODULO, DP_DTO, 3),\ 144 SRII(MODULO, DP_DTO, 4),\ 145 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 146 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 147 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 148 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 149 SRII(PIXEL_RATE_CNTL, OTG, 4) 150 151 #define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \ 152 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 153 SRII(PHASE, DP_DTO, 0),\ 154 SRII(PHASE, DP_DTO, 1),\ 155 SRII(MODULO, DP_DTO, 0),\ 156 SRII(MODULO, DP_DTO, 1),\ 157 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 158 SRII(PIXEL_RATE_CNTL, OTG, 1) 159 160 161 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ 162 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 163 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 164 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 165 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 166 167 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ 168 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 169 SRII(PHASE, DP_DTO, 0),\ 170 SRII(PHASE, DP_DTO, 1),\ 171 SRII(PHASE, DP_DTO, 2),\ 172 SRII(PHASE, DP_DTO, 3),\ 173 SRII(MODULO, DP_DTO, 0),\ 174 SRII(MODULO, DP_DTO, 1),\ 175 SRII(MODULO, DP_DTO, 2),\ 176 SRII(MODULO, DP_DTO, 3),\ 177 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 178 SRII(PIXEL_RATE_CNTL, OTG, 1), \ 179 SRII(PIXEL_RATE_CNTL, OTG, 2), \ 180 SRII(PIXEL_RATE_CNTL, OTG, 3) 181 182 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 183 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 184 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 185 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 186 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 187 188 189 #define CS_REG_FIELD_LIST(type) \ 190 type PLL_REF_DIV_SRC; \ 191 type DCCG_DEEP_COLOR_CNTL1; \ 192 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \ 193 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ 194 type PLL_POST_DIV_PIXCLK; \ 195 type PLL_REF_DIV; \ 196 type DP_DTO0_PHASE; \ 197 type DP_DTO0_MODULO; \ 198 type DP_DTO0_ENABLE; 199 200 struct dce110_clk_src_shift { 201 CS_REG_FIELD_LIST(uint8_t) 202 }; 203 204 struct dce110_clk_src_mask{ 205 CS_REG_FIELD_LIST(uint32_t) 206 }; 207 208 struct dce110_clk_src_regs { 209 uint32_t RESYNC_CNTL; 210 uint32_t PIXCLK_RESYNC_CNTL; 211 uint32_t PLL_CNTL; 212 213 /* below are for DTO. 214 * todo: should probably use different struct to not waste space 215 */ 216 uint32_t PHASE[MAX_PIPES]; 217 uint32_t MODULO[MAX_PIPES]; 218 uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; 219 }; 220 221 struct dce110_clk_src { 222 struct clock_source base; 223 const struct dce110_clk_src_regs *regs; 224 const struct dce110_clk_src_mask *cs_mask; 225 const struct dce110_clk_src_shift *cs_shift; 226 struct dc_bios *bios; 227 228 struct spread_spectrum_data *dp_ss_params; 229 uint32_t dp_ss_params_cnt; 230 struct spread_spectrum_data *hdmi_ss_params; 231 uint32_t hdmi_ss_params_cnt; 232 struct spread_spectrum_data *dvi_ss_params; 233 uint32_t dvi_ss_params_cnt; 234 struct spread_spectrum_data *lvds_ss_params; 235 uint32_t lvds_ss_params_cnt; 236 237 uint32_t ext_clk_khz; 238 uint32_t ref_freq_khz; 239 240 struct calc_pll_clock_source calc_pll; 241 struct calc_pll_clock_source calc_pll_hdmi; 242 }; 243 244 bool dce110_clk_src_construct( 245 struct dce110_clk_src *clk_src, 246 struct dc_context *ctx, 247 struct dc_bios *bios, 248 enum clock_source_id, 249 const struct dce110_clk_src_regs *regs, 250 const struct dce110_clk_src_shift *cs_shift, 251 const struct dce110_clk_src_mask *cs_mask); 252 253 bool dce112_clk_src_construct( 254 struct dce110_clk_src *clk_src, 255 struct dc_context *ctx, 256 struct dc_bios *bios, 257 enum clock_source_id id, 258 const struct dce110_clk_src_regs *regs, 259 const struct dce110_clk_src_shift *cs_shift, 260 const struct dce110_clk_src_mask *cs_mask); 261 262 bool dcn20_clk_src_construct( 263 struct dce110_clk_src *clk_src, 264 struct dc_context *ctx, 265 struct dc_bios *bios, 266 enum clock_source_id id, 267 const struct dce110_clk_src_regs *regs, 268 const struct dce110_clk_src_shift *cs_shift, 269 const struct dce110_clk_src_mask *cs_mask); 270 271 bool dcn3_clk_src_construct( 272 struct dce110_clk_src *clk_src, 273 struct dc_context *ctx, 274 struct dc_bios *bios, 275 enum clock_source_id id, 276 const struct dce110_clk_src_regs *regs, 277 const struct dce110_clk_src_shift *cs_shift, 278 const struct dce110_clk_src_mask *cs_mask); 279 280 bool dcn301_clk_src_construct( 281 struct dce110_clk_src *clk_src, 282 struct dc_context *ctx, 283 struct dc_bios *bios, 284 enum clock_source_id id, 285 const struct dce110_clk_src_regs *regs, 286 const struct dce110_clk_src_shift *cs_shift, 287 const struct dce110_clk_src_mask *cs_mask); 288 289 bool dcn31_clk_src_construct( 290 struct dce110_clk_src *clk_src, 291 struct dc_context *ctx, 292 struct dc_bios *bios, 293 enum clock_source_id id, 294 const struct dce110_clk_src_regs *regs, 295 const struct dce110_clk_src_shift *cs_shift, 296 const struct dce110_clk_src_mask *cs_mask); 297 298 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ 299 struct pixel_rate_range_table_entry { 300 unsigned int range_min_khz; 301 unsigned int range_max_khz; 302 unsigned int target_pixel_rate_khz; 303 unsigned short mult_factor; 304 unsigned short div_factor; 305 }; 306 307 extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[]; 308 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( 309 unsigned int pixel_rate_khz); 310 311 #endif 312