1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 29 #include "dc_types.h" 30 #include "core_types.h" 31 32 #include "include/grph_object_id.h" 33 #include "include/logger_interface.h" 34 35 #include "dce_clock_source.h" 36 37 #include "reg_helper.h" 38 39 #define REG(reg)\ 40 (clk_src->regs->reg) 41 42 #define CTX \ 43 clk_src->base.ctx 44 45 #define DC_LOGGER_INIT() 46 47 #undef FN 48 #define FN(reg_name, field_name) \ 49 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name 50 51 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6 52 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1 53 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF 54 55 static const struct spread_spectrum_data *get_ss_data_entry( 56 struct dce110_clk_src *clk_src, 57 enum signal_type signal, 58 uint32_t pix_clk_khz) 59 { 60 61 uint32_t entrys_num; 62 uint32_t i; 63 struct spread_spectrum_data *ss_parm = NULL; 64 struct spread_spectrum_data *ret = NULL; 65 66 switch (signal) { 67 case SIGNAL_TYPE_DVI_SINGLE_LINK: 68 case SIGNAL_TYPE_DVI_DUAL_LINK: 69 ss_parm = clk_src->dvi_ss_params; 70 entrys_num = clk_src->dvi_ss_params_cnt; 71 break; 72 73 case SIGNAL_TYPE_HDMI_TYPE_A: 74 ss_parm = clk_src->hdmi_ss_params; 75 entrys_num = clk_src->hdmi_ss_params_cnt; 76 break; 77 78 case SIGNAL_TYPE_LVDS: 79 ss_parm = clk_src->lvds_ss_params; 80 entrys_num = clk_src->lvds_ss_params_cnt; 81 break; 82 83 case SIGNAL_TYPE_DISPLAY_PORT: 84 case SIGNAL_TYPE_DISPLAY_PORT_MST: 85 case SIGNAL_TYPE_EDP: 86 case SIGNAL_TYPE_VIRTUAL: 87 ss_parm = clk_src->dp_ss_params; 88 entrys_num = clk_src->dp_ss_params_cnt; 89 break; 90 91 default: 92 ss_parm = NULL; 93 entrys_num = 0; 94 break; 95 } 96 97 if (ss_parm == NULL) 98 return ret; 99 100 for (i = 0; i < entrys_num; ++i, ++ss_parm) { 101 if (ss_parm->freq_range_khz >= pix_clk_khz) { 102 ret = ss_parm; 103 break; 104 } 105 } 106 107 return ret; 108 } 109 110 /** 111 * Function: calculate_fb_and_fractional_fb_divider 112 * 113 * * DESCRIPTION: Calculates feedback and fractional feedback dividers values 114 * 115 *PARAMETERS: 116 * targetPixelClock Desired frequency in 100 Hz 117 * ref_divider Reference divider (already known) 118 * postDivider Post Divider (already known) 119 * feedback_divider_param Pointer where to store 120 * calculated feedback divider value 121 * fract_feedback_divider_param Pointer where to store 122 * calculated fract feedback divider value 123 * 124 *RETURNS: 125 * It fills the locations pointed by feedback_divider_param 126 * and fract_feedback_divider_param 127 * It returns - true if feedback divider not 0 128 * - false should never happen) 129 */ 130 static bool calculate_fb_and_fractional_fb_divider( 131 struct calc_pll_clock_source *calc_pll_cs, 132 uint32_t target_pix_clk_100hz, 133 uint32_t ref_divider, 134 uint32_t post_divider, 135 uint32_t *feedback_divider_param, 136 uint32_t *fract_feedback_divider_param) 137 { 138 uint64_t feedback_divider; 139 140 feedback_divider = 141 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; 142 feedback_divider *= 10; 143 /* additional factor, since we divide by 10 afterwards */ 144 feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor); 145 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull); 146 147 /*Round to the number of precision 148 * The following code replace the old code (ullfeedbackDivider + 5)/10 149 * for example if the difference between the number 150 * of fractional feedback decimal point and the fractional FB Divider precision 151 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ 152 153 feedback_divider += 5ULL * 154 calc_pll_cs->fract_fb_divider_precision_factor; 155 feedback_divider = 156 div_u64(feedback_divider, 157 calc_pll_cs->fract_fb_divider_precision_factor * 10); 158 feedback_divider *= (uint64_t) 159 (calc_pll_cs->fract_fb_divider_precision_factor); 160 161 *feedback_divider_param = 162 div_u64_rem( 163 feedback_divider, 164 calc_pll_cs->fract_fb_divider_factor, 165 fract_feedback_divider_param); 166 167 if (*feedback_divider_param != 0) 168 return true; 169 return false; 170 } 171 172 /** 173 *calc_fb_divider_checking_tolerance 174 * 175 *DESCRIPTION: Calculates Feedback and Fractional Feedback divider values 176 * for passed Reference and Post divider, checking for tolerance. 177 *PARAMETERS: 178 * pll_settings Pointer to structure 179 * ref_divider Reference divider (already known) 180 * postDivider Post Divider (already known) 181 * tolerance Tolerance for Calculated Pixel Clock to be within 182 * 183 *RETURNS: 184 * It fills the PLLSettings structure with PLL Dividers values 185 * if calculated values are within required tolerance 186 * It returns - true if eror is within tolerance 187 * - false if eror is not within tolerance 188 */ 189 static bool calc_fb_divider_checking_tolerance( 190 struct calc_pll_clock_source *calc_pll_cs, 191 struct pll_settings *pll_settings, 192 uint32_t ref_divider, 193 uint32_t post_divider, 194 uint32_t tolerance) 195 { 196 uint32_t feedback_divider; 197 uint32_t fract_feedback_divider; 198 uint32_t actual_calculated_clock_100hz; 199 uint32_t abs_err; 200 uint64_t actual_calc_clk_100hz; 201 202 calculate_fb_and_fractional_fb_divider( 203 calc_pll_cs, 204 pll_settings->adjusted_pix_clk_100hz, 205 ref_divider, 206 post_divider, 207 &feedback_divider, 208 &fract_feedback_divider); 209 210 /*Actual calculated value*/ 211 actual_calc_clk_100hz = (uint64_t)feedback_divider * 212 calc_pll_cs->fract_fb_divider_factor + 213 fract_feedback_divider; 214 actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10; 215 actual_calc_clk_100hz = 216 div_u64(actual_calc_clk_100hz, 217 ref_divider * post_divider * 218 calc_pll_cs->fract_fb_divider_factor); 219 220 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz); 221 222 abs_err = (actual_calculated_clock_100hz > 223 pll_settings->adjusted_pix_clk_100hz) 224 ? actual_calculated_clock_100hz - 225 pll_settings->adjusted_pix_clk_100hz 226 : pll_settings->adjusted_pix_clk_100hz - 227 actual_calculated_clock_100hz; 228 229 if (abs_err <= tolerance) { 230 /*found good values*/ 231 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; 232 pll_settings->reference_divider = ref_divider; 233 pll_settings->feedback_divider = feedback_divider; 234 pll_settings->fract_feedback_divider = fract_feedback_divider; 235 pll_settings->pix_clk_post_divider = post_divider; 236 pll_settings->calculated_pix_clk_100hz = 237 actual_calculated_clock_100hz; 238 pll_settings->vco_freq = 239 actual_calculated_clock_100hz * post_divider / 10; 240 return true; 241 } 242 return false; 243 } 244 245 static bool calc_pll_dividers_in_range( 246 struct calc_pll_clock_source *calc_pll_cs, 247 struct pll_settings *pll_settings, 248 uint32_t min_ref_divider, 249 uint32_t max_ref_divider, 250 uint32_t min_post_divider, 251 uint32_t max_post_divider, 252 uint32_t err_tolerance) 253 { 254 uint32_t ref_divider; 255 uint32_t post_divider; 256 uint32_t tolerance; 257 258 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25% 259 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/ 260 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) / 261 100000; 262 if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE) 263 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE; 264 265 for ( 266 post_divider = max_post_divider; 267 post_divider >= min_post_divider; 268 --post_divider) { 269 for ( 270 ref_divider = min_ref_divider; 271 ref_divider <= max_ref_divider; 272 ++ref_divider) { 273 if (calc_fb_divider_checking_tolerance( 274 calc_pll_cs, 275 pll_settings, 276 ref_divider, 277 post_divider, 278 tolerance)) { 279 return true; 280 } 281 } 282 } 283 284 return false; 285 } 286 287 static uint32_t calculate_pixel_clock_pll_dividers( 288 struct calc_pll_clock_source *calc_pll_cs, 289 struct pll_settings *pll_settings) 290 { 291 uint32_t err_tolerance; 292 uint32_t min_post_divider; 293 uint32_t max_post_divider; 294 uint32_t min_ref_divider; 295 uint32_t max_ref_divider; 296 297 if (pll_settings->adjusted_pix_clk_100hz == 0) { 298 DC_LOG_ERROR( 299 "%s Bad requested pixel clock", __func__); 300 return MAX_PLL_CALC_ERROR; 301 } 302 303 /* 1) Find Post divider ranges */ 304 if (pll_settings->pix_clk_post_divider) { 305 min_post_divider = pll_settings->pix_clk_post_divider; 306 max_post_divider = pll_settings->pix_clk_post_divider; 307 } else { 308 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider; 309 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz < 310 calc_pll_cs->min_vco_khz * 10) { 311 min_post_divider = calc_pll_cs->min_vco_khz * 10 / 312 pll_settings->adjusted_pix_clk_100hz; 313 if ((min_post_divider * 314 pll_settings->adjusted_pix_clk_100hz) < 315 calc_pll_cs->min_vco_khz * 10) 316 min_post_divider++; 317 } 318 319 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider; 320 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz 321 > calc_pll_cs->max_vco_khz * 10) 322 max_post_divider = calc_pll_cs->max_vco_khz * 10 / 323 pll_settings->adjusted_pix_clk_100hz; 324 } 325 326 /* 2) Find Reference divider ranges 327 * When SS is enabled, or for Display Port even without SS, 328 * pll_settings->referenceDivider is not zero. 329 * So calculate PPLL FB and fractional FB divider 330 * using the passed reference divider*/ 331 332 if (pll_settings->reference_divider) { 333 min_ref_divider = pll_settings->reference_divider; 334 max_ref_divider = pll_settings->reference_divider; 335 } else { 336 min_ref_divider = ((calc_pll_cs->ref_freq_khz 337 / calc_pll_cs->max_pll_input_freq_khz) 338 > calc_pll_cs->min_pll_ref_divider) 339 ? calc_pll_cs->ref_freq_khz 340 / calc_pll_cs->max_pll_input_freq_khz 341 : calc_pll_cs->min_pll_ref_divider; 342 343 max_ref_divider = ((calc_pll_cs->ref_freq_khz 344 / calc_pll_cs->min_pll_input_freq_khz) 345 < calc_pll_cs->max_pll_ref_divider) 346 ? calc_pll_cs->ref_freq_khz / 347 calc_pll_cs->min_pll_input_freq_khz 348 : calc_pll_cs->max_pll_ref_divider; 349 } 350 351 /* If some parameters are invalid we could have scenario when "min">"max" 352 * which produced endless loop later. 353 * We should investigate why we get the wrong parameters. 354 * But to follow the similar logic when "adjustedPixelClock" is set to be 0 355 * it is better to return here than cause system hang/watchdog timeout later. 356 * ## SVS Wed 15 Jul 2009 */ 357 358 if (min_post_divider > max_post_divider) { 359 DC_LOG_ERROR( 360 "%s Post divider range is invalid", __func__); 361 return MAX_PLL_CALC_ERROR; 362 } 363 364 if (min_ref_divider > max_ref_divider) { 365 DC_LOG_ERROR( 366 "%s Reference divider range is invalid", __func__); 367 return MAX_PLL_CALC_ERROR; 368 } 369 370 /* 3) Try to find PLL dividers given ranges 371 * starting with minimal error tolerance. 372 * Increase error tolerance until PLL dividers found*/ 373 err_tolerance = MAX_PLL_CALC_ERROR; 374 375 while (!calc_pll_dividers_in_range( 376 calc_pll_cs, 377 pll_settings, 378 min_ref_divider, 379 max_ref_divider, 380 min_post_divider, 381 max_post_divider, 382 err_tolerance)) 383 err_tolerance += (err_tolerance > 10) 384 ? (err_tolerance / 10) 385 : 1; 386 387 return err_tolerance; 388 } 389 390 static bool pll_adjust_pix_clk( 391 struct dce110_clk_src *clk_src, 392 struct pixel_clk_params *pix_clk_params, 393 struct pll_settings *pll_settings) 394 { 395 uint32_t actual_pix_clk_100hz = 0; 396 uint32_t requested_clk_100hz = 0; 397 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = { 398 0 }; 399 enum bp_result bp_result; 400 switch (pix_clk_params->signal_type) { 401 case SIGNAL_TYPE_HDMI_TYPE_A: { 402 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 403 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 404 switch (pix_clk_params->color_depth) { 405 case COLOR_DEPTH_101010: 406 requested_clk_100hz = (requested_clk_100hz * 5) >> 2; 407 break; /* x1.25*/ 408 case COLOR_DEPTH_121212: 409 requested_clk_100hz = (requested_clk_100hz * 6) >> 2; 410 break; /* x1.5*/ 411 case COLOR_DEPTH_161616: 412 requested_clk_100hz = requested_clk_100hz * 2; 413 break; /* x2.0*/ 414 default: 415 break; 416 } 417 } 418 actual_pix_clk_100hz = requested_clk_100hz; 419 } 420 break; 421 422 case SIGNAL_TYPE_DISPLAY_PORT: 423 case SIGNAL_TYPE_DISPLAY_PORT_MST: 424 case SIGNAL_TYPE_EDP: 425 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10; 426 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 427 break; 428 429 default: 430 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 431 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 432 break; 433 } 434 435 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10; 436 bp_adjust_pixel_clock_params. 437 encoder_object_id = pix_clk_params->encoder_object_id; 438 bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; 439 bp_adjust_pixel_clock_params. 440 ss_enable = pix_clk_params->flags.ENABLE_SS; 441 bp_result = clk_src->bios->funcs->adjust_pixel_clock( 442 clk_src->bios, &bp_adjust_pixel_clock_params); 443 if (bp_result == BP_RESULT_OK) { 444 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz; 445 pll_settings->adjusted_pix_clk_100hz = 446 bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10; 447 pll_settings->reference_divider = 448 bp_adjust_pixel_clock_params.reference_divider; 449 pll_settings->pix_clk_post_divider = 450 bp_adjust_pixel_clock_params.pixel_clock_post_divider; 451 452 return true; 453 } 454 455 return false; 456 } 457 458 /** 459 * Calculate PLL Dividers for given Clock Value. 460 * First will call VBIOS Adjust Exec table to check if requested Pixel clock 461 * will be Adjusted based on usage. 462 * Then it will calculate PLL Dividers for this Adjusted clock using preferred 463 * method (Maximum VCO frequency). 464 * 465 * \return 466 * Calculation error in units of 0.01% 467 */ 468 469 static uint32_t dce110_get_pix_clk_dividers_helper ( 470 struct dce110_clk_src *clk_src, 471 struct pll_settings *pll_settings, 472 struct pixel_clk_params *pix_clk_params) 473 { 474 uint32_t field = 0; 475 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 476 DC_LOGGER_INIT(); 477 /* Check if reference clock is external (not pcie/xtalin) 478 * HW Dce80 spec: 479 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB 480 * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */ 481 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field); 482 pll_settings->use_external_clk = (field > 1); 483 484 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always 485 * (we do not care any more from SI for some older DP Sink which 486 * does not report SS support, no known issues) */ 487 if ((pix_clk_params->flags.ENABLE_SS) || 488 (dc_is_dp_signal(pix_clk_params->signal_type))) { 489 490 const struct spread_spectrum_data *ss_data = get_ss_data_entry( 491 clk_src, 492 pix_clk_params->signal_type, 493 pll_settings->adjusted_pix_clk_100hz / 10); 494 495 if (NULL != ss_data) 496 pll_settings->ss_percentage = ss_data->percentage; 497 } 498 499 /* Check VBIOS AdjustPixelClock Exec table */ 500 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) { 501 /* Should never happen, ASSERT and fill up values to be able 502 * to continue. */ 503 DC_LOG_ERROR( 504 "%s: Failed to adjust pixel clock!!", __func__); 505 pll_settings->actual_pix_clk_100hz = 506 pix_clk_params->requested_pix_clk_100hz; 507 pll_settings->adjusted_pix_clk_100hz = 508 pix_clk_params->requested_pix_clk_100hz; 509 510 if (dc_is_dp_signal(pix_clk_params->signal_type)) 511 pll_settings->adjusted_pix_clk_100hz = 1000000; 512 } 513 514 /* Calculate Dividers */ 515 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) 516 /*Calculate Dividers by HDMI object, no SS case or SS case */ 517 pll_calc_error = 518 calculate_pixel_clock_pll_dividers( 519 &clk_src->calc_pll_hdmi, 520 pll_settings); 521 else 522 /*Calculate Dividers by default object, no SS case or SS case */ 523 pll_calc_error = 524 calculate_pixel_clock_pll_dividers( 525 &clk_src->calc_pll, 526 pll_settings); 527 528 return pll_calc_error; 529 } 530 531 static void dce112_get_pix_clk_dividers_helper ( 532 struct dce110_clk_src *clk_src, 533 struct pll_settings *pll_settings, 534 struct pixel_clk_params *pix_clk_params) 535 { 536 uint32_t actual_pixel_clock_100hz; 537 538 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz; 539 /* Calculate Dividers */ 540 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 541 switch (pix_clk_params->color_depth) { 542 case COLOR_DEPTH_101010: 543 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; 544 break; 545 case COLOR_DEPTH_121212: 546 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; 547 break; 548 case COLOR_DEPTH_161616: 549 actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; 550 break; 551 default: 552 break; 553 } 554 } 555 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz; 556 pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz; 557 pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 558 } 559 560 static uint32_t dce110_get_pix_clk_dividers( 561 struct clock_source *cs, 562 struct pixel_clk_params *pix_clk_params, 563 struct pll_settings *pll_settings) 564 { 565 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 566 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 567 DC_LOGGER_INIT(); 568 569 if (pix_clk_params == NULL || pll_settings == NULL 570 || pix_clk_params->requested_pix_clk_100hz == 0) { 571 DC_LOG_ERROR( 572 "%s: Invalid parameters!!\n", __func__); 573 return pll_calc_error; 574 } 575 576 memset(pll_settings, 0, sizeof(*pll_settings)); 577 578 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 579 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 580 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 581 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 582 pll_settings->actual_pix_clk_100hz = 583 pix_clk_params->requested_pix_clk_100hz; 584 return 0; 585 } 586 587 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src, 588 pll_settings, pix_clk_params); 589 590 return pll_calc_error; 591 } 592 593 static uint32_t dce112_get_pix_clk_dividers( 594 struct clock_source *cs, 595 struct pixel_clk_params *pix_clk_params, 596 struct pll_settings *pll_settings) 597 { 598 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 599 DC_LOGGER_INIT(); 600 601 if (pix_clk_params == NULL || pll_settings == NULL 602 || pix_clk_params->requested_pix_clk_100hz == 0) { 603 DC_LOG_ERROR( 604 "%s: Invalid parameters!!\n", __func__); 605 return -1; 606 } 607 608 memset(pll_settings, 0, sizeof(*pll_settings)); 609 610 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 611 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 612 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 613 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 614 pll_settings->actual_pix_clk_100hz = 615 pix_clk_params->requested_pix_clk_100hz; 616 return -1; 617 } 618 619 dce112_get_pix_clk_dividers_helper(clk_src, 620 pll_settings, pix_clk_params); 621 622 return 0; 623 } 624 625 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src) 626 { 627 enum bp_result result; 628 struct bp_spread_spectrum_parameters bp_ss_params = {0}; 629 630 bp_ss_params.pll_id = clk_src->base.id; 631 632 /*Call ASICControl to process ATOMBIOS Exec table*/ 633 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll( 634 clk_src->bios, 635 &bp_ss_params, 636 false); 637 638 return result == BP_RESULT_OK; 639 } 640 641 static bool calculate_ss( 642 const struct pll_settings *pll_settings, 643 const struct spread_spectrum_data *ss_data, 644 struct delta_sigma_data *ds_data) 645 { 646 struct fixed31_32 fb_div; 647 struct fixed31_32 ss_amount; 648 struct fixed31_32 ss_nslip_amount; 649 struct fixed31_32 ss_ds_frac_amount; 650 struct fixed31_32 ss_step_size; 651 struct fixed31_32 modulation_time; 652 653 if (ds_data == NULL) 654 return false; 655 if (ss_data == NULL) 656 return false; 657 if (ss_data->percentage == 0) 658 return false; 659 if (pll_settings == NULL) 660 return false; 661 662 memset(ds_data, 0, sizeof(struct delta_sigma_data)); 663 664 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/ 665 /* 6 decimal point support in fractional feedback divider */ 666 fb_div = dc_fixpt_from_fraction( 667 pll_settings->fract_feedback_divider, 1000000); 668 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); 669 670 ds_data->ds_frac_amount = 0; 671 /*spreadSpectrumPercentage is in the unit of .01%, 672 * so have to divided by 100 * 100*/ 673 ss_amount = dc_fixpt_mul( 674 fb_div, dc_fixpt_from_fraction(ss_data->percentage, 675 100 * ss_data->percentage_divider)); 676 ds_data->feedback_amount = dc_fixpt_floor(ss_amount); 677 678 ss_nslip_amount = dc_fixpt_sub(ss_amount, 679 dc_fixpt_from_int(ds_data->feedback_amount)); 680 ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10); 681 ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount); 682 683 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount, 684 dc_fixpt_from_int(ds_data->nfrac_amount)); 685 ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536); 686 ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount); 687 688 /* compute SS_STEP_SIZE_DSFRAC */ 689 modulation_time = dc_fixpt_from_fraction( 690 pll_settings->reference_freq * 1000, 691 pll_settings->reference_divider * ss_data->modulation_freq_hz); 692 693 if (ss_data->flags.CENTER_SPREAD) 694 modulation_time = dc_fixpt_div_int(modulation_time, 4); 695 else 696 modulation_time = dc_fixpt_div_int(modulation_time, 2); 697 698 ss_step_size = dc_fixpt_div(ss_amount, modulation_time); 699 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/ 700 ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10); 701 ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size); 702 703 return true; 704 } 705 706 static bool enable_spread_spectrum( 707 struct dce110_clk_src *clk_src, 708 enum signal_type signal, struct pll_settings *pll_settings) 709 { 710 struct bp_spread_spectrum_parameters bp_params = {0}; 711 struct delta_sigma_data d_s_data; 712 const struct spread_spectrum_data *ss_data = NULL; 713 714 ss_data = get_ss_data_entry( 715 clk_src, 716 signal, 717 pll_settings->calculated_pix_clk_100hz / 10); 718 719 /* Pixel clock PLL has been programmed to generate desired pixel clock, 720 * now enable SS on pixel clock */ 721 /* TODO is it OK to return true not doing anything ??*/ 722 if (ss_data != NULL && pll_settings->ss_percentage != 0) { 723 if (calculate_ss(pll_settings, ss_data, &d_s_data)) { 724 bp_params.ds.feedback_amount = 725 d_s_data.feedback_amount; 726 bp_params.ds.nfrac_amount = 727 d_s_data.nfrac_amount; 728 bp_params.ds.ds_frac_size = d_s_data.ds_frac_size; 729 bp_params.ds_frac_amount = 730 d_s_data.ds_frac_amount; 731 bp_params.flags.DS_TYPE = 1; 732 bp_params.pll_id = clk_src->base.id; 733 bp_params.percentage = ss_data->percentage; 734 if (ss_data->flags.CENTER_SPREAD) 735 bp_params.flags.CENTER_SPREAD = 1; 736 if (ss_data->flags.EXTERNAL_SS) 737 bp_params.flags.EXTERNAL_SS = 1; 738 739 if (BP_RESULT_OK != 740 clk_src->bios->funcs-> 741 enable_spread_spectrum_on_ppll( 742 clk_src->bios, 743 &bp_params, 744 true)) 745 return false; 746 } else 747 return false; 748 } 749 return true; 750 } 751 752 static void dce110_program_pixel_clk_resync( 753 struct dce110_clk_src *clk_src, 754 enum signal_type signal_type, 755 enum dc_color_depth colordepth) 756 { 757 REG_UPDATE(RESYNC_CNTL, 758 DCCG_DEEP_COLOR_CNTL1, 0); 759 /* 760 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 761 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 762 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 763 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 764 */ 765 if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A) 766 return; 767 768 switch (colordepth) { 769 case COLOR_DEPTH_888: 770 REG_UPDATE(RESYNC_CNTL, 771 DCCG_DEEP_COLOR_CNTL1, 0); 772 break; 773 case COLOR_DEPTH_101010: 774 REG_UPDATE(RESYNC_CNTL, 775 DCCG_DEEP_COLOR_CNTL1, 1); 776 break; 777 case COLOR_DEPTH_121212: 778 REG_UPDATE(RESYNC_CNTL, 779 DCCG_DEEP_COLOR_CNTL1, 2); 780 break; 781 case COLOR_DEPTH_161616: 782 REG_UPDATE(RESYNC_CNTL, 783 DCCG_DEEP_COLOR_CNTL1, 3); 784 break; 785 default: 786 break; 787 } 788 } 789 790 static void dce112_program_pixel_clk_resync( 791 struct dce110_clk_src *clk_src, 792 enum signal_type signal_type, 793 enum dc_color_depth colordepth, 794 bool enable_ycbcr420) 795 { 796 uint32_t deep_color_cntl = 0; 797 uint32_t double_rate_enable = 0; 798 799 /* 800 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 801 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 802 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 803 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 804 */ 805 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 806 double_rate_enable = enable_ycbcr420 ? 1 : 0; 807 808 switch (colordepth) { 809 case COLOR_DEPTH_888: 810 deep_color_cntl = 0; 811 break; 812 case COLOR_DEPTH_101010: 813 deep_color_cntl = 1; 814 break; 815 case COLOR_DEPTH_121212: 816 deep_color_cntl = 2; 817 break; 818 case COLOR_DEPTH_161616: 819 deep_color_cntl = 3; 820 break; 821 default: 822 break; 823 } 824 } 825 826 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) 827 REG_UPDATE_2(PIXCLK_RESYNC_CNTL, 828 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl, 829 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable); 830 else 831 REG_UPDATE(PIXCLK_RESYNC_CNTL, 832 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl); 833 834 } 835 836 static bool dce110_program_pix_clk( 837 struct clock_source *clock_source, 838 struct pixel_clk_params *pix_clk_params, 839 struct pll_settings *pll_settings) 840 { 841 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 842 struct bp_pixel_clock_parameters bp_pc_params = {0}; 843 844 /* First disable SS 845 * ATOMBIOS will enable by default SS on PLL for DP, 846 * do not disable it here 847 */ 848 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 849 !dc_is_dp_signal(pix_clk_params->signal_type) && 850 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 851 disable_spread_spectrum(clk_src); 852 853 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 854 bp_pc_params.controller_id = pix_clk_params->controller_id; 855 bp_pc_params.pll_id = clock_source->id; 856 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 857 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 858 bp_pc_params.signal_type = pix_clk_params->signal_type; 859 860 bp_pc_params.reference_divider = pll_settings->reference_divider; 861 bp_pc_params.feedback_divider = pll_settings->feedback_divider; 862 bp_pc_params.fractional_feedback_divider = 863 pll_settings->fract_feedback_divider; 864 bp_pc_params.pixel_clock_post_divider = 865 pll_settings->pix_clk_post_divider; 866 bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC = 867 pll_settings->use_external_clk; 868 869 if (clk_src->bios->funcs->set_pixel_clock( 870 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 871 return false; 872 /* Enable SS 873 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock), 874 * based on HW display PLL team, SS control settings should be programmed 875 * during PLL Reset, but they do not have effect 876 * until SS_EN is asserted.*/ 877 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL 878 && !dc_is_dp_signal(pix_clk_params->signal_type)) { 879 880 if (pix_clk_params->flags.ENABLE_SS) 881 if (!enable_spread_spectrum(clk_src, 882 pix_clk_params->signal_type, 883 pll_settings)) 884 return false; 885 886 /* Resync deep color DTO */ 887 dce110_program_pixel_clk_resync(clk_src, 888 pix_clk_params->signal_type, 889 pix_clk_params->color_depth); 890 } 891 892 return true; 893 } 894 895 static bool dce112_program_pix_clk( 896 struct clock_source *clock_source, 897 struct pixel_clk_params *pix_clk_params, 898 struct pll_settings *pll_settings) 899 { 900 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 901 struct bp_pixel_clock_parameters bp_pc_params = {0}; 902 903 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 904 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { 905 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 906 unsigned dp_dto_ref_100hz = 7000000; 907 unsigned clock_100hz = pll_settings->actual_pix_clk_100hz; 908 909 /* Set DTO values: phase = target clock, modulo = reference clock */ 910 REG_WRITE(PHASE[inst], clock_100hz); 911 REG_WRITE(MODULO[inst], dp_dto_ref_100hz); 912 913 /* Enable DTO */ 914 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 915 return true; 916 } 917 #endif 918 /* First disable SS 919 * ATOMBIOS will enable by default SS on PLL for DP, 920 * do not disable it here 921 */ 922 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 923 !dc_is_dp_signal(pix_clk_params->signal_type) && 924 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 925 disable_spread_spectrum(clk_src); 926 927 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 928 bp_pc_params.controller_id = pix_clk_params->controller_id; 929 bp_pc_params.pll_id = clock_source->id; 930 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 931 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 932 bp_pc_params.signal_type = pix_clk_params->signal_type; 933 934 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 935 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 936 pll_settings->use_external_clk; 937 bp_pc_params.flags.SET_XTALIN_REF_SRC = 938 !pll_settings->use_external_clk; 939 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 940 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 941 } 942 } 943 if (clk_src->bios->funcs->set_pixel_clock( 944 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 945 return false; 946 /* Resync deep color DTO */ 947 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 948 dce112_program_pixel_clk_resync(clk_src, 949 pix_clk_params->signal_type, 950 pix_clk_params->color_depth, 951 pix_clk_params->flags.SUPPORT_YCBCR420); 952 953 return true; 954 } 955 956 957 static bool dce110_clock_source_power_down( 958 struct clock_source *clk_src) 959 { 960 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src); 961 enum bp_result bp_result; 962 struct bp_pixel_clock_parameters bp_pixel_clock_params = {0}; 963 964 if (clk_src->dp_clk_src) 965 return true; 966 967 /* If Pixel Clock is 0 it means Power Down Pll*/ 968 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; 969 bp_pixel_clock_params.pll_id = clk_src->id; 970 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1; 971 972 /*Call ASICControl to process ATOMBIOS Exec table*/ 973 bp_result = dce110_clk_src->bios->funcs->set_pixel_clock( 974 dce110_clk_src->bios, 975 &bp_pixel_clock_params); 976 977 return bp_result == BP_RESULT_OK; 978 } 979 980 static bool get_pixel_clk_frequency_100hz( 981 const struct clock_source *clock_source, 982 unsigned int inst, 983 unsigned int *pixel_clk_khz) 984 { 985 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 986 unsigned int clock_hz = 0; 987 988 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) { 989 clock_hz = REG_READ(PHASE[inst]); 990 991 /* NOTE: There is agreement with VBIOS here that MODULO is 992 * programmed equal to DPREFCLK, in which case PHASE will be 993 * equivalent to pixel clock. 994 */ 995 *pixel_clk_khz = clock_hz / 100; 996 return true; 997 } 998 999 return false; 1000 } 1001 1002 /*****************************************/ 1003 /* Constructor */ 1004 /*****************************************/ 1005 1006 static const struct clock_source_funcs dce112_clk_src_funcs = { 1007 .cs_power_down = dce110_clock_source_power_down, 1008 .program_pix_clk = dce112_program_pix_clk, 1009 .get_pix_clk_dividers = dce112_get_pix_clk_dividers, 1010 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1011 }; 1012 static const struct clock_source_funcs dce110_clk_src_funcs = { 1013 .cs_power_down = dce110_clock_source_power_down, 1014 .program_pix_clk = dce110_program_pix_clk, 1015 .get_pix_clk_dividers = dce110_get_pix_clk_dividers, 1016 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1017 }; 1018 1019 1020 static void get_ss_info_from_atombios( 1021 struct dce110_clk_src *clk_src, 1022 enum as_signal_type as_signal, 1023 struct spread_spectrum_data *spread_spectrum_data[], 1024 uint32_t *ss_entries_num) 1025 { 1026 enum bp_result bp_result = BP_RESULT_FAILURE; 1027 struct spread_spectrum_info *ss_info; 1028 struct spread_spectrum_data *ss_data; 1029 struct spread_spectrum_info *ss_info_cur; 1030 struct spread_spectrum_data *ss_data_cur; 1031 uint32_t i; 1032 DC_LOGGER_INIT(); 1033 if (ss_entries_num == NULL) { 1034 DC_LOG_SYNC( 1035 "Invalid entry !!!\n"); 1036 return; 1037 } 1038 if (spread_spectrum_data == NULL) { 1039 DC_LOG_SYNC( 1040 "Invalid array pointer!!!\n"); 1041 return; 1042 } 1043 1044 spread_spectrum_data[0] = NULL; 1045 *ss_entries_num = 0; 1046 1047 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number( 1048 clk_src->bios, 1049 as_signal); 1050 1051 if (*ss_entries_num == 0) 1052 return; 1053 1054 ss_info = kcalloc(*ss_entries_num, 1055 sizeof(struct spread_spectrum_info), 1056 GFP_KERNEL); 1057 ss_info_cur = ss_info; 1058 if (ss_info == NULL) 1059 return; 1060 1061 ss_data = kcalloc(*ss_entries_num, 1062 sizeof(struct spread_spectrum_data), 1063 GFP_KERNEL); 1064 if (ss_data == NULL) 1065 goto out_free_info; 1066 1067 for (i = 0, ss_info_cur = ss_info; 1068 i < (*ss_entries_num); 1069 ++i, ++ss_info_cur) { 1070 1071 bp_result = clk_src->bios->funcs->get_spread_spectrum_info( 1072 clk_src->bios, 1073 as_signal, 1074 i, 1075 ss_info_cur); 1076 1077 if (bp_result != BP_RESULT_OK) 1078 goto out_free_data; 1079 } 1080 1081 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data; 1082 i < (*ss_entries_num); 1083 ++i, ++ss_info_cur, ++ss_data_cur) { 1084 1085 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) { 1086 DC_LOG_SYNC( 1087 "Invalid ATOMBIOS SS Table!!!\n"); 1088 goto out_free_data; 1089 } 1090 1091 /* for HDMI check SS percentage, 1092 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/ 1093 if (as_signal == AS_SIGNAL_TYPE_HDMI 1094 && ss_info_cur->spread_spectrum_percentage > 6){ 1095 /* invalid input, do nothing */ 1096 DC_LOG_SYNC( 1097 "Invalid SS percentage "); 1098 DC_LOG_SYNC( 1099 "for HDMI in ATOMBIOS info Table!!!\n"); 1100 continue; 1101 } 1102 if (ss_info_cur->spread_percentage_divider == 1000) { 1103 /* Keep previous precision from ATOMBIOS for these 1104 * in case new precision set by ATOMBIOS for these 1105 * (otherwise all code in DCE specific classes 1106 * for all previous ASICs would need 1107 * to be updated for SS calculations, 1108 * Audio SS compensation and DP DTO SS compensation 1109 * which assumes fixed SS percentage Divider = 100)*/ 1110 ss_info_cur->spread_spectrum_percentage /= 10; 1111 ss_info_cur->spread_percentage_divider = 100; 1112 } 1113 1114 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range; 1115 ss_data_cur->percentage = 1116 ss_info_cur->spread_spectrum_percentage; 1117 ss_data_cur->percentage_divider = 1118 ss_info_cur->spread_percentage_divider; 1119 ss_data_cur->modulation_freq_hz = 1120 ss_info_cur->spread_spectrum_range; 1121 1122 if (ss_info_cur->type.CENTER_MODE) 1123 ss_data_cur->flags.CENTER_SPREAD = 1; 1124 1125 if (ss_info_cur->type.EXTERNAL) 1126 ss_data_cur->flags.EXTERNAL_SS = 1; 1127 1128 } 1129 1130 *spread_spectrum_data = ss_data; 1131 kfree(ss_info); 1132 return; 1133 1134 out_free_data: 1135 kfree(ss_data); 1136 *ss_entries_num = 0; 1137 out_free_info: 1138 kfree(ss_info); 1139 } 1140 1141 static void ss_info_from_atombios_create( 1142 struct dce110_clk_src *clk_src) 1143 { 1144 get_ss_info_from_atombios( 1145 clk_src, 1146 AS_SIGNAL_TYPE_DISPLAY_PORT, 1147 &clk_src->dp_ss_params, 1148 &clk_src->dp_ss_params_cnt); 1149 get_ss_info_from_atombios( 1150 clk_src, 1151 AS_SIGNAL_TYPE_HDMI, 1152 &clk_src->hdmi_ss_params, 1153 &clk_src->hdmi_ss_params_cnt); 1154 get_ss_info_from_atombios( 1155 clk_src, 1156 AS_SIGNAL_TYPE_DVI, 1157 &clk_src->dvi_ss_params, 1158 &clk_src->dvi_ss_params_cnt); 1159 get_ss_info_from_atombios( 1160 clk_src, 1161 AS_SIGNAL_TYPE_LVDS, 1162 &clk_src->lvds_ss_params, 1163 &clk_src->lvds_ss_params_cnt); 1164 } 1165 1166 static bool calc_pll_max_vco_construct( 1167 struct calc_pll_clock_source *calc_pll_cs, 1168 struct calc_pll_clock_source_init_data *init_data) 1169 { 1170 uint32_t i; 1171 struct dc_firmware_info fw_info = { { 0 } }; 1172 if (calc_pll_cs == NULL || 1173 init_data == NULL || 1174 init_data->bp == NULL) 1175 return false; 1176 1177 if (init_data->bp->funcs->get_firmware_info( 1178 init_data->bp, 1179 &fw_info) != BP_RESULT_OK) 1180 return false; 1181 1182 calc_pll_cs->ctx = init_data->ctx; 1183 calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency; 1184 calc_pll_cs->min_vco_khz = 1185 fw_info.pll_info.min_output_pxl_clk_pll_frequency; 1186 calc_pll_cs->max_vco_khz = 1187 fw_info.pll_info.max_output_pxl_clk_pll_frequency; 1188 1189 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0) 1190 calc_pll_cs->max_pll_input_freq_khz = 1191 init_data->max_override_input_pxl_clk_pll_freq_khz; 1192 else 1193 calc_pll_cs->max_pll_input_freq_khz = 1194 fw_info.pll_info.max_input_pxl_clk_pll_frequency; 1195 1196 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0) 1197 calc_pll_cs->min_pll_input_freq_khz = 1198 init_data->min_override_input_pxl_clk_pll_freq_khz; 1199 else 1200 calc_pll_cs->min_pll_input_freq_khz = 1201 fw_info.pll_info.min_input_pxl_clk_pll_frequency; 1202 1203 calc_pll_cs->min_pix_clock_pll_post_divider = 1204 init_data->min_pix_clk_pll_post_divider; 1205 calc_pll_cs->max_pix_clock_pll_post_divider = 1206 init_data->max_pix_clk_pll_post_divider; 1207 calc_pll_cs->min_pll_ref_divider = 1208 init_data->min_pll_ref_divider; 1209 calc_pll_cs->max_pll_ref_divider = 1210 init_data->max_pll_ref_divider; 1211 1212 if (init_data->num_fract_fb_divider_decimal_point == 0 || 1213 init_data->num_fract_fb_divider_decimal_point_precision > 1214 init_data->num_fract_fb_divider_decimal_point) { 1215 DC_LOG_ERROR( 1216 "The dec point num or precision is incorrect!"); 1217 return false; 1218 } 1219 if (init_data->num_fract_fb_divider_decimal_point_precision == 0) { 1220 DC_LOG_ERROR( 1221 "Incorrect fract feedback divider precision num!"); 1222 return false; 1223 } 1224 1225 calc_pll_cs->fract_fb_divider_decimal_points_num = 1226 init_data->num_fract_fb_divider_decimal_point; 1227 calc_pll_cs->fract_fb_divider_precision = 1228 init_data->num_fract_fb_divider_decimal_point_precision; 1229 calc_pll_cs->fract_fb_divider_factor = 1; 1230 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i) 1231 calc_pll_cs->fract_fb_divider_factor *= 10; 1232 1233 calc_pll_cs->fract_fb_divider_precision_factor = 1; 1234 for ( 1235 i = 0; 1236 i < (calc_pll_cs->fract_fb_divider_decimal_points_num - 1237 calc_pll_cs->fract_fb_divider_precision); 1238 ++i) 1239 calc_pll_cs->fract_fb_divider_precision_factor *= 10; 1240 1241 return true; 1242 } 1243 1244 bool dce110_clk_src_construct( 1245 struct dce110_clk_src *clk_src, 1246 struct dc_context *ctx, 1247 struct dc_bios *bios, 1248 enum clock_source_id id, 1249 const struct dce110_clk_src_regs *regs, 1250 const struct dce110_clk_src_shift *cs_shift, 1251 const struct dce110_clk_src_mask *cs_mask) 1252 { 1253 struct dc_firmware_info fw_info = { { 0 } }; 1254 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi; 1255 struct calc_pll_clock_source_init_data calc_pll_cs_init_data; 1256 1257 clk_src->base.ctx = ctx; 1258 clk_src->bios = bios; 1259 clk_src->base.id = id; 1260 clk_src->base.funcs = &dce110_clk_src_funcs; 1261 1262 clk_src->regs = regs; 1263 clk_src->cs_shift = cs_shift; 1264 clk_src->cs_mask = cs_mask; 1265 1266 if (clk_src->bios->funcs->get_firmware_info( 1267 clk_src->bios, &fw_info) != BP_RESULT_OK) { 1268 ASSERT_CRITICAL(false); 1269 goto unexpected_failure; 1270 } 1271 1272 clk_src->ext_clk_khz = 1273 fw_info.external_clock_source_frequency_for_dp; 1274 1275 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */ 1276 calc_pll_cs_init_data.bp = bios; 1277 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1; 1278 calc_pll_cs_init_data.max_pix_clk_pll_post_divider = 1279 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1280 calc_pll_cs_init_data.min_pll_ref_divider = 1; 1281 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1282 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1283 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0; 1284 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1285 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0; 1286 /*numberOfFractFBDividerDecimalPoints*/ 1287 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point = 1288 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1289 /*number of decimal point to round off for fractional feedback divider value*/ 1290 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision = 1291 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1292 calc_pll_cs_init_data.ctx = ctx; 1293 1294 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */ 1295 calc_pll_cs_init_data_hdmi.bp = bios; 1296 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1; 1297 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider = 1298 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1299 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1; 1300 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1301 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1302 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500; 1303 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1304 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000; 1305 /*numberOfFractFBDividerDecimalPoints*/ 1306 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point = 1307 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1308 /*number of decimal point to round off for fractional feedback divider value*/ 1309 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision = 1310 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1311 calc_pll_cs_init_data_hdmi.ctx = ctx; 1312 1313 clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency; 1314 1315 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) 1316 return true; 1317 1318 /* PLL only from here on */ 1319 ss_info_from_atombios_create(clk_src); 1320 1321 if (!calc_pll_max_vco_construct( 1322 &clk_src->calc_pll, 1323 &calc_pll_cs_init_data)) { 1324 ASSERT_CRITICAL(false); 1325 goto unexpected_failure; 1326 } 1327 1328 1329 calc_pll_cs_init_data_hdmi. 1330 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2; 1331 calc_pll_cs_init_data_hdmi. 1332 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz; 1333 1334 1335 if (!calc_pll_max_vco_construct( 1336 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) { 1337 ASSERT_CRITICAL(false); 1338 goto unexpected_failure; 1339 } 1340 1341 return true; 1342 1343 unexpected_failure: 1344 return false; 1345 } 1346 1347 bool dce112_clk_src_construct( 1348 struct dce110_clk_src *clk_src, 1349 struct dc_context *ctx, 1350 struct dc_bios *bios, 1351 enum clock_source_id id, 1352 const struct dce110_clk_src_regs *regs, 1353 const struct dce110_clk_src_shift *cs_shift, 1354 const struct dce110_clk_src_mask *cs_mask) 1355 { 1356 struct dc_firmware_info fw_info = { { 0 } }; 1357 1358 clk_src->base.ctx = ctx; 1359 clk_src->bios = bios; 1360 clk_src->base.id = id; 1361 clk_src->base.funcs = &dce112_clk_src_funcs; 1362 1363 clk_src->regs = regs; 1364 clk_src->cs_shift = cs_shift; 1365 clk_src->cs_mask = cs_mask; 1366 1367 if (clk_src->bios->funcs->get_firmware_info( 1368 clk_src->bios, &fw_info) != BP_RESULT_OK) { 1369 ASSERT_CRITICAL(false); 1370 return false; 1371 } 1372 1373 clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp; 1374 1375 return true; 1376 } 1377 1378