1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_AUX_ENGINE_DCE110_H__ 27 #define __DAL_AUX_ENGINE_DCE110_H__ 28 29 #include "i2caux_interface.h" 30 #include "inc/hw/aux_engine.h" 31 32 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 33 #define AUX_COMMON_REG_LIST0(id)\ 34 SRI(AUX_CONTROL, DP_AUX, id), \ 35 SRI(AUX_ARB_CONTROL, DP_AUX, id), \ 36 SRI(AUX_SW_DATA, DP_AUX, id), \ 37 SRI(AUX_SW_CONTROL, DP_AUX, id), \ 38 SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ 39 SRI(AUX_SW_STATUS, DP_AUX, id) 40 #endif 41 42 #define AUX_COMMON_REG_LIST(id)\ 43 SRI(AUX_CONTROL, DP_AUX, id), \ 44 SRI(AUX_ARB_CONTROL, DP_AUX, id), \ 45 SRI(AUX_SW_DATA, DP_AUX, id), \ 46 SRI(AUX_SW_CONTROL, DP_AUX, id), \ 47 SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ 48 SRI(AUX_SW_STATUS, DP_AUX, id), \ 49 SR(AUXN_IMPCAL), \ 50 SR(AUXP_IMPCAL) 51 52 struct dce110_aux_registers { 53 uint32_t AUX_CONTROL; 54 uint32_t AUX_ARB_CONTROL; 55 uint32_t AUX_SW_DATA; 56 uint32_t AUX_SW_CONTROL; 57 uint32_t AUX_INTERRUPT_CONTROL; 58 uint32_t AUX_SW_STATUS; 59 uint32_t AUXN_IMPCAL; 60 uint32_t AUXP_IMPCAL; 61 62 uint32_t AUX_RESET_MASK; 63 }; 64 65 enum { /* This is the timeout as defined in DP 1.2a, 66 * 2.3.4 "Detailed uPacket TX AUX CH State Description". 67 */ 68 AUX_TIMEOUT_PERIOD = 400, 69 70 /* Ideally, the SW timeout should be just above 550usec 71 * which is programmed in HW. 72 * But the SW timeout of 600usec is not reliable, 73 * because on some systems, delay_in_microseconds() 74 * returns faster than it should. 75 * EPR #379763: by trial-and-error on different systems, 76 * 700usec is the minimum reliable SW timeout for polling 77 * the AUX_SW_STATUS.AUX_SW_DONE bit. 78 * This timeout expires *only* when there is 79 * AUX Error or AUX Timeout conditions - not during normal operation. 80 * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set 81 * at most within ~240usec. That means, 82 * increasing this timeout will not affect normal operation, 83 * and we'll timeout after 84 * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec. 85 * This timeout is especially important for 86 * converters, resume from S3, and CTS. 87 */ 88 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6 89 }; 90 91 struct dce_aux { 92 uint32_t inst; 93 struct ddc *ddc; 94 struct dc_context *ctx; 95 /* following values are expressed in milliseconds */ 96 uint32_t delay; 97 uint32_t max_defer_write_retry; 98 99 bool acquire_reset; 100 }; 101 102 struct aux_engine_dce110 { 103 struct dce_aux base; 104 const struct dce110_aux_registers *regs; 105 struct { 106 uint32_t aux_control; 107 uint32_t aux_arb_control; 108 uint32_t aux_sw_data; 109 uint32_t aux_sw_control; 110 uint32_t aux_interrupt_control; 111 uint32_t aux_sw_status; 112 } addr; 113 uint32_t timeout_period; 114 }; 115 116 struct aux_engine_dce110_init_data { 117 uint32_t engine_id; 118 uint32_t timeout_period; 119 struct dc_context *ctx; 120 const struct dce110_aux_registers *regs; 121 }; 122 123 struct dce_aux *dce110_aux_engine_construct( 124 struct aux_engine_dce110 *aux_engine110, 125 struct dc_context *ctx, 126 uint32_t inst, 127 uint32_t timeout_period, 128 const struct dce110_aux_registers *regs); 129 130 void dce110_engine_destroy(struct dce_aux **engine); 131 132 bool dce110_aux_engine_acquire( 133 struct dce_aux *aux_engine, 134 struct ddc *ddc); 135 136 int dce_aux_transfer_raw(struct ddc_service *ddc, 137 struct aux_payload *cmd, 138 enum aux_channel_operation_result *operation_result); 139 140 bool dce_aux_transfer_with_retries(struct ddc_service *ddc, 141 struct aux_payload *cmd); 142 #endif 143