1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "core_types.h" 31 #include "dce_aux.h" 32 #include "dce/dce_11_0_sh_mask.h" 33 #include "dm_event_log.h" 34 #include "dm_helpers.h" 35 #include "dmub/inc/dmub_cmd.h" 36 37 #define CTX \ 38 aux110->base.ctx 39 #define REG(reg_name)\ 40 (aux110->regs->reg_name) 41 42 #define DC_LOGGER \ 43 engine->ctx->logger 44 45 #include "reg_helper.h" 46 47 #undef FN 48 #define FN(reg_name, field_name) \ 49 aux110->shift->field_name, aux110->mask->field_name 50 51 #define FROM_AUX_ENGINE(ptr) \ 52 container_of((ptr), struct aux_engine_dce110, base) 53 54 #define FROM_ENGINE(ptr) \ 55 FROM_AUX_ENGINE(container_of((ptr), struct dce_aux, base)) 56 57 #define FROM_AUX_ENGINE_ENGINE(ptr) \ 58 container_of((ptr), struct dce_aux, base) 59 enum { 60 AUX_INVALID_REPLY_RETRY_COUNTER = 1, 61 AUX_TIMED_OUT_RETRY_COUNTER = 2, 62 AUX_DEFER_RETRY_COUNTER = 6 63 }; 64 65 #define TIME_OUT_INCREMENT 1016 66 #define TIME_OUT_MULTIPLIER_8 8 67 #define TIME_OUT_MULTIPLIER_16 16 68 #define TIME_OUT_MULTIPLIER_32 32 69 #define TIME_OUT_MULTIPLIER_64 64 70 #define MAX_TIMEOUT_LENGTH 127 71 #define DEFAULT_AUX_ENGINE_MULT 0 72 #define DEFAULT_AUX_ENGINE_LENGTH 69 73 74 static void release_engine( 75 struct dce_aux *engine) 76 { 77 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 78 79 dal_ddc_close(engine->ddc); 80 81 engine->ddc = NULL; 82 83 REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1); 84 } 85 86 #define SW_CAN_ACCESS_AUX 1 87 #define DMCU_CAN_ACCESS_AUX 2 88 89 static bool is_engine_available( 90 struct dce_aux *engine) 91 { 92 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 93 94 uint32_t value = REG_READ(AUX_ARB_CONTROL); 95 uint32_t field = get_reg_field_value( 96 value, 97 AUX_ARB_CONTROL, 98 AUX_REG_RW_CNTL_STATUS); 99 100 return (field != DMCU_CAN_ACCESS_AUX); 101 } 102 static bool acquire_engine( 103 struct dce_aux *engine) 104 { 105 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 106 107 uint32_t value = REG_READ(AUX_ARB_CONTROL); 108 uint32_t field = get_reg_field_value( 109 value, 110 AUX_ARB_CONTROL, 111 AUX_REG_RW_CNTL_STATUS); 112 if (field == DMCU_CAN_ACCESS_AUX) 113 return false; 114 /* enable AUX before request SW to access AUX */ 115 value = REG_READ(AUX_CONTROL); 116 field = get_reg_field_value(value, 117 AUX_CONTROL, 118 AUX_EN); 119 120 if (field == 0) { 121 set_reg_field_value( 122 value, 123 1, 124 AUX_CONTROL, 125 AUX_EN); 126 127 if (REG(AUX_RESET_MASK)) { 128 /*DP_AUX block as part of the enable sequence*/ 129 set_reg_field_value( 130 value, 131 1, 132 AUX_CONTROL, 133 AUX_RESET); 134 } 135 136 REG_WRITE(AUX_CONTROL, value); 137 138 if (REG(AUX_RESET_MASK)) { 139 /*poll HW to make sure reset it done*/ 140 141 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, 142 1, 11); 143 144 set_reg_field_value( 145 value, 146 0, 147 AUX_CONTROL, 148 AUX_RESET); 149 150 REG_WRITE(AUX_CONTROL, value); 151 152 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, 153 1, 11); 154 } 155 } /*if (field)*/ 156 157 /* request SW to access AUX */ 158 REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1); 159 160 value = REG_READ(AUX_ARB_CONTROL); 161 field = get_reg_field_value( 162 value, 163 AUX_ARB_CONTROL, 164 AUX_REG_RW_CNTL_STATUS); 165 166 return (field == SW_CAN_ACCESS_AUX); 167 } 168 169 #define COMPOSE_AUX_SW_DATA_16_20(command, address) \ 170 ((command) | ((0xF0000 & (address)) >> 16)) 171 172 #define COMPOSE_AUX_SW_DATA_8_15(address) \ 173 ((0xFF00 & (address)) >> 8) 174 175 #define COMPOSE_AUX_SW_DATA_0_7(address) \ 176 (0xFF & (address)) 177 178 static void submit_channel_request( 179 struct dce_aux *engine, 180 struct aux_request_transaction_data *request) 181 { 182 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 183 uint32_t value; 184 uint32_t length; 185 186 bool is_write = 187 ((request->type == AUX_TRANSACTION_TYPE_DP) && 188 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) || 189 ((request->type == AUX_TRANSACTION_TYPE_I2C) && 190 ((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) || 191 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT))); 192 if (REG(AUXN_IMPCAL)) { 193 /* clear_aux_error */ 194 REG_UPDATE_SEQ_2(AUXN_IMPCAL, 195 AUXN_CALOUT_ERROR_AK, 1, 196 AUXN_CALOUT_ERROR_AK, 0); 197 198 REG_UPDATE_SEQ_2(AUXP_IMPCAL, 199 AUXP_CALOUT_ERROR_AK, 1, 200 AUXP_CALOUT_ERROR_AK, 0); 201 202 /* force_default_calibrate */ 203 REG_UPDATE_SEQ_2(AUXN_IMPCAL, 204 AUXN_IMPCAL_ENABLE, 1, 205 AUXN_IMPCAL_OVERRIDE_ENABLE, 0); 206 207 /* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */ 208 209 REG_UPDATE_SEQ_2(AUXP_IMPCAL, 210 AUXP_IMPCAL_OVERRIDE_ENABLE, 1, 211 AUXP_IMPCAL_OVERRIDE_ENABLE, 0); 212 } 213 214 REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1); 215 216 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, 217 10, aux110->polling_timeout_period/10); 218 219 /* set the delay and the number of bytes to write */ 220 221 /* The length include 222 * the 4 bit header and the 20 bit address 223 * (that is 3 byte). 224 * If the requested length is non zero this means 225 * an addition byte specifying the length is required. 226 */ 227 228 length = request->length ? 4 : 3; 229 if (is_write) 230 length += request->length; 231 232 REG_UPDATE_2(AUX_SW_CONTROL, 233 AUX_SW_START_DELAY, request->delay, 234 AUX_SW_WR_BYTES, length); 235 236 /* program action and address and payload data (if 'is_write') */ 237 value = REG_UPDATE_4(AUX_SW_DATA, 238 AUX_SW_INDEX, 0, 239 AUX_SW_DATA_RW, 0, 240 AUX_SW_AUTOINCREMENT_DISABLE, 1, 241 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address)); 242 243 value = REG_SET_2(AUX_SW_DATA, value, 244 AUX_SW_AUTOINCREMENT_DISABLE, 0, 245 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address)); 246 247 value = REG_SET(AUX_SW_DATA, value, 248 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address)); 249 250 if (request->length) { 251 value = REG_SET(AUX_SW_DATA, value, 252 AUX_SW_DATA, request->length - 1); 253 } 254 255 if (is_write) { 256 /* Load the HW buffer with the Data to be sent. 257 * This is relevant for write operation. 258 * For read, the data recived data will be 259 * processed in process_channel_reply(). 260 */ 261 uint32_t i = 0; 262 263 while (i < request->length) { 264 value = REG_SET(AUX_SW_DATA, value, 265 AUX_SW_DATA, request->data[i]); 266 267 ++i; 268 } 269 } 270 271 REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1); 272 EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE, 273 request->action, request->address, request->length, request->data); 274 } 275 276 static int read_channel_reply(struct dce_aux *engine, uint32_t size, 277 uint8_t *buffer, uint8_t *reply_result, 278 uint32_t *sw_status) 279 { 280 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 281 uint32_t bytes_replied; 282 uint32_t reply_result_32; 283 284 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, 285 &bytes_replied); 286 287 /* In case HPD is LOW, exit AUX transaction */ 288 if ((*sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) 289 return -1; 290 291 /* Need at least the status byte */ 292 if (!bytes_replied) 293 return -1; 294 295 REG_UPDATE_SEQ_3(AUX_SW_DATA, 296 AUX_SW_INDEX, 0, 297 AUX_SW_AUTOINCREMENT_DISABLE, 1, 298 AUX_SW_DATA_RW, 1); 299 300 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); 301 reply_result_32 = reply_result_32 >> 4; 302 if (reply_result != NULL) 303 *reply_result = (uint8_t)reply_result_32; 304 305 if (reply_result_32 == 0) { /* ACK */ 306 uint32_t i = 0; 307 308 /* First byte was already used to get the command status */ 309 --bytes_replied; 310 311 /* Do not overflow buffer */ 312 if (bytes_replied > size) 313 return -1; 314 315 while (i < bytes_replied) { 316 uint32_t aux_sw_data_val; 317 318 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); 319 buffer[i] = aux_sw_data_val; 320 ++i; 321 } 322 323 return i; 324 } 325 326 return 0; 327 } 328 329 static enum aux_return_code_type get_channel_status( 330 struct dce_aux *engine, 331 uint8_t *returned_bytes) 332 { 333 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 334 335 uint32_t value; 336 337 if (returned_bytes == NULL) { 338 /*caller pass NULL pointer*/ 339 ASSERT_CRITICAL(false); 340 return AUX_RET_ERROR_UNKNOWN; 341 } 342 *returned_bytes = 0; 343 344 /* poll to make sure that SW_DONE is asserted */ 345 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, 346 10, aux110->polling_timeout_period/10); 347 348 value = REG_READ(AUX_SW_STATUS); 349 /* in case HPD is LOW, exit AUX transaction */ 350 if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) 351 return AUX_RET_ERROR_HPD_DISCON; 352 353 /* Note that the following bits are set in 'status.bits' 354 * during CTS 4.2.1.2 (FW 3.3.1): 355 * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP, 356 * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H. 357 * 358 * AUX_SW_RX_MIN_COUNT_VIOL is an internal, 359 * HW debugging bit and should be ignored. 360 */ 361 if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) { 362 if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) || 363 (value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK)) 364 return AUX_RET_ERROR_TIMEOUT; 365 366 else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) || 367 (value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) || 368 (value & 369 AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) || 370 (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK)) 371 return AUX_RET_ERROR_INVALID_REPLY; 372 373 *returned_bytes = get_reg_field_value(value, 374 AUX_SW_STATUS, 375 AUX_SW_REPLY_BYTE_COUNT); 376 377 if (*returned_bytes == 0) 378 return 379 AUX_RET_ERROR_INVALID_REPLY; 380 else { 381 *returned_bytes -= 1; 382 return AUX_RET_SUCCESS; 383 } 384 } else { 385 /*time_elapsed >= aux_engine->timeout_period 386 * AUX_SW_STATUS__AUX_SW_HPD_DISCON = at this point 387 */ 388 ASSERT_CRITICAL(false); 389 return AUX_RET_ERROR_TIMEOUT; 390 } 391 } 392 393 static bool acquire( 394 struct dce_aux *engine, 395 struct ddc *ddc) 396 { 397 enum gpio_result result; 398 399 if ((engine == NULL) || !is_engine_available(engine)) 400 return false; 401 402 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, 403 GPIO_DDC_CONFIG_TYPE_MODE_AUX); 404 405 if (result != GPIO_RESULT_OK) 406 return false; 407 408 if (!acquire_engine(engine)) { 409 dal_ddc_close(ddc); 410 return false; 411 } 412 413 engine->ddc = ddc; 414 415 return true; 416 } 417 418 void dce110_engine_destroy(struct dce_aux **engine) 419 { 420 421 struct aux_engine_dce110 *engine110 = FROM_AUX_ENGINE(*engine); 422 423 kfree(engine110); 424 *engine = NULL; 425 426 } 427 428 static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc, 429 uint32_t timeout_in_us) 430 { 431 uint32_t multiplier = 0; 432 uint32_t length = 0; 433 uint32_t prev_length = 0; 434 uint32_t prev_mult = 0; 435 uint32_t prev_timeout_val = 0; 436 struct ddc *ddc_pin = ddc->ddc_pin; 437 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 438 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine); 439 440 /* 1-Update polling timeout period */ 441 aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER; 442 443 /* 2-Update aux timeout period length and multiplier */ 444 if (timeout_in_us == 0) { 445 multiplier = DEFAULT_AUX_ENGINE_MULT; 446 length = DEFAULT_AUX_ENGINE_LENGTH; 447 } else if (timeout_in_us <= TIME_OUT_INCREMENT) { 448 multiplier = 0; 449 length = timeout_in_us/TIME_OUT_MULTIPLIER_8; 450 if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0) 451 length++; 452 } else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) { 453 multiplier = 1; 454 length = timeout_in_us/TIME_OUT_MULTIPLIER_16; 455 if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0) 456 length++; 457 } else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) { 458 multiplier = 2; 459 length = timeout_in_us/TIME_OUT_MULTIPLIER_32; 460 if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0) 461 length++; 462 } else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) { 463 multiplier = 3; 464 length = timeout_in_us/TIME_OUT_MULTIPLIER_64; 465 if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0) 466 length++; 467 } 468 469 length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH; 470 471 REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult); 472 473 switch (prev_mult) { 474 case 0: 475 prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_8; 476 break; 477 case 1: 478 prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_16; 479 break; 480 case 2: 481 prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_32; 482 break; 483 case 3: 484 prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_64; 485 break; 486 default: 487 prev_timeout_val = DEFAULT_AUX_ENGINE_LENGTH * TIME_OUT_MULTIPLIER_8; 488 break; 489 } 490 491 REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier); 492 493 return prev_timeout_val; 494 } 495 496 static struct dce_aux_funcs aux_functions = { 497 .configure_timeout = NULL, 498 .destroy = NULL, 499 }; 500 501 struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110, 502 struct dc_context *ctx, 503 uint32_t inst, 504 uint32_t timeout_period, 505 const struct dce110_aux_registers *regs, 506 const struct dce110_aux_registers_mask *mask, 507 const struct dce110_aux_registers_shift *shift, 508 bool is_ext_aux_timeout_configurable) 509 { 510 aux_engine110->base.ddc = NULL; 511 aux_engine110->base.ctx = ctx; 512 aux_engine110->base.delay = 0; 513 aux_engine110->base.max_defer_write_retry = 0; 514 aux_engine110->base.inst = inst; 515 aux_engine110->polling_timeout_period = timeout_period; 516 aux_engine110->regs = regs; 517 518 aux_engine110->mask = mask; 519 aux_engine110->shift = shift; 520 aux_engine110->base.funcs = &aux_functions; 521 if (is_ext_aux_timeout_configurable) 522 aux_engine110->base.funcs->configure_timeout = &dce_aux_configure_timeout; 523 524 return &aux_engine110->base; 525 } 526 527 static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payload *payload) 528 { 529 if (payload->i2c_over_aux) { 530 if (payload->write) { 531 if (payload->mot) 532 return I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT; 533 return I2CAUX_TRANSACTION_ACTION_I2C_WRITE; 534 } 535 if (payload->mot) 536 return I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT; 537 return I2CAUX_TRANSACTION_ACTION_I2C_READ; 538 } 539 if (payload->write) 540 return I2CAUX_TRANSACTION_ACTION_DP_WRITE; 541 return I2CAUX_TRANSACTION_ACTION_DP_READ; 542 } 543 544 int dce_aux_transfer_raw(struct ddc_service *ddc, 545 struct aux_payload *payload, 546 enum aux_return_code_type *operation_result) 547 { 548 struct ddc *ddc_pin = ddc->ddc_pin; 549 struct dce_aux *aux_engine; 550 struct aux_request_transaction_data aux_req; 551 struct aux_reply_transaction_data aux_rep; 552 uint8_t returned_bytes = 0; 553 int res = -1; 554 uint32_t status; 555 556 memset(&aux_req, 0, sizeof(aux_req)); 557 memset(&aux_rep, 0, sizeof(aux_rep)); 558 559 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 560 if (!acquire(aux_engine, ddc_pin)) { 561 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 562 return -1; 563 } 564 565 if (payload->i2c_over_aux) 566 aux_req.type = AUX_TRANSACTION_TYPE_I2C; 567 else 568 aux_req.type = AUX_TRANSACTION_TYPE_DP; 569 570 aux_req.action = i2caux_action_from_payload(payload); 571 572 aux_req.address = payload->address; 573 aux_req.delay = 0; 574 aux_req.length = payload->length; 575 aux_req.data = payload->data; 576 577 submit_channel_request(aux_engine, &aux_req); 578 *operation_result = get_channel_status(aux_engine, &returned_bytes); 579 580 if (*operation_result == AUX_RET_SUCCESS) { 581 int __maybe_unused bytes_replied = 0; 582 583 bytes_replied = read_channel_reply(aux_engine, payload->length, 584 payload->data, payload->reply, 585 &status); 586 EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en, 587 EVENT_LOG_AUX_ORIGIN_NATIVE, *payload->reply, 588 bytes_replied, payload->data); 589 res = returned_bytes; 590 } else { 591 res = -1; 592 } 593 594 release_engine(aux_engine); 595 return res; 596 } 597 598 int dce_aux_transfer_dmub_raw(struct ddc_service *ddc, 599 struct aux_payload *payload, 600 enum aux_return_code_type *operation_result) 601 { 602 struct ddc *ddc_pin = ddc->ddc_pin; 603 604 if (ddc_pin != NULL) { 605 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 606 /* XXX: Workaround to configure ddc channels for aux transactions */ 607 if (!acquire(aux_engine, ddc_pin)) { 608 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 609 return -1; 610 } 611 release_engine(aux_engine); 612 } 613 614 return dm_helper_dmub_aux_transfer_sync(ddc->ctx, ddc->link, payload, operation_result); 615 } 616 617 #define AUX_MAX_RETRIES 7 618 #define AUX_MIN_DEFER_RETRIES 7 619 #define AUX_MAX_DEFER_TIMEOUT_MS 50 620 #define AUX_MAX_I2C_DEFER_RETRIES 7 621 #define AUX_MAX_INVALID_REPLY_RETRIES 2 622 #define AUX_MAX_TIMEOUT_RETRIES 3 623 624 bool dce_aux_transfer_with_retries(struct ddc_service *ddc, 625 struct aux_payload *payload) 626 { 627 int i, ret = 0; 628 uint8_t reply; 629 bool payload_reply = true; 630 enum aux_return_code_type operation_result; 631 bool retry_on_defer = false; 632 struct ddc *ddc_pin = ddc->ddc_pin; 633 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 634 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine); 635 uint32_t defer_time_in_ms = 0; 636 637 int aux_ack_retries = 0, 638 aux_defer_retries = 0, 639 aux_i2c_defer_retries = 0, 640 aux_timeout_retries = 0, 641 aux_invalid_reply_retries = 0; 642 643 if (!payload->reply) { 644 payload_reply = false; 645 payload->reply = &reply; 646 } 647 648 for (i = 0; i < AUX_MAX_RETRIES; i++) { 649 ret = dce_aux_transfer_raw(ddc, payload, &operation_result); 650 651 switch (operation_result) { 652 case AUX_RET_SUCCESS: 653 aux_timeout_retries = 0; 654 aux_invalid_reply_retries = 0; 655 656 switch (*payload->reply) { 657 case AUX_TRANSACTION_REPLY_AUX_ACK: 658 if (!payload->write && payload->length != ret) { 659 if (++aux_ack_retries >= AUX_MAX_RETRIES) 660 goto fail; 661 else 662 udelay(300); 663 } else 664 return true; 665 break; 666 667 case AUX_TRANSACTION_REPLY_AUX_DEFER: 668 /* polling_timeout_period is in us */ 669 defer_time_in_ms += aux110->polling_timeout_period / 1000; 670 ++aux_defer_retries; 671 fallthrough; 672 case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER: 673 retry_on_defer = true; 674 fallthrough; 675 case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK: 676 if (aux_defer_retries >= AUX_MIN_DEFER_RETRIES 677 && defer_time_in_ms >= AUX_MAX_DEFER_TIMEOUT_MS) { 678 goto fail; 679 } else { 680 if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) || 681 (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) { 682 if (payload->defer_delay > 1) { 683 msleep(payload->defer_delay); 684 defer_time_in_ms += payload->defer_delay; 685 } else if (payload->defer_delay <= 1) { 686 udelay(payload->defer_delay * 1000); 687 defer_time_in_ms += payload->defer_delay; 688 } 689 } 690 } 691 break; 692 693 case AUX_TRANSACTION_REPLY_I2C_DEFER: 694 aux_defer_retries = 0; 695 if (++aux_i2c_defer_retries >= AUX_MAX_I2C_DEFER_RETRIES) 696 goto fail; 697 break; 698 699 case AUX_TRANSACTION_REPLY_AUX_NACK: 700 case AUX_TRANSACTION_REPLY_HPD_DISCON: 701 default: 702 goto fail; 703 } 704 break; 705 706 case AUX_RET_ERROR_INVALID_REPLY: 707 if (++aux_invalid_reply_retries >= AUX_MAX_INVALID_REPLY_RETRIES) 708 goto fail; 709 else 710 udelay(400); 711 break; 712 713 case AUX_RET_ERROR_TIMEOUT: 714 // Check whether a DEFER had occurred before the timeout. 715 // If so, treat timeout as a DEFER. 716 if (retry_on_defer) { 717 if (++aux_defer_retries >= AUX_MIN_DEFER_RETRIES) 718 goto fail; 719 else if (payload->defer_delay > 0) 720 msleep(payload->defer_delay); 721 } else { 722 if (++aux_timeout_retries >= AUX_MAX_TIMEOUT_RETRIES) 723 goto fail; 724 else { 725 /* 726 * DP 1.4, 2.8.2: AUX Transaction Response/Reply Timeouts 727 * According to the DP spec there should be 3 retries total 728 * with a 400us wait inbetween each. Hardware already waits 729 * for 550us therefore no wait is required here. 730 */ 731 } 732 } 733 break; 734 735 case AUX_RET_ERROR_HPD_DISCON: 736 case AUX_RET_ERROR_ENGINE_ACQUIRE: 737 case AUX_RET_ERROR_UNKNOWN: 738 default: 739 goto fail; 740 } 741 } 742 743 fail: 744 if (!payload_reply) 745 payload->reply = NULL; 746 return false; 747 } 748