1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "core_types.h" 31 #include "dce_aux.h" 32 #include "dce/dce_11_0_sh_mask.h" 33 #include "dm_event_log.h" 34 35 #define CTX \ 36 aux110->base.ctx 37 #define REG(reg_name)\ 38 (aux110->regs->reg_name) 39 40 #define DC_LOGGER \ 41 engine->ctx->logger 42 43 #include "reg_helper.h" 44 45 #undef FN 46 #define FN(reg_name, field_name) \ 47 aux110->shift->field_name, aux110->mask->field_name 48 49 #define FROM_AUX_ENGINE(ptr) \ 50 container_of((ptr), struct aux_engine_dce110, base) 51 52 #define FROM_ENGINE(ptr) \ 53 FROM_AUX_ENGINE(container_of((ptr), struct dce_aux, base)) 54 55 #define FROM_AUX_ENGINE_ENGINE(ptr) \ 56 container_of((ptr), struct dce_aux, base) 57 enum { 58 AUX_INVALID_REPLY_RETRY_COUNTER = 1, 59 AUX_TIMED_OUT_RETRY_COUNTER = 2, 60 AUX_DEFER_RETRY_COUNTER = 6 61 }; 62 63 #define TIME_OUT_INCREMENT 1016 64 #define TIME_OUT_MULTIPLIER_8 8 65 #define TIME_OUT_MULTIPLIER_16 16 66 #define TIME_OUT_MULTIPLIER_32 32 67 #define TIME_OUT_MULTIPLIER_64 64 68 #define MAX_TIMEOUT_LENGTH 127 69 70 static void release_engine( 71 struct dce_aux *engine) 72 { 73 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 74 75 dal_ddc_close(engine->ddc); 76 77 engine->ddc = NULL; 78 79 REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1); 80 } 81 82 #define SW_CAN_ACCESS_AUX 1 83 #define DMCU_CAN_ACCESS_AUX 2 84 85 static bool is_engine_available( 86 struct dce_aux *engine) 87 { 88 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 89 90 uint32_t value = REG_READ(AUX_ARB_CONTROL); 91 uint32_t field = get_reg_field_value( 92 value, 93 AUX_ARB_CONTROL, 94 AUX_REG_RW_CNTL_STATUS); 95 96 return (field != DMCU_CAN_ACCESS_AUX); 97 } 98 static bool acquire_engine( 99 struct dce_aux *engine) 100 { 101 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 102 103 uint32_t value = REG_READ(AUX_ARB_CONTROL); 104 uint32_t field = get_reg_field_value( 105 value, 106 AUX_ARB_CONTROL, 107 AUX_REG_RW_CNTL_STATUS); 108 if (field == DMCU_CAN_ACCESS_AUX) 109 return false; 110 /* enable AUX before request SW to access AUX */ 111 value = REG_READ(AUX_CONTROL); 112 field = get_reg_field_value(value, 113 AUX_CONTROL, 114 AUX_EN); 115 116 if (field == 0) { 117 set_reg_field_value( 118 value, 119 1, 120 AUX_CONTROL, 121 AUX_EN); 122 123 if (REG(AUX_RESET_MASK)) { 124 /*DP_AUX block as part of the enable sequence*/ 125 set_reg_field_value( 126 value, 127 1, 128 AUX_CONTROL, 129 AUX_RESET); 130 } 131 132 REG_WRITE(AUX_CONTROL, value); 133 134 if (REG(AUX_RESET_MASK)) { 135 /*poll HW to make sure reset it done*/ 136 137 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, 138 1, 11); 139 140 set_reg_field_value( 141 value, 142 0, 143 AUX_CONTROL, 144 AUX_RESET); 145 146 REG_WRITE(AUX_CONTROL, value); 147 148 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, 149 1, 11); 150 } 151 } /*if (field)*/ 152 153 /* request SW to access AUX */ 154 REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1); 155 156 value = REG_READ(AUX_ARB_CONTROL); 157 field = get_reg_field_value( 158 value, 159 AUX_ARB_CONTROL, 160 AUX_REG_RW_CNTL_STATUS); 161 162 return (field == SW_CAN_ACCESS_AUX); 163 } 164 165 #define COMPOSE_AUX_SW_DATA_16_20(command, address) \ 166 ((command) | ((0xF0000 & (address)) >> 16)) 167 168 #define COMPOSE_AUX_SW_DATA_8_15(address) \ 169 ((0xFF00 & (address)) >> 8) 170 171 #define COMPOSE_AUX_SW_DATA_0_7(address) \ 172 (0xFF & (address)) 173 174 static void submit_channel_request( 175 struct dce_aux *engine, 176 struct aux_request_transaction_data *request) 177 { 178 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 179 uint32_t value; 180 uint32_t length; 181 182 bool is_write = 183 ((request->type == AUX_TRANSACTION_TYPE_DP) && 184 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) || 185 ((request->type == AUX_TRANSACTION_TYPE_I2C) && 186 ((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) || 187 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT))); 188 if (REG(AUXN_IMPCAL)) { 189 /* clear_aux_error */ 190 REG_UPDATE_SEQ_2(AUXN_IMPCAL, 191 AUXN_CALOUT_ERROR_AK, 1, 192 AUXN_CALOUT_ERROR_AK, 0); 193 194 REG_UPDATE_SEQ_2(AUXP_IMPCAL, 195 AUXP_CALOUT_ERROR_AK, 1, 196 AUXP_CALOUT_ERROR_AK, 0); 197 198 /* force_default_calibrate */ 199 REG_UPDATE_SEQ_2(AUXN_IMPCAL, 200 AUXN_IMPCAL_ENABLE, 1, 201 AUXN_IMPCAL_OVERRIDE_ENABLE, 0); 202 203 /* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */ 204 205 REG_UPDATE_SEQ_2(AUXP_IMPCAL, 206 AUXP_IMPCAL_OVERRIDE_ENABLE, 1, 207 AUXP_IMPCAL_OVERRIDE_ENABLE, 0); 208 } 209 210 REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1); 211 212 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, 213 10, aux110->polling_timeout_period/10); 214 215 /* set the delay and the number of bytes to write */ 216 217 /* The length include 218 * the 4 bit header and the 20 bit address 219 * (that is 3 byte). 220 * If the requested length is non zero this means 221 * an addition byte specifying the length is required. 222 */ 223 224 length = request->length ? 4 : 3; 225 if (is_write) 226 length += request->length; 227 228 REG_UPDATE_2(AUX_SW_CONTROL, 229 AUX_SW_START_DELAY, request->delay, 230 AUX_SW_WR_BYTES, length); 231 232 /* program action and address and payload data (if 'is_write') */ 233 value = REG_UPDATE_4(AUX_SW_DATA, 234 AUX_SW_INDEX, 0, 235 AUX_SW_DATA_RW, 0, 236 AUX_SW_AUTOINCREMENT_DISABLE, 1, 237 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address)); 238 239 value = REG_SET_2(AUX_SW_DATA, value, 240 AUX_SW_AUTOINCREMENT_DISABLE, 0, 241 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address)); 242 243 value = REG_SET(AUX_SW_DATA, value, 244 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address)); 245 246 if (request->length) { 247 value = REG_SET(AUX_SW_DATA, value, 248 AUX_SW_DATA, request->length - 1); 249 } 250 251 if (is_write) { 252 /* Load the HW buffer with the Data to be sent. 253 * This is relevant for write operation. 254 * For read, the data recived data will be 255 * processed in process_channel_reply(). 256 */ 257 uint32_t i = 0; 258 259 while (i < request->length) { 260 value = REG_SET(AUX_SW_DATA, value, 261 AUX_SW_DATA, request->data[i]); 262 263 ++i; 264 } 265 } 266 267 REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1); 268 EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE, 269 request->action, request->address, request->length, request->data); 270 } 271 272 static int read_channel_reply(struct dce_aux *engine, uint32_t size, 273 uint8_t *buffer, uint8_t *reply_result, 274 uint32_t *sw_status) 275 { 276 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 277 uint32_t bytes_replied; 278 uint32_t reply_result_32; 279 280 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, 281 &bytes_replied); 282 283 /* In case HPD is LOW, exit AUX transaction */ 284 if ((*sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) 285 return -1; 286 287 /* Need at least the status byte */ 288 if (!bytes_replied) 289 return -1; 290 291 REG_UPDATE_SEQ_3(AUX_SW_DATA, 292 AUX_SW_INDEX, 0, 293 AUX_SW_AUTOINCREMENT_DISABLE, 1, 294 AUX_SW_DATA_RW, 1); 295 296 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); 297 reply_result_32 = reply_result_32 >> 4; 298 if (reply_result != NULL) 299 *reply_result = (uint8_t)reply_result_32; 300 301 if (reply_result_32 == 0) { /* ACK */ 302 uint32_t i = 0; 303 304 /* First byte was already used to get the command status */ 305 --bytes_replied; 306 307 /* Do not overflow buffer */ 308 if (bytes_replied > size) 309 return -1; 310 311 while (i < bytes_replied) { 312 uint32_t aux_sw_data_val; 313 314 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); 315 buffer[i] = aux_sw_data_val; 316 ++i; 317 } 318 319 return i; 320 } 321 322 return 0; 323 } 324 325 static enum aux_channel_operation_result get_channel_status( 326 struct dce_aux *engine, 327 uint8_t *returned_bytes) 328 { 329 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine); 330 331 uint32_t value; 332 333 if (returned_bytes == NULL) { 334 /*caller pass NULL pointer*/ 335 ASSERT_CRITICAL(false); 336 return AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN; 337 } 338 *returned_bytes = 0; 339 340 /* poll to make sure that SW_DONE is asserted */ 341 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, 342 10, aux110->polling_timeout_period/10); 343 344 value = REG_READ(AUX_SW_STATUS); 345 /* in case HPD is LOW, exit AUX transaction */ 346 if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) 347 return AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; 348 349 /* Note that the following bits are set in 'status.bits' 350 * during CTS 4.2.1.2 (FW 3.3.1): 351 * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP, 352 * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H. 353 * 354 * AUX_SW_RX_MIN_COUNT_VIOL is an internal, 355 * HW debugging bit and should be ignored. 356 */ 357 if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) { 358 if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) || 359 (value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK)) 360 return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT; 361 362 else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) || 363 (value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) || 364 (value & 365 AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) || 366 (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK)) 367 return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY; 368 369 *returned_bytes = get_reg_field_value(value, 370 AUX_SW_STATUS, 371 AUX_SW_REPLY_BYTE_COUNT); 372 373 if (*returned_bytes == 0) 374 return 375 AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY; 376 else { 377 *returned_bytes -= 1; 378 return AUX_CHANNEL_OPERATION_SUCCEEDED; 379 } 380 } else { 381 /*time_elapsed >= aux_engine->timeout_period 382 * AUX_SW_STATUS__AUX_SW_HPD_DISCON = at this point 383 */ 384 ASSERT_CRITICAL(false); 385 return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT; 386 } 387 } 388 389 enum i2caux_engine_type get_engine_type( 390 const struct dce_aux *engine) 391 { 392 return I2CAUX_ENGINE_TYPE_AUX; 393 } 394 395 static bool acquire( 396 struct dce_aux *engine, 397 struct ddc *ddc) 398 { 399 enum gpio_result result; 400 401 if (!is_engine_available(engine)) 402 return false; 403 404 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, 405 GPIO_DDC_CONFIG_TYPE_MODE_AUX); 406 407 if (result != GPIO_RESULT_OK) 408 return false; 409 410 if (!acquire_engine(engine)) { 411 dal_ddc_close(ddc); 412 return false; 413 } 414 415 engine->ddc = ddc; 416 417 return true; 418 } 419 420 void dce110_engine_destroy(struct dce_aux **engine) 421 { 422 423 struct aux_engine_dce110 *engine110 = FROM_AUX_ENGINE(*engine); 424 425 kfree(engine110); 426 *engine = NULL; 427 428 } 429 430 static bool dce_aux_configure_timeout(struct ddc_service *ddc, 431 uint32_t timeout_in_us) 432 { 433 uint32_t multiplier = 0; 434 uint32_t length = 0; 435 uint32_t timeout = 0; 436 struct ddc *ddc_pin = ddc->ddc_pin; 437 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 438 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine); 439 440 /* 1-Update polling timeout period */ 441 aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER; 442 443 /* 2-Update aux timeout period length and multiplier */ 444 if (timeout_in_us <= TIME_OUT_INCREMENT) { 445 multiplier = 0; 446 length = timeout_in_us/TIME_OUT_MULTIPLIER_8; 447 if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0) 448 length++; 449 timeout = length * TIME_OUT_MULTIPLIER_8; 450 } else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) { 451 multiplier = 1; 452 length = timeout_in_us/TIME_OUT_MULTIPLIER_16; 453 if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0) 454 length++; 455 timeout = length * TIME_OUT_MULTIPLIER_16; 456 } else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) { 457 multiplier = 2; 458 length = timeout_in_us/TIME_OUT_MULTIPLIER_32; 459 if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0) 460 length++; 461 timeout = length * TIME_OUT_MULTIPLIER_32; 462 } else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) { 463 multiplier = 3; 464 length = timeout_in_us/TIME_OUT_MULTIPLIER_64; 465 if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0) 466 length++; 467 timeout = length * TIME_OUT_MULTIPLIER_64; 468 } 469 470 length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH; 471 472 REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier); 473 474 return true; 475 } 476 477 static struct dce_aux_funcs aux_functions = { 478 .configure_timeout = NULL, 479 .destroy = NULL, 480 }; 481 482 struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110, 483 struct dc_context *ctx, 484 uint32_t inst, 485 uint32_t timeout_period, 486 const struct dce110_aux_registers *regs, 487 const struct dce110_aux_registers_mask *mask, 488 const struct dce110_aux_registers_shift *shift, 489 bool is_ext_aux_timeout_configurable) 490 { 491 aux_engine110->base.ddc = NULL; 492 aux_engine110->base.ctx = ctx; 493 aux_engine110->base.delay = 0; 494 aux_engine110->base.max_defer_write_retry = 0; 495 aux_engine110->base.inst = inst; 496 aux_engine110->polling_timeout_period = timeout_period; 497 aux_engine110->regs = regs; 498 499 aux_engine110->mask = mask; 500 aux_engine110->shift = shift; 501 aux_engine110->base.funcs = &aux_functions; 502 if (is_ext_aux_timeout_configurable) 503 aux_engine110->base.funcs->configure_timeout = &dce_aux_configure_timeout; 504 505 return &aux_engine110->base; 506 } 507 508 static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payload *payload) 509 { 510 if (payload->i2c_over_aux) { 511 if (payload->write) { 512 if (payload->mot) 513 return I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT; 514 return I2CAUX_TRANSACTION_ACTION_I2C_WRITE; 515 } 516 if (payload->mot) 517 return I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT; 518 return I2CAUX_TRANSACTION_ACTION_I2C_READ; 519 } 520 if (payload->write) 521 return I2CAUX_TRANSACTION_ACTION_DP_WRITE; 522 return I2CAUX_TRANSACTION_ACTION_DP_READ; 523 } 524 525 int dce_aux_transfer_raw(struct ddc_service *ddc, 526 struct aux_payload *payload, 527 enum aux_channel_operation_result *operation_result) 528 { 529 struct ddc *ddc_pin = ddc->ddc_pin; 530 struct dce_aux *aux_engine; 531 struct aux_request_transaction_data aux_req; 532 struct aux_reply_transaction_data aux_rep; 533 uint8_t returned_bytes = 0; 534 int res = -1; 535 uint32_t status; 536 537 memset(&aux_req, 0, sizeof(aux_req)); 538 memset(&aux_rep, 0, sizeof(aux_rep)); 539 540 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 541 if (!acquire(aux_engine, ddc_pin)) 542 return -1; 543 544 if (payload->i2c_over_aux) 545 aux_req.type = AUX_TRANSACTION_TYPE_I2C; 546 else 547 aux_req.type = AUX_TRANSACTION_TYPE_DP; 548 549 aux_req.action = i2caux_action_from_payload(payload); 550 551 aux_req.address = payload->address; 552 aux_req.delay = 0; 553 aux_req.length = payload->length; 554 aux_req.data = payload->data; 555 556 submit_channel_request(aux_engine, &aux_req); 557 *operation_result = get_channel_status(aux_engine, &returned_bytes); 558 559 if (*operation_result == AUX_CHANNEL_OPERATION_SUCCEEDED) { 560 int bytes_replied = 0; 561 bytes_replied = read_channel_reply(aux_engine, payload->length, 562 payload->data, payload->reply, 563 &status); 564 EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en, 565 EVENT_LOG_AUX_ORIGIN_NATIVE, *payload->reply, 566 bytes_replied, payload->data); 567 res = returned_bytes; 568 } else { 569 res = -1; 570 } 571 572 release_engine(aux_engine); 573 return res; 574 } 575 576 #define AUX_MAX_RETRIES 7 577 #define AUX_MAX_DEFER_RETRIES 7 578 #define AUX_MAX_I2C_DEFER_RETRIES 7 579 #define AUX_MAX_INVALID_REPLY_RETRIES 2 580 #define AUX_MAX_TIMEOUT_RETRIES 3 581 582 bool dce_aux_transfer_with_retries(struct ddc_service *ddc, 583 struct aux_payload *payload) 584 { 585 int i, ret = 0; 586 uint8_t reply; 587 bool payload_reply = true; 588 enum aux_channel_operation_result operation_result; 589 int aux_ack_retries = 0, 590 aux_defer_retries = 0, 591 aux_i2c_defer_retries = 0, 592 aux_timeout_retries = 0, 593 aux_invalid_reply_retries = 0; 594 595 if (!payload->reply) { 596 payload_reply = false; 597 payload->reply = &reply; 598 } 599 600 for (i = 0; i < AUX_MAX_RETRIES; i++) { 601 ret = dce_aux_transfer_raw(ddc, payload, &operation_result); 602 switch (operation_result) { 603 case AUX_CHANNEL_OPERATION_SUCCEEDED: 604 aux_timeout_retries = 0; 605 aux_invalid_reply_retries = 0; 606 607 switch (*payload->reply) { 608 case AUX_TRANSACTION_REPLY_AUX_ACK: 609 if (!payload->write && payload->length != ret) { 610 if (++aux_ack_retries >= AUX_MAX_RETRIES) 611 goto fail; 612 else 613 udelay(300); 614 } else 615 return true; 616 break; 617 618 case AUX_TRANSACTION_REPLY_AUX_DEFER: 619 case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK: 620 case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER: 621 if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) { 622 goto fail; 623 } else { 624 if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) || 625 (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) { 626 if (payload->defer_delay > 0) 627 msleep(payload->defer_delay); 628 } 629 } 630 break; 631 632 case AUX_TRANSACTION_REPLY_I2C_DEFER: 633 aux_defer_retries = 0; 634 if (++aux_i2c_defer_retries >= AUX_MAX_I2C_DEFER_RETRIES) 635 goto fail; 636 break; 637 638 case AUX_TRANSACTION_REPLY_AUX_NACK: 639 case AUX_TRANSACTION_REPLY_HPD_DISCON: 640 default: 641 goto fail; 642 } 643 break; 644 645 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY: 646 if (++aux_invalid_reply_retries >= AUX_MAX_INVALID_REPLY_RETRIES) 647 goto fail; 648 else 649 udelay(400); 650 break; 651 652 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT: 653 if (++aux_timeout_retries >= AUX_MAX_TIMEOUT_RETRIES) 654 goto fail; 655 else { 656 /* 657 * DP 1.4, 2.8.2: AUX Transaction Response/Reply Timeouts 658 * According to the DP spec there should be 3 retries total 659 * with a 400us wait inbetween each. Hardware already waits 660 * for 550us therefore no wait is required here. 661 */ 662 } 663 break; 664 665 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON: 666 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN: 667 default: 668 goto fail; 669 } 670 } 671 672 fail: 673 if (!payload_reply) 674 payload->reply = NULL; 675 return false; 676 } 677