xref: /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c (revision 19dc81b4017baffd6e919fd71cfc8dcbd5442e15)
1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 
29 #include "dm_services.h"
30 #include "core_types.h"
31 #include "dce_aux.h"
32 #include "dce/dce_11_0_sh_mask.h"
33 #include "dm_event_log.h"
34 #include "dm_helpers.h"
35 #include "dmub/inc/dmub_cmd.h"
36 
37 #define CTX \
38 	aux110->base.ctx
39 #define REG(reg_name)\
40 	(aux110->regs->reg_name)
41 
42 #define DC_LOGGER \
43 	engine->ctx->logger
44 
45 #define DC_TRACE_LEVEL_MESSAGE(...) do { } while (0)
46 #define IS_DC_I2CAUX_LOGGING_ENABLED() (false)
47 #define LOG_FLAG_Error_I2cAux LOG_ERROR
48 #define LOG_FLAG_I2cAux_DceAux LOG_I2C_AUX
49 
50 #include "reg_helper.h"
51 
52 #undef FN
53 #define FN(reg_name, field_name) \
54 	aux110->shift->field_name, aux110->mask->field_name
55 
56 #define FROM_AUX_ENGINE(ptr) \
57 	container_of((ptr), struct aux_engine_dce110, base)
58 
59 #define FROM_ENGINE(ptr) \
60 	FROM_AUX_ENGINE(container_of((ptr), struct dce_aux, base))
61 
62 #define FROM_AUX_ENGINE_ENGINE(ptr) \
63 	container_of((ptr), struct dce_aux, base)
64 enum {
65 	AUX_INVALID_REPLY_RETRY_COUNTER = 1,
66 	AUX_TIMED_OUT_RETRY_COUNTER = 2,
67 	AUX_DEFER_RETRY_COUNTER = 6
68 };
69 
70 #define TIME_OUT_INCREMENT        1016
71 #define TIME_OUT_MULTIPLIER_8     8
72 #define TIME_OUT_MULTIPLIER_16    16
73 #define TIME_OUT_MULTIPLIER_32    32
74 #define TIME_OUT_MULTIPLIER_64    64
75 #define MAX_TIMEOUT_LENGTH        127
76 #define DEFAULT_AUX_ENGINE_MULT   0
77 #define DEFAULT_AUX_ENGINE_LENGTH 69
78 
79 #define DC_TRACE_LEVEL_MESSAGE(...) do { } while (0)
80 
81 static void release_engine(
82 	struct dce_aux *engine)
83 {
84 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
85 
86 	dal_ddc_close(engine->ddc);
87 
88 	engine->ddc = NULL;
89 
90 	REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);
91 }
92 
93 #define SW_CAN_ACCESS_AUX 1
94 #define DMCU_CAN_ACCESS_AUX 2
95 
96 static bool is_engine_available(
97 	struct dce_aux *engine)
98 {
99 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
100 
101 	uint32_t value = REG_READ(AUX_ARB_CONTROL);
102 	uint32_t field = get_reg_field_value(
103 			value,
104 			AUX_ARB_CONTROL,
105 			AUX_REG_RW_CNTL_STATUS);
106 
107 	return (field != DMCU_CAN_ACCESS_AUX);
108 }
109 static bool acquire_engine(
110 	struct dce_aux *engine)
111 {
112 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
113 
114 	uint32_t value = REG_READ(AUX_ARB_CONTROL);
115 	uint32_t field = get_reg_field_value(
116 			value,
117 			AUX_ARB_CONTROL,
118 			AUX_REG_RW_CNTL_STATUS);
119 	if (field == DMCU_CAN_ACCESS_AUX)
120 		return false;
121 	/* enable AUX before request SW to access AUX */
122 	value = REG_READ(AUX_CONTROL);
123 	field = get_reg_field_value(value,
124 				AUX_CONTROL,
125 				AUX_EN);
126 
127 	if (field == 0) {
128 		set_reg_field_value(
129 				value,
130 				1,
131 				AUX_CONTROL,
132 				AUX_EN);
133 
134 		if (REG(AUX_RESET_MASK)) {
135 			/*DP_AUX block as part of the enable sequence*/
136 			set_reg_field_value(
137 				value,
138 				1,
139 				AUX_CONTROL,
140 				AUX_RESET);
141 		}
142 
143 		REG_WRITE(AUX_CONTROL, value);
144 
145 		if (REG(AUX_RESET_MASK)) {
146 			/*poll HW to make sure reset it done*/
147 
148 			REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
149 					1, 11);
150 
151 			set_reg_field_value(
152 				value,
153 				0,
154 				AUX_CONTROL,
155 				AUX_RESET);
156 
157 			REG_WRITE(AUX_CONTROL, value);
158 
159 			REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
160 					1, 11);
161 		}
162 	} /*if (field)*/
163 
164 	/* request SW to access AUX */
165 	REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);
166 
167 	value = REG_READ(AUX_ARB_CONTROL);
168 	field = get_reg_field_value(
169 			value,
170 			AUX_ARB_CONTROL,
171 			AUX_REG_RW_CNTL_STATUS);
172 
173 	return (field == SW_CAN_ACCESS_AUX);
174 }
175 
176 #define COMPOSE_AUX_SW_DATA_16_20(command, address) \
177 	((command) | ((0xF0000 & (address)) >> 16))
178 
179 #define COMPOSE_AUX_SW_DATA_8_15(address) \
180 	((0xFF00 & (address)) >> 8)
181 
182 #define COMPOSE_AUX_SW_DATA_0_7(address) \
183 	(0xFF & (address))
184 
185 static void submit_channel_request(
186 	struct dce_aux *engine,
187 	struct aux_request_transaction_data *request)
188 {
189 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
190 	uint32_t value;
191 	uint32_t length;
192 
193 	bool is_write =
194 		((request->type == AUX_TRANSACTION_TYPE_DP) &&
195 		 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) ||
196 		((request->type == AUX_TRANSACTION_TYPE_I2C) &&
197 		((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
198 		 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
199 	if (REG(AUXN_IMPCAL)) {
200 		/* clear_aux_error */
201 		REG_UPDATE_SEQ_2(AUXN_IMPCAL,
202 				AUXN_CALOUT_ERROR_AK, 1,
203 				AUXN_CALOUT_ERROR_AK, 0);
204 
205 		REG_UPDATE_SEQ_2(AUXP_IMPCAL,
206 				AUXP_CALOUT_ERROR_AK, 1,
207 				AUXP_CALOUT_ERROR_AK, 0);
208 
209 		/* force_default_calibrate */
210 		REG_UPDATE_SEQ_2(AUXN_IMPCAL,
211 				AUXN_IMPCAL_ENABLE, 1,
212 				AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
213 
214 		/* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */
215 
216 		REG_UPDATE_SEQ_2(AUXP_IMPCAL,
217 				AUXP_IMPCAL_OVERRIDE_ENABLE, 1,
218 				AUXP_IMPCAL_OVERRIDE_ENABLE, 0);
219 	}
220 
221 	REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
222 
223 	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
224 				10, aux110->polling_timeout_period/10);
225 
226 	/* set the delay and the number of bytes to write */
227 
228 	/* The length include
229 	 * the 4 bit header and the 20 bit address
230 	 * (that is 3 byte).
231 	 * If the requested length is non zero this means
232 	 * an addition byte specifying the length is required.
233 	 */
234 
235 	length = request->length ? 4 : 3;
236 	if (is_write)
237 		length += request->length;
238 
239 	REG_UPDATE_2(AUX_SW_CONTROL,
240 			AUX_SW_START_DELAY, request->delay,
241 			AUX_SW_WR_BYTES, length);
242 
243 	/* program action and address and payload data (if 'is_write') */
244 	value = REG_UPDATE_4(AUX_SW_DATA,
245 			AUX_SW_INDEX, 0,
246 			AUX_SW_DATA_RW, 0,
247 			AUX_SW_AUTOINCREMENT_DISABLE, 1,
248 			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address));
249 
250 	value = REG_SET_2(AUX_SW_DATA, value,
251 			AUX_SW_AUTOINCREMENT_DISABLE, 0,
252 			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address));
253 
254 	value = REG_SET(AUX_SW_DATA, value,
255 			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address));
256 
257 	if (request->length) {
258 		value = REG_SET(AUX_SW_DATA, value,
259 				AUX_SW_DATA, request->length - 1);
260 	}
261 
262 	if (is_write) {
263 		/* Load the HW buffer with the Data to be sent.
264 		 * This is relevant for write operation.
265 		 * For read, the data recived data will be
266 		 * processed in process_channel_reply().
267 		 */
268 		uint32_t i = 0;
269 
270 		while (i < request->length) {
271 			value = REG_SET(AUX_SW_DATA, value,
272 					AUX_SW_DATA, request->data[i]);
273 
274 			++i;
275 		}
276 	}
277 
278 	REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
279 	EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
280 					request->action, request->address, request->length, request->data);
281 }
282 
283 static int read_channel_reply(struct dce_aux *engine, uint32_t size,
284 			      uint8_t *buffer, uint8_t *reply_result,
285 			      uint32_t *sw_status)
286 {
287 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
288 	uint32_t bytes_replied;
289 	uint32_t reply_result_32;
290 
291 	*sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,
292 			     &bytes_replied);
293 
294 	/* In case HPD is LOW, exit AUX transaction */
295 	if ((*sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
296 		return -1;
297 
298 	/* Need at least the status byte */
299 	if (!bytes_replied)
300 		return -1;
301 
302 	REG_UPDATE_SEQ_3(AUX_SW_DATA,
303 			  AUX_SW_INDEX, 0,
304 			  AUX_SW_AUTOINCREMENT_DISABLE, 1,
305 			  AUX_SW_DATA_RW, 1);
306 
307 	REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
308 	reply_result_32 = reply_result_32 >> 4;
309 	if (reply_result != NULL)
310 		*reply_result = (uint8_t)reply_result_32;
311 
312 	if (reply_result_32 == 0) { /* ACK */
313 		uint32_t i = 0;
314 
315 		/* First byte was already used to get the command status */
316 		--bytes_replied;
317 
318 		/* Do not overflow buffer */
319 		if (bytes_replied > size)
320 			return -1;
321 
322 		while (i < bytes_replied) {
323 			uint32_t aux_sw_data_val;
324 
325 			REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
326 			buffer[i] = aux_sw_data_val;
327 			++i;
328 		}
329 
330 		return i;
331 	}
332 
333 	return 0;
334 }
335 
336 static enum aux_return_code_type get_channel_status(
337 	struct dce_aux *engine,
338 	uint8_t *returned_bytes)
339 {
340 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
341 
342 	uint32_t value;
343 
344 	if (returned_bytes == NULL) {
345 		/*caller pass NULL pointer*/
346 		ASSERT_CRITICAL(false);
347 		return AUX_RET_ERROR_UNKNOWN;
348 	}
349 	*returned_bytes = 0;
350 
351 	/* poll to make sure that SW_DONE is asserted */
352 	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
353 				10, aux110->polling_timeout_period/10);
354 
355 	value = REG_READ(AUX_SW_STATUS);
356 	/* in case HPD is LOW, exit AUX transaction */
357 	if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
358 		return AUX_RET_ERROR_HPD_DISCON;
359 
360 	/* Note that the following bits are set in 'status.bits'
361 	 * during CTS 4.2.1.2 (FW 3.3.1):
362 	 * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP,
363 	 * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H.
364 	 *
365 	 * AUX_SW_RX_MIN_COUNT_VIOL is an internal,
366 	 * HW debugging bit and should be ignored.
367 	 */
368 	if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) {
369 		if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) ||
370 			(value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK))
371 			return AUX_RET_ERROR_TIMEOUT;
372 
373 		else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) ||
374 			(value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) ||
375 			(value &
376 				AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) ||
377 			(value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
378 			return AUX_RET_ERROR_INVALID_REPLY;
379 
380 		*returned_bytes = get_reg_field_value(value,
381 				AUX_SW_STATUS,
382 				AUX_SW_REPLY_BYTE_COUNT);
383 
384 		if (*returned_bytes == 0)
385 			return
386 			AUX_RET_ERROR_INVALID_REPLY;
387 		else {
388 			*returned_bytes -= 1;
389 			return AUX_RET_SUCCESS;
390 		}
391 	} else {
392 		/*time_elapsed >= aux_engine->timeout_period
393 		 *  AUX_SW_STATUS__AUX_SW_HPD_DISCON = at this point
394 		 */
395 		ASSERT_CRITICAL(false);
396 		return AUX_RET_ERROR_TIMEOUT;
397 	}
398 }
399 
400 static bool acquire(
401 	struct dce_aux *engine,
402 	struct ddc *ddc)
403 {
404 	enum gpio_result result;
405 
406 	if ((engine == NULL) || !is_engine_available(engine))
407 		return false;
408 
409 	result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
410 		GPIO_DDC_CONFIG_TYPE_MODE_AUX);
411 
412 	if (result != GPIO_RESULT_OK)
413 		return false;
414 
415 	if (!acquire_engine(engine)) {
416 		engine->ddc = ddc;
417 		release_engine(engine);
418 		return false;
419 	}
420 
421 	engine->ddc = ddc;
422 
423 	return true;
424 }
425 
426 void dce110_engine_destroy(struct dce_aux **engine)
427 {
428 
429 	struct aux_engine_dce110 *engine110 = FROM_AUX_ENGINE(*engine);
430 
431 	kfree(engine110);
432 	*engine = NULL;
433 
434 }
435 
436 static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc,
437 		uint32_t timeout_in_us)
438 {
439 	uint32_t multiplier = 0;
440 	uint32_t length = 0;
441 	uint32_t prev_length = 0;
442 	uint32_t prev_mult = 0;
443 	uint32_t prev_timeout_val = 0;
444 	struct ddc *ddc_pin = ddc->ddc_pin;
445 	struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
446 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
447 
448 	/* 1-Update polling timeout period */
449 	aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER;
450 
451 	/* 2-Update aux timeout period length and multiplier */
452 	if (timeout_in_us == 0) {
453 		multiplier = DEFAULT_AUX_ENGINE_MULT;
454 		length = DEFAULT_AUX_ENGINE_LENGTH;
455 	} else if (timeout_in_us <= TIME_OUT_INCREMENT) {
456 		multiplier = 0;
457 		length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
458 		if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
459 			length++;
460 	} else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) {
461 		multiplier = 1;
462 		length = timeout_in_us/TIME_OUT_MULTIPLIER_16;
463 		if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0)
464 			length++;
465 	} else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) {
466 		multiplier = 2;
467 		length = timeout_in_us/TIME_OUT_MULTIPLIER_32;
468 		if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0)
469 			length++;
470 	} else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) {
471 		multiplier = 3;
472 		length = timeout_in_us/TIME_OUT_MULTIPLIER_64;
473 		if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0)
474 			length++;
475 	}
476 
477 	length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
478 
479 	REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
480 
481 	switch (prev_mult) {
482 	case 0:
483 		prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_8;
484 		break;
485 	case 1:
486 		prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_16;
487 		break;
488 	case 2:
489 		prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_32;
490 		break;
491 	case 3:
492 		prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_64;
493 		break;
494 	default:
495 		prev_timeout_val = DEFAULT_AUX_ENGINE_LENGTH * TIME_OUT_MULTIPLIER_8;
496 		break;
497 	}
498 
499 	REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier);
500 
501 	return prev_timeout_val;
502 }
503 
504 static struct dce_aux_funcs aux_functions = {
505 	.configure_timeout = NULL,
506 	.destroy = NULL,
507 };
508 
509 struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
510 		struct dc_context *ctx,
511 		uint32_t inst,
512 		uint32_t timeout_period,
513 		const struct dce110_aux_registers *regs,
514 		const struct dce110_aux_registers_mask *mask,
515 		const struct dce110_aux_registers_shift *shift,
516 		bool is_ext_aux_timeout_configurable)
517 {
518 	aux_engine110->base.ddc = NULL;
519 	aux_engine110->base.ctx = ctx;
520 	aux_engine110->base.delay = 0;
521 	aux_engine110->base.max_defer_write_retry = 0;
522 	aux_engine110->base.inst = inst;
523 	aux_engine110->polling_timeout_period = timeout_period;
524 	aux_engine110->regs = regs;
525 
526 	aux_engine110->mask = mask;
527 	aux_engine110->shift = shift;
528 	aux_engine110->base.funcs = &aux_functions;
529 	if (is_ext_aux_timeout_configurable)
530 		aux_engine110->base.funcs->configure_timeout = &dce_aux_configure_timeout;
531 
532 	return &aux_engine110->base;
533 }
534 
535 static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payload *payload)
536 {
537 	if (payload->i2c_over_aux) {
538 		if (payload->write_status_update) {
539 			if (payload->mot)
540 				return I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT;
541 			else
542 				return I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
543 		}
544 		if (payload->write) {
545 			if (payload->mot)
546 				return I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT;
547 			else
548 				return I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
549 		}
550 		if (payload->mot)
551 			return I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT;
552 
553 		return I2CAUX_TRANSACTION_ACTION_I2C_READ;
554 	}
555 	if (payload->write)
556 		return I2CAUX_TRANSACTION_ACTION_DP_WRITE;
557 
558 	return I2CAUX_TRANSACTION_ACTION_DP_READ;
559 }
560 
561 int dce_aux_transfer_raw(struct ddc_service *ddc,
562 		struct aux_payload *payload,
563 		enum aux_return_code_type *operation_result)
564 {
565 	struct ddc *ddc_pin = ddc->ddc_pin;
566 	struct dce_aux *aux_engine;
567 	struct aux_request_transaction_data aux_req;
568 	uint8_t returned_bytes = 0;
569 	int res = -1;
570 	uint32_t status;
571 
572 	memset(&aux_req, 0, sizeof(aux_req));
573 
574 	aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
575 	if (!acquire(aux_engine, ddc_pin)) {
576 		*operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
577 		return -1;
578 	}
579 
580 	if (payload->i2c_over_aux)
581 		aux_req.type = AUX_TRANSACTION_TYPE_I2C;
582 	else
583 		aux_req.type = AUX_TRANSACTION_TYPE_DP;
584 
585 	aux_req.action = i2caux_action_from_payload(payload);
586 
587 	aux_req.address = payload->address;
588 	aux_req.delay = 0;
589 	aux_req.length = payload->length;
590 	aux_req.data = payload->data;
591 
592 	submit_channel_request(aux_engine, &aux_req);
593 	*operation_result = get_channel_status(aux_engine, &returned_bytes);
594 
595 	if (*operation_result == AUX_RET_SUCCESS) {
596 		int __maybe_unused bytes_replied = 0;
597 
598 		bytes_replied = read_channel_reply(aux_engine, payload->length,
599 					 payload->data, payload->reply,
600 					 &status);
601 		EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en,
602 					EVENT_LOG_AUX_ORIGIN_NATIVE, *payload->reply,
603 					bytes_replied, payload->data);
604 		res = returned_bytes;
605 	} else {
606 		res = -1;
607 	}
608 
609 	release_engine(aux_engine);
610 	return res;
611 }
612 
613 int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
614 		struct aux_payload *payload,
615 		enum aux_return_code_type *operation_result)
616 {
617 	struct ddc *ddc_pin = ddc->ddc_pin;
618 
619 	if (ddc_pin != NULL) {
620 		struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
621 		/* XXX: Workaround to configure ddc channels for aux transactions */
622 		if (!acquire(aux_engine, ddc_pin)) {
623 			*operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
624 			return -1;
625 		}
626 		release_engine(aux_engine);
627 	}
628 
629 	return dm_helper_dmub_aux_transfer_sync(ddc->ctx, ddc->link, payload, operation_result);
630 }
631 
632 #define AUX_MAX_RETRIES 7
633 #define AUX_MIN_DEFER_RETRIES 7
634 #define AUX_MAX_DEFER_TIMEOUT_MS 50
635 #define AUX_MAX_I2C_DEFER_RETRIES 7
636 #define AUX_MAX_INVALID_REPLY_RETRIES 2
637 #define AUX_MAX_TIMEOUT_RETRIES 3
638 #define AUX_DEFER_DELAY_FOR_DPIA 4 /*ms*/
639 
640 static void dce_aux_log_payload(const char *payload_name,
641 	unsigned char *payload, uint32_t length, uint32_t max_length_to_log)
642 {
643 	if (!IS_DC_I2CAUX_LOGGING_ENABLED())
644 		return;
645 
646 	if (payload && length) {
647 		char hex_str[128] = {0};
648 		char *hex_str_ptr = &hex_str[0];
649 		uint32_t hex_str_remaining = sizeof(hex_str);
650 		unsigned char *payload_ptr = payload;
651 		unsigned char *payload_max_to_log_ptr = payload_ptr + min(max_length_to_log, length);
652 		unsigned int count;
653 		char *padding = "";
654 
655 		while (payload_ptr < payload_max_to_log_ptr) {
656 			count = snprintf_count(hex_str_ptr, hex_str_remaining, "%s%02X", padding, *payload_ptr);
657 			padding = " ";
658 			hex_str_remaining -= count;
659 			hex_str_ptr += count;
660 			payload_ptr++;
661 		}
662 
663 		count = snprintf_count(hex_str_ptr, hex_str_remaining, "   ");
664 		hex_str_remaining -= count;
665 		hex_str_ptr += count;
666 
667 		payload_ptr = payload;
668 		while (payload_ptr < payload_max_to_log_ptr) {
669 			count = snprintf_count(hex_str_ptr, hex_str_remaining, "%c",
670 				*payload_ptr >= ' ' ? *payload_ptr : '.');
671 			hex_str_remaining -= count;
672 			hex_str_ptr += count;
673 			payload_ptr++;
674 		}
675 
676 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
677 					LOG_FLAG_I2cAux_DceAux,
678 					"dce_aux_log_payload: %s: length=%u: data: %s%s",
679 					payload_name,
680 					length,
681 					hex_str,
682 					(length > max_length_to_log ? " (...)" : " "));
683 	} else {
684 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
685 					LOG_FLAG_I2cAux_DceAux,
686 					"dce_aux_log_payload: %s: length=%u: data: <empty payload>",
687 					payload_name,
688 					length);
689 	}
690 }
691 
692 bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
693 		struct aux_payload *payload)
694 {
695 	int i, ret = 0;
696 	uint8_t reply;
697 	bool payload_reply = true;
698 	enum aux_return_code_type operation_result;
699 	bool retry_on_defer = false;
700 	struct ddc *ddc_pin = ddc->ddc_pin;
701 	struct dce_aux *aux_engine = NULL;
702 	struct aux_engine_dce110 *aux110 = NULL;
703 	uint32_t defer_time_in_ms = 0;
704 
705 	int aux_ack_retries = 0,
706 		aux_defer_retries = 0,
707 		aux_i2c_defer_retries = 0,
708 		aux_timeout_retries = 0,
709 		aux_invalid_reply_retries = 0,
710 		aux_ack_m_retries = 0;
711 
712 	if (ddc_pin) {
713 		aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
714 		aux110 = FROM_AUX_ENGINE(aux_engine);
715 	}
716 
717 	if (!payload->reply) {
718 		payload_reply = false;
719 		payload->reply = &reply;
720 	}
721 
722 	for (i = 0; i < AUX_MAX_RETRIES; i++) {
723 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
724 					LOG_FLAG_I2cAux_DceAux,
725 					"dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: address=0x%04x length=%u write=%d mot=%d",
726 					ddc && ddc->link ? ddc->link->link_index : UINT_MAX,
727 					i + 1,
728 					(int)AUX_MAX_RETRIES,
729 					payload->address,
730 					payload->length,
731 					(unsigned int) payload->write,
732 					(unsigned int) payload->mot);
733 		if (payload->write)
734 			dce_aux_log_payload("  write", payload->data, payload->length, 16);
735 		ret = dce_aux_transfer_raw(ddc, payload, &operation_result);
736 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
737 					LOG_FLAG_I2cAux_DceAux,
738 					"dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d payload->reply=%u",
739 					ddc && ddc->link ? ddc->link->link_index : UINT_MAX,
740 					i + 1,
741 					(int)AUX_MAX_RETRIES,
742 					payload->address,
743 					payload->length,
744 					(unsigned int) payload->write,
745 					(unsigned int) payload->mot,
746 					ret,
747 					(int)operation_result,
748 					(unsigned int) *payload->reply);
749 		if (!payload->write)
750 			dce_aux_log_payload("  read", payload->data, ret > 0 ? ret : 0, 16);
751 
752 		switch (operation_result) {
753 		case AUX_RET_SUCCESS:
754 			aux_timeout_retries = 0;
755 			aux_invalid_reply_retries = 0;
756 
757 			switch (*payload->reply) {
758 			case AUX_TRANSACTION_REPLY_AUX_ACK:
759 				DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
760 							LOG_FLAG_I2cAux_DceAux,
761 							"dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_AUX_ACK");
762 				if (!payload->write && payload->length != ret) {
763 					if (++aux_ack_retries >= AUX_MAX_RETRIES) {
764 						DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
765 									LOG_FLAG_Error_I2cAux,
766 									"dce_aux_transfer_with_retries: FAILURE: aux_ack_retries=%d >= AUX_MAX_RETRIES=%d",
767 									aux_defer_retries,
768 									AUX_MAX_RETRIES);
769 						goto fail;
770 					} else
771 						udelay(300);
772 				} else if (payload->write && ret > 0) {
773 					/* sink requested more time to complete the write via AUX_ACKM */
774 					if (++aux_ack_m_retries >= AUX_MAX_RETRIES) {
775 						DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
776 								LOG_FLAG_Error_I2cAux,
777 								"dce_aux_transfer_with_retries: FAILURE: aux_ack_m_retries=%d >= AUX_MAX_RETRIES=%d",
778 								aux_ack_m_retries,
779 								AUX_MAX_RETRIES);
780 						goto fail;
781 					}
782 
783 					/* retry reading the write status until complete
784 					 * NOTE: payload is modified here
785 					 */
786 					payload->write = false;
787 					payload->write_status_update = true;
788 					payload->length = 0;
789 					udelay(300);
790 
791 				} else
792 					return true;
793 			break;
794 
795 			case AUX_TRANSACTION_REPLY_AUX_DEFER:
796 				DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
797 							LOG_FLAG_I2cAux_DceAux,
798 							"dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_AUX_DEFER");
799 
800 				/* polling_timeout_period is in us */
801 				if (aux110)
802 					defer_time_in_ms += aux110->polling_timeout_period / 1000;
803 				else
804 					defer_time_in_ms += AUX_DEFER_DELAY_FOR_DPIA;
805 				++aux_defer_retries;
806 				fallthrough;
807 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
808 				if (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)
809 					DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
810 								LOG_FLAG_I2cAux_DceAux,
811 								"dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER");
812 
813 				retry_on_defer = true;
814 				fallthrough;
815 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
816 				if (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK)
817 					DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
818 								LOG_FLAG_I2cAux_DceAux,
819 								"dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK");
820 
821 				if (aux_defer_retries >= AUX_MIN_DEFER_RETRIES
822 						&& defer_time_in_ms >= AUX_MAX_DEFER_TIMEOUT_MS) {
823 					DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
824 								LOG_FLAG_Error_I2cAux,
825 								"dce_aux_transfer_with_retries: FAILURE: aux_defer_retries=%d >= AUX_MIN_DEFER_RETRIES=%d && defer_time_in_ms=%d >= AUX_MAX_DEFER_TIMEOUT_MS=%d",
826 								aux_defer_retries,
827 								AUX_MIN_DEFER_RETRIES,
828 								defer_time_in_ms,
829 								AUX_MAX_DEFER_TIMEOUT_MS);
830 					goto fail;
831 				} else {
832 					if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
833 						(*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
834 						DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
835 									LOG_FLAG_I2cAux_DceAux,
836 									"dce_aux_transfer_with_retries: payload->defer_delay=%u",
837 									payload->defer_delay);
838 						if (payload->defer_delay > 1) {
839 							msleep(payload->defer_delay);
840 							defer_time_in_ms += payload->defer_delay;
841 						} else if (payload->defer_delay <= 1) {
842 							udelay(payload->defer_delay * 1000);
843 							defer_time_in_ms += payload->defer_delay;
844 						}
845 					}
846 				}
847 				break;
848 
849 			case AUX_TRANSACTION_REPLY_I2C_DEFER:
850 				DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
851 							LOG_FLAG_I2cAux_DceAux,
852 							"dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_I2C_DEFER");
853 
854 				aux_defer_retries = 0;
855 				if (++aux_i2c_defer_retries >= AUX_MAX_I2C_DEFER_RETRIES) {
856 					DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
857 								LOG_FLAG_Error_I2cAux,
858 								"dce_aux_transfer_with_retries: FAILURE: aux_i2c_defer_retries=%d >= AUX_MAX_I2C_DEFER_RETRIES=%d",
859 								aux_i2c_defer_retries,
860 								AUX_MAX_I2C_DEFER_RETRIES);
861 					goto fail;
862 				}
863 				break;
864 
865 			case AUX_TRANSACTION_REPLY_AUX_NACK:
866 				DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
867 							LOG_FLAG_I2cAux_DceAux,
868 							"dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_AUX_NACK");
869 				goto fail;
870 
871 			case AUX_TRANSACTION_REPLY_HPD_DISCON:
872 				DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
873 							LOG_FLAG_I2cAux_DceAux,
874 							"dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_HPD_DISCON");
875 				goto fail;
876 
877 			default:
878 				DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
879 							LOG_FLAG_Error_I2cAux,
880 							"dce_aux_transfer_with_retries: AUX_RET_SUCCESS: FAILURE: AUX_TRANSACTION_REPLY_* unknown, default case. Reply: %d", *payload->reply);
881 				goto fail;
882 			}
883 			break;
884 
885 		case AUX_RET_ERROR_INVALID_REPLY:
886 			DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
887 						LOG_FLAG_I2cAux_DceAux,
888 						"dce_aux_transfer_with_retries: AUX_RET_ERROR_INVALID_REPLY");
889 			if (++aux_invalid_reply_retries >= AUX_MAX_INVALID_REPLY_RETRIES) {
890 				DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
891 							LOG_FLAG_Error_I2cAux,
892 							"dce_aux_transfer_with_retries: FAILURE: aux_invalid_reply_retries=%d >= AUX_MAX_INVALID_REPLY_RETRIES=%d",
893 							aux_invalid_reply_retries,
894 							AUX_MAX_INVALID_REPLY_RETRIES);
895 				goto fail;
896 			} else
897 				udelay(400);
898 			break;
899 
900 		case AUX_RET_ERROR_TIMEOUT:
901 			DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
902 						LOG_FLAG_I2cAux_DceAux,
903 						"dce_aux_transfer_with_retries: AUX_RET_ERROR_TIMEOUT");
904 			// Check whether a DEFER had occurred before the timeout.
905 			// If so, treat timeout as a DEFER.
906 			if (retry_on_defer) {
907 				if (++aux_defer_retries >= AUX_MIN_DEFER_RETRIES) {
908 					DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
909 								LOG_FLAG_Error_I2cAux,
910 								"dce_aux_transfer_with_retries: FAILURE: aux_defer_retries=%d >= AUX_MIN_DEFER_RETRIES=%d",
911 								aux_defer_retries,
912 								AUX_MIN_DEFER_RETRIES);
913 					goto fail;
914 				} else if (payload->defer_delay > 0) {
915 					DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
916 								LOG_FLAG_I2cAux_DceAux,
917 								"dce_aux_transfer_with_retries: payload->defer_delay=%u",
918 								payload->defer_delay);
919 					msleep(payload->defer_delay);
920 				}
921 			} else {
922 				if (++aux_timeout_retries >= AUX_MAX_TIMEOUT_RETRIES) {
923 					DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
924 								LOG_FLAG_Error_I2cAux,
925 								"dce_aux_transfer_with_retries: FAILURE: aux_timeout_retries=%d >= AUX_MAX_TIMEOUT_RETRIES=%d",
926 								aux_timeout_retries,
927 								AUX_MAX_TIMEOUT_RETRIES);
928 					goto fail;
929 				} else {
930 					/*
931 					 * DP 1.4, 2.8.2:  AUX Transaction Response/Reply Timeouts
932 					 * According to the DP spec there should be 3 retries total
933 					 * with a 400us wait inbetween each. Hardware already waits
934 					 * for 550us therefore no wait is required here.
935 					 */
936 				}
937 			}
938 			break;
939 
940 		case AUX_RET_ERROR_HPD_DISCON:
941 		case AUX_RET_ERROR_ENGINE_ACQUIRE:
942 		case AUX_RET_ERROR_UNKNOWN:
943 		default:
944 			DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
945 						LOG_FLAG_I2cAux_DceAux,
946 						"dce_aux_transfer_with_retries: Failure: operation_result=%d",
947 						(int)operation_result);
948 			goto fail;
949 		}
950 	}
951 
952 fail:
953 	DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
954 				LOG_FLAG_Error_I2cAux,
955 				"dce_aux_transfer_with_retries: FAILURE");
956 	if (!payload_reply)
957 		payload->reply = NULL;
958 
959 	DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
960 				WPP_BIT_FLAG_DC_ERROR,
961 				"AUX transaction failed. Result: %d",
962 				operation_result);
963 
964 	return false;
965 }
966