1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dce_audio.h" 28 #include "dce/dce_11_0_d.h" 29 #include "dce/dce_11_0_sh_mask.h" 30 31 #define DCE_AUD(audio)\ 32 container_of(audio, struct dce_audio, base) 33 34 #define CTX \ 35 aud->base.ctx 36 #define REG(reg)\ 37 (aud->regs->reg) 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 aud->shifts->field_name, aud->masks->field_name 42 43 #define IX_REG(reg)\ 44 ix ## reg 45 46 #define AZ_REG_READ(reg_name) \ 47 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 48 49 #define AZ_REG_WRITE(reg_name, value) \ 50 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 51 52 static void write_indirect_azalia_reg(struct audio *audio, 53 uint32_t reg_index, 54 uint32_t reg_data) 55 { 56 struct dce_audio *aud = DCE_AUD(audio); 57 58 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 59 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 60 AZALIA_ENDPOINT_REG_INDEX, reg_index); 61 62 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 63 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 64 AZALIA_ENDPOINT_REG_DATA, reg_data); 65 66 dm_logger_write(CTX->logger, LOG_HW_AUDIO, 67 "AUDIO:write_indirect_azalia_reg: index: %u data: %u\n", 68 reg_index, reg_data); 69 } 70 71 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 72 { 73 struct dce_audio *aud = DCE_AUD(audio); 74 75 uint32_t value = 0; 76 77 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 78 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 79 AZALIA_ENDPOINT_REG_INDEX, reg_index); 80 81 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 82 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 83 84 dm_logger_write(CTX->logger, LOG_HW_AUDIO, 85 "AUDIO:read_indirect_azalia_reg: index: %u data: %u\n", 86 reg_index, value); 87 88 return value; 89 } 90 91 static bool is_audio_format_supported( 92 const struct audio_info *audio_info, 93 enum audio_format_code audio_format_code, 94 uint32_t *format_index) 95 { 96 uint32_t index; 97 uint32_t max_channe_index = 0; 98 bool found = false; 99 100 if (audio_info == NULL) 101 return found; 102 103 /* pass through whole array */ 104 for (index = 0; index < audio_info->mode_count; index++) { 105 if (audio_info->modes[index].format_code == audio_format_code) { 106 if (found) { 107 /* format has multiply entries, choose one with 108 * highst number of channels */ 109 if (audio_info->modes[index].channel_count > 110 audio_info->modes[max_channe_index].channel_count) { 111 max_channe_index = index; 112 } 113 } else { 114 /* format found, save it's index */ 115 found = true; 116 max_channe_index = index; 117 } 118 } 119 } 120 121 /* return index */ 122 if (found && format_index != NULL) 123 *format_index = max_channe_index; 124 125 return found; 126 } 127 128 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 129 static void check_audio_bandwidth_hdmi( 130 const struct audio_crtc_info *crtc_info, 131 uint32_t channel_count, 132 union audio_sample_rates *sample_rates) 133 { 134 uint32_t samples; 135 uint32_t h_blank; 136 bool limit_freq_to_48_khz = false; 137 bool limit_freq_to_88_2_khz = false; 138 bool limit_freq_to_96_khz = false; 139 bool limit_freq_to_174_4_khz = false; 140 141 /* For two channels supported return whatever sink support,unmodified*/ 142 if (channel_count > 2) { 143 144 /* Based on HDMI spec 1.3 Table 7.5 */ 145 if ((crtc_info->requested_pixel_clock <= 27000) && 146 (crtc_info->v_active <= 576) && 147 !(crtc_info->interlaced) && 148 !(crtc_info->pixel_repetition == 2 || 149 crtc_info->pixel_repetition == 4)) { 150 limit_freq_to_48_khz = true; 151 152 } else if ((crtc_info->requested_pixel_clock <= 27000) && 153 (crtc_info->v_active <= 576) && 154 (crtc_info->interlaced) && 155 (crtc_info->pixel_repetition == 2)) { 156 limit_freq_to_88_2_khz = true; 157 158 } else if ((crtc_info->requested_pixel_clock <= 54000) && 159 (crtc_info->v_active <= 576) && 160 !(crtc_info->interlaced)) { 161 limit_freq_to_174_4_khz = true; 162 } 163 } 164 165 /* Also do some calculation for the available Audio Bandwidth for the 166 * 8 ch (i.e. for the Layout 1 => ch > 2) 167 */ 168 h_blank = crtc_info->h_total - crtc_info->h_active; 169 170 if (crtc_info->pixel_repetition) 171 h_blank *= crtc_info->pixel_repetition; 172 173 /*based on HDMI spec 1.3 Table 7.5 */ 174 h_blank -= 58; 175 /*for Control Period */ 176 h_blank -= 16; 177 178 samples = h_blank * 10; 179 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 180 * of Audio samples per line multiplied by 10 - Layout 1) 181 */ 182 samples /= 32; 183 samples *= crtc_info->v_active; 184 /*Number of samples multiplied by 10, per second */ 185 samples *= crtc_info->refresh_rate; 186 /*Number of Audio samples per second */ 187 samples /= 10; 188 189 /* @todo do it after deep color is implemented 190 * 8xx - deep color bandwidth scaling 191 * Extra bandwidth is avaliable in deep color b/c link runs faster than 192 * pixel rate. This has the effect of allowing more tmds characters to 193 * be transmitted during blank 194 */ 195 196 switch (crtc_info->color_depth) { 197 case COLOR_DEPTH_888: 198 samples *= 4; 199 break; 200 case COLOR_DEPTH_101010: 201 samples *= 5; 202 break; 203 case COLOR_DEPTH_121212: 204 samples *= 6; 205 break; 206 default: 207 samples *= 4; 208 break; 209 } 210 211 samples /= 4; 212 213 /*check limitation*/ 214 if (samples < 88200) 215 limit_freq_to_48_khz = true; 216 else if (samples < 96000) 217 limit_freq_to_88_2_khz = true; 218 else if (samples < 176400) 219 limit_freq_to_96_khz = true; 220 else if (samples < 192000) 221 limit_freq_to_174_4_khz = true; 222 223 if (sample_rates != NULL) { 224 /* limit frequencies */ 225 if (limit_freq_to_174_4_khz) 226 sample_rates->rate.RATE_192 = 0; 227 228 if (limit_freq_to_96_khz) { 229 sample_rates->rate.RATE_192 = 0; 230 sample_rates->rate.RATE_176_4 = 0; 231 } 232 if (limit_freq_to_88_2_khz) { 233 sample_rates->rate.RATE_192 = 0; 234 sample_rates->rate.RATE_176_4 = 0; 235 sample_rates->rate.RATE_96 = 0; 236 } 237 if (limit_freq_to_48_khz) { 238 sample_rates->rate.RATE_192 = 0; 239 sample_rates->rate.RATE_176_4 = 0; 240 sample_rates->rate.RATE_96 = 0; 241 sample_rates->rate.RATE_88_2 = 0; 242 } 243 } 244 } 245 246 /*For DP SST, calculate if specified sample rates can fit into a given timing */ 247 static void check_audio_bandwidth_dpsst( 248 const struct audio_crtc_info *crtc_info, 249 uint32_t channel_count, 250 union audio_sample_rates *sample_rates) 251 { 252 /* do nothing */ 253 } 254 255 /*For DP MST, calculate if specified sample rates can fit into a given timing */ 256 static void check_audio_bandwidth_dpmst( 257 const struct audio_crtc_info *crtc_info, 258 uint32_t channel_count, 259 union audio_sample_rates *sample_rates) 260 { 261 /* do nothing */ 262 } 263 264 static void check_audio_bandwidth( 265 const struct audio_crtc_info *crtc_info, 266 uint32_t channel_count, 267 enum signal_type signal, 268 union audio_sample_rates *sample_rates) 269 { 270 switch (signal) { 271 case SIGNAL_TYPE_HDMI_TYPE_A: 272 check_audio_bandwidth_hdmi( 273 crtc_info, channel_count, sample_rates); 274 break; 275 case SIGNAL_TYPE_EDP: 276 case SIGNAL_TYPE_DISPLAY_PORT: 277 check_audio_bandwidth_dpsst( 278 crtc_info, channel_count, sample_rates); 279 break; 280 case SIGNAL_TYPE_DISPLAY_PORT_MST: 281 check_audio_bandwidth_dpmst( 282 crtc_info, channel_count, sample_rates); 283 break; 284 default: 285 break; 286 } 287 } 288 289 /* expose/not expose HBR capability to Audio driver */ 290 static void set_high_bit_rate_capable( 291 struct audio *audio, 292 bool capable) 293 { 294 uint32_t value = 0; 295 296 /* set high bit rate audio capable*/ 297 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 298 299 set_reg_field_value(value, capable, 300 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 301 HBR_CAPABLE); 302 303 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 304 } 305 306 /* set video latency in in ms/2+1 */ 307 static void set_video_latency( 308 struct audio *audio, 309 int latency_in_ms) 310 { 311 uint32_t value = 0; 312 313 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 314 return; 315 316 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 317 318 set_reg_field_value(value, latency_in_ms, 319 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 320 VIDEO_LIPSYNC); 321 322 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 323 value); 324 } 325 326 /* set audio latency in in ms/2+1 */ 327 static void set_audio_latency( 328 struct audio *audio, 329 int latency_in_ms) 330 { 331 uint32_t value = 0; 332 333 if (latency_in_ms < 0) 334 latency_in_ms = 0; 335 336 if (latency_in_ms > 255) 337 latency_in_ms = 255; 338 339 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 340 341 set_reg_field_value(value, latency_in_ms, 342 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 343 AUDIO_LIPSYNC); 344 345 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 346 value); 347 } 348 349 void dce_aud_az_enable(struct audio *audio) 350 { 351 struct dce_audio *aud = DCE_AUD(audio); 352 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 353 354 set_reg_field_value(value, 1, 355 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 356 CLOCK_GATING_DISABLE); 357 set_reg_field_value(value, 1, 358 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 359 AUDIO_ENABLED); 360 361 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 362 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 363 364 dm_logger_write(CTX->logger, LOG_HW_AUDIO, 365 "\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", 366 audio->inst, value); 367 } 368 369 void dce_aud_az_disable(struct audio *audio) 370 { 371 uint32_t value; 372 struct dce_audio *aud = DCE_AUD(audio); 373 374 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 375 376 set_reg_field_value(value, 0, 377 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 378 AUDIO_ENABLED); 379 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 380 381 set_reg_field_value(value, 0, 382 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 383 CLOCK_GATING_DISABLE); 384 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 385 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 386 dm_logger_write(CTX->logger, LOG_HW_AUDIO, 387 "\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", 388 audio->inst, value); 389 } 390 391 void dce_aud_az_configure( 392 struct audio *audio, 393 enum signal_type signal, 394 const struct audio_crtc_info *crtc_info, 395 const struct audio_info *audio_info) 396 { 397 struct dce_audio *aud = DCE_AUD(audio); 398 399 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 400 uint32_t value; 401 uint32_t field = 0; 402 enum audio_format_code audio_format_code; 403 uint32_t format_index; 404 uint32_t index; 405 bool is_ac3_supported = false; 406 union audio_sample_rates sample_rate; 407 uint32_t strlen = 0; 408 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 409 set_reg_field_value(value, 1, 410 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 411 CLOCK_GATING_DISABLE); 412 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 413 414 /* Speaker Allocation */ 415 /* 416 uint32_t value; 417 uint32_t field = 0;*/ 418 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 419 420 set_reg_field_value(value, 421 speakers, 422 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 423 SPEAKER_ALLOCATION); 424 425 /* LFE_PLAYBACK_LEVEL = LFEPBL 426 * LFEPBL = 0 : Unknown or refer to other information 427 * LFEPBL = 1 : 0dB playback 428 * LFEPBL = 2 : +10dB playback 429 * LFE_BL = 3 : Reserved 430 */ 431 set_reg_field_value(value, 432 0, 433 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 434 LFE_PLAYBACK_LEVEL); 435 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 436 * why are we writing to it? DCE8 does not write this */ 437 438 439 set_reg_field_value(value, 440 0, 441 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 442 HDMI_CONNECTION); 443 444 set_reg_field_value(value, 445 0, 446 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 447 DP_CONNECTION); 448 449 field = get_reg_field_value(value, 450 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 451 EXTRA_CONNECTION_INFO); 452 453 field &= ~0x1; 454 455 set_reg_field_value(value, 456 field, 457 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 458 EXTRA_CONNECTION_INFO); 459 460 /* set audio for output signal */ 461 switch (signal) { 462 case SIGNAL_TYPE_HDMI_TYPE_A: 463 set_reg_field_value(value, 464 1, 465 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 466 HDMI_CONNECTION); 467 468 break; 469 470 case SIGNAL_TYPE_EDP: 471 case SIGNAL_TYPE_DISPLAY_PORT: 472 case SIGNAL_TYPE_DISPLAY_PORT_MST: 473 set_reg_field_value(value, 474 1, 475 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 476 DP_CONNECTION); 477 break; 478 default: 479 BREAK_TO_DEBUGGER(); 480 break; 481 } 482 483 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 484 485 /* Audio Descriptors */ 486 /* pass through all formats */ 487 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 488 format_index++) { 489 audio_format_code = 490 (AUDIO_FORMAT_CODE_FIRST + format_index); 491 492 /* those are unsupported, skip programming */ 493 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 494 audio_format_code == AUDIO_FORMAT_CODE_DST) 495 continue; 496 497 value = 0; 498 499 /* check if supported */ 500 if (is_audio_format_supported( 501 audio_info, audio_format_code, &index)) { 502 const struct audio_mode *audio_mode = 503 &audio_info->modes[index]; 504 union audio_sample_rates sample_rates = 505 audio_mode->sample_rates; 506 uint8_t byte2 = audio_mode->max_bit_rate; 507 508 /* adjust specific properties */ 509 switch (audio_format_code) { 510 case AUDIO_FORMAT_CODE_LINEARPCM: { 511 check_audio_bandwidth( 512 crtc_info, 513 audio_mode->channel_count, 514 signal, 515 &sample_rates); 516 517 byte2 = audio_mode->sample_size; 518 519 set_reg_field_value(value, 520 sample_rates.all, 521 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 522 SUPPORTED_FREQUENCIES_STEREO); 523 } 524 break; 525 case AUDIO_FORMAT_CODE_AC3: 526 is_ac3_supported = true; 527 break; 528 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 529 case AUDIO_FORMAT_CODE_DTS_HD: 530 case AUDIO_FORMAT_CODE_MAT_MLP: 531 case AUDIO_FORMAT_CODE_DST: 532 case AUDIO_FORMAT_CODE_WMAPRO: 533 byte2 = audio_mode->vendor_specific; 534 break; 535 default: 536 break; 537 } 538 539 /* fill audio format data */ 540 set_reg_field_value(value, 541 audio_mode->channel_count - 1, 542 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 543 MAX_CHANNELS); 544 545 set_reg_field_value(value, 546 sample_rates.all, 547 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 548 SUPPORTED_FREQUENCIES); 549 550 set_reg_field_value(value, 551 byte2, 552 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 553 DESCRIPTOR_BYTE_2); 554 } /* if */ 555 556 AZ_REG_WRITE( 557 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 558 value); 559 } /* for */ 560 561 if (is_ac3_supported) 562 /* todo: this reg global. why program global register? */ 563 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 564 0x05); 565 566 /* check for 192khz/8-Ch support for HBR requirements */ 567 sample_rate.all = 0; 568 sample_rate.rate.RATE_192 = 1; 569 570 check_audio_bandwidth( 571 crtc_info, 572 8, 573 signal, 574 &sample_rate); 575 576 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 577 578 /* Audio and Video Lipsync */ 579 set_video_latency(audio, audio_info->video_latency); 580 set_audio_latency(audio, audio_info->audio_latency); 581 582 value = 0; 583 set_reg_field_value(value, audio_info->manufacture_id, 584 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 585 MANUFACTURER_ID); 586 587 set_reg_field_value(value, audio_info->product_id, 588 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 589 PRODUCT_ID); 590 591 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 592 value); 593 594 value = 0; 595 596 /*get display name string length */ 597 while (audio_info->display_name[strlen++] != '\0') { 598 if (strlen >= 599 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 600 break; 601 } 602 set_reg_field_value(value, strlen, 603 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 604 SINK_DESCRIPTION_LEN); 605 606 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 607 value); 608 609 /* 610 *write the port ID: 611 *PORT_ID0 = display index 612 *PORT_ID1 = 16bit BDF 613 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 614 */ 615 616 value = 0; 617 618 set_reg_field_value(value, audio_info->port_id[0], 619 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 620 PORT_ID0); 621 622 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 623 624 value = 0; 625 set_reg_field_value(value, audio_info->port_id[1], 626 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 627 PORT_ID1); 628 629 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 630 631 /*write the 18 char monitor string */ 632 633 value = 0; 634 set_reg_field_value(value, audio_info->display_name[0], 635 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 636 DESCRIPTION0); 637 638 set_reg_field_value(value, audio_info->display_name[1], 639 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 640 DESCRIPTION1); 641 642 set_reg_field_value(value, audio_info->display_name[2], 643 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 644 DESCRIPTION2); 645 646 set_reg_field_value(value, audio_info->display_name[3], 647 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 648 DESCRIPTION3); 649 650 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 651 652 value = 0; 653 set_reg_field_value(value, audio_info->display_name[4], 654 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 655 DESCRIPTION4); 656 657 set_reg_field_value(value, audio_info->display_name[5], 658 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 659 DESCRIPTION5); 660 661 set_reg_field_value(value, audio_info->display_name[6], 662 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 663 DESCRIPTION6); 664 665 set_reg_field_value(value, audio_info->display_name[7], 666 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 667 DESCRIPTION7); 668 669 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 670 671 value = 0; 672 set_reg_field_value(value, audio_info->display_name[8], 673 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 674 DESCRIPTION8); 675 676 set_reg_field_value(value, audio_info->display_name[9], 677 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 678 DESCRIPTION9); 679 680 set_reg_field_value(value, audio_info->display_name[10], 681 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 682 DESCRIPTION10); 683 684 set_reg_field_value(value, audio_info->display_name[11], 685 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 686 DESCRIPTION11); 687 688 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 689 690 value = 0; 691 set_reg_field_value(value, audio_info->display_name[12], 692 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 693 DESCRIPTION12); 694 695 set_reg_field_value(value, audio_info->display_name[13], 696 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 697 DESCRIPTION13); 698 699 set_reg_field_value(value, audio_info->display_name[14], 700 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 701 DESCRIPTION14); 702 703 set_reg_field_value(value, audio_info->display_name[15], 704 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 705 DESCRIPTION15); 706 707 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 708 709 value = 0; 710 set_reg_field_value(value, audio_info->display_name[16], 711 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 712 DESCRIPTION16); 713 714 set_reg_field_value(value, audio_info->display_name[17], 715 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 716 DESCRIPTION17); 717 718 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 719 } 720 721 /* 722 * todo: wall clk related functionality probably belong to clock_src. 723 */ 724 725 /* search pixel clock value for Azalia HDMI Audio */ 726 static void get_azalia_clock_info_hdmi( 727 uint32_t crtc_pixel_clock_in_khz, 728 uint32_t actual_pixel_clock_in_khz, 729 struct azalia_clock_info *azalia_clock_info) 730 { 731 /* audio_dto_phase= 24 * 10,000; 732 * 24MHz in [100Hz] units */ 733 azalia_clock_info->audio_dto_phase = 734 24 * 10000; 735 736 /* audio_dto_module = PCLKFrequency * 10,000; 737 * [khz] -> [100Hz] */ 738 azalia_clock_info->audio_dto_module = 739 actual_pixel_clock_in_khz * 10; 740 } 741 742 static void get_azalia_clock_info_dp( 743 uint32_t requested_pixel_clock_in_khz, 744 const struct audio_pll_info *pll_info, 745 struct azalia_clock_info *azalia_clock_info) 746 { 747 /* Reported dpDtoSourceClockInkhz value for 748 * DCE8 already adjusted for SS, do not need any 749 * adjustment here anymore 750 */ 751 752 /*audio_dto_phase = 24 * 10,000; 753 * 24MHz in [100Hz] units */ 754 azalia_clock_info->audio_dto_phase = 24 * 10000; 755 756 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 757 * [khz] ->[100Hz] */ 758 azalia_clock_info->audio_dto_module = 759 pll_info->dp_dto_source_clock_in_khz * 10; 760 } 761 762 void dce_aud_wall_dto_setup( 763 struct audio *audio, 764 enum signal_type signal, 765 const struct audio_crtc_info *crtc_info, 766 const struct audio_pll_info *pll_info) 767 { 768 struct dce_audio *aud = DCE_AUD(audio); 769 770 struct azalia_clock_info clock_info = { 0 }; 771 772 if (dc_is_hdmi_signal(signal)) { 773 uint32_t src_sel; 774 775 /*DTO0 Programming goal: 776 -generate 24MHz, 128*Fs from 24MHz 777 -use DTO0 when an active HDMI port is connected 778 (optionally a DP is connected) */ 779 780 /* calculate DTO settings */ 781 get_azalia_clock_info_hdmi( 782 crtc_info->requested_pixel_clock, 783 crtc_info->calculated_pixel_clock, 784 &clock_info); 785 786 dm_logger_write(audio->ctx->logger, LOG_HW_AUDIO,\ 787 "\n%s:Input::requested_pixel_clock = %d"\ 788 "calculated_pixel_clock =%d\n"\ 789 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 790 crtc_info->requested_pixel_clock,\ 791 crtc_info->calculated_pixel_clock,\ 792 clock_info.audio_dto_module,\ 793 clock_info.audio_dto_phase); 794 795 /* On TN/SI, Program DTO source select and DTO select before 796 programming DTO modulo and DTO phase. These bits must be 797 programmed first, otherwise there will be no HDMI audio at boot 798 up. This is a HW sequence change (different from old ASICs). 799 Caution when changing this programming sequence. 800 801 HDMI enabled, using DTO0 802 program master CRTC for DTO0 */ 803 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 804 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 805 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 806 DCCG_AUDIO_DTO_SEL, 0); 807 808 /* module */ 809 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 810 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 811 812 /* phase */ 813 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 814 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 815 } else { 816 /*DTO1 Programming goal: 817 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 818 -default is to used DTO1, and switch to DTO0 when an audio 819 master HDMI port is connected 820 -use as default for DP 821 822 calculate DTO settings */ 823 get_azalia_clock_info_dp( 824 crtc_info->requested_pixel_clock, 825 pll_info, 826 &clock_info); 827 828 /* Program DTO select before programming DTO modulo and DTO 829 phase. default to use DTO1 */ 830 831 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 832 DCCG_AUDIO_DTO_SEL, 1); 833 834 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 835 DCCG_AUDIO_DTO_SEL, 1); 836 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 837 * Select 512fs for DP TODO: web register definition 838 * does not match register header file 839 * DCE11 version it's commented out while DCE8 it's set to 1 840 */ 841 842 /* module */ 843 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 844 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 845 846 /* phase */ 847 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 848 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 849 850 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 851 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 852 853 } 854 } 855 856 static bool dce_aud_endpoint_valid(struct audio *audio) 857 { 858 uint32_t value; 859 uint32_t port_connectivity; 860 861 value = AZ_REG_READ( 862 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 863 864 port_connectivity = get_reg_field_value(value, 865 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 866 PORT_CONNECTIVITY); 867 868 return !(port_connectivity == 1); 869 } 870 871 /* initialize HW state */ 872 void dce_aud_hw_init( 873 struct audio *audio) 874 { 875 uint32_t value; 876 struct dce_audio *aud = DCE_AUD(audio); 877 878 /* we only need to program the following registers once, so we only do 879 it for the inst 0*/ 880 if (audio->inst != 0) 881 return; 882 883 /* Suport R5 - 32khz 884 * Suport R6 - 44.1khz 885 * Suport R7 - 48khz 886 */ 887 /*disable clock gating before write to endpoint register*/ 888 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 889 set_reg_field_value(value, 1, 890 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 891 CLOCK_GATING_DISABLE); 892 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 893 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 894 AUDIO_RATE_CAPABILITIES, 0x70); 895 896 /*Keep alive bit to verify HW block in BU. */ 897 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 898 CLKSTOP, 1, 899 EPSS, 1); 900 } 901 902 static const struct audio_funcs funcs = { 903 .endpoint_valid = dce_aud_endpoint_valid, 904 .hw_init = dce_aud_hw_init, 905 .wall_dto_setup = dce_aud_wall_dto_setup, 906 .az_enable = dce_aud_az_enable, 907 .az_disable = dce_aud_az_disable, 908 .az_configure = dce_aud_az_configure, 909 .destroy = dce_aud_destroy, 910 }; 911 912 void dce_aud_destroy(struct audio **audio) 913 { 914 struct dce_audio *aud = DCE_AUD(*audio); 915 916 kfree(aud); 917 *audio = NULL; 918 } 919 920 struct audio *dce_audio_create( 921 struct dc_context *ctx, 922 unsigned int inst, 923 const struct dce_audio_registers *reg, 924 const struct dce_audio_shift *shifts, 925 const struct dce_aduio_mask *masks 926 ) 927 { 928 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 929 930 if (audio == NULL) { 931 ASSERT_CRITICAL(audio); 932 return NULL; 933 } 934 935 audio->base.ctx = ctx; 936 audio->base.inst = inst; 937 audio->base.funcs = &funcs; 938 939 audio->regs = reg; 940 audio->shifts = shifts; 941 audio->masks = masks; 942 943 return &audio->base; 944 } 945 946