1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "reg_helper.h" 29 #include "dce_audio.h" 30 #include "dce/dce_11_0_d.h" 31 #include "dce/dce_11_0_sh_mask.h" 32 33 #define DCE_AUD(audio)\ 34 container_of(audio, struct dce_audio, base) 35 36 #define CTX \ 37 aud->base.ctx 38 39 #define DC_LOGGER_INIT() 40 41 #define REG(reg)\ 42 (aud->regs->reg) 43 44 #undef FN 45 #define FN(reg_name, field_name) \ 46 aud->shifts->field_name, aud->masks->field_name 47 48 #define IX_REG(reg)\ 49 ix ## reg 50 51 #define AZ_REG_READ(reg_name) \ 52 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 53 54 #define AZ_REG_WRITE(reg_name, value) \ 55 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 56 57 static void write_indirect_azalia_reg(struct audio *audio, 58 uint32_t reg_index, 59 uint32_t reg_data) 60 { 61 struct dce_audio *aud = DCE_AUD(audio); 62 63 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 64 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 65 AZALIA_ENDPOINT_REG_INDEX, reg_index); 66 67 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 68 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 69 AZALIA_ENDPOINT_REG_DATA, reg_data); 70 } 71 72 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 73 { 74 struct dce_audio *aud = DCE_AUD(audio); 75 76 uint32_t value = 0; 77 78 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 79 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 80 AZALIA_ENDPOINT_REG_INDEX, reg_index); 81 82 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 83 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 84 85 return value; 86 } 87 88 static bool is_audio_format_supported( 89 const struct audio_info *audio_info, 90 enum audio_format_code audio_format_code, 91 uint32_t *format_index) 92 { 93 uint32_t index; 94 uint32_t max_channe_index = 0; 95 bool found = false; 96 97 if (audio_info == NULL) 98 return found; 99 100 /* pass through whole array */ 101 for (index = 0; index < audio_info->mode_count; index++) { 102 if (audio_info->modes[index].format_code == audio_format_code) { 103 if (found) { 104 /* format has multiply entries, choose one with 105 * highst number of channels */ 106 if (audio_info->modes[index].channel_count > 107 audio_info->modes[max_channe_index].channel_count) { 108 max_channe_index = index; 109 } 110 } else { 111 /* format found, save it's index */ 112 found = true; 113 max_channe_index = index; 114 } 115 } 116 } 117 118 /* return index */ 119 if (found && format_index != NULL) 120 *format_index = max_channe_index; 121 122 return found; 123 } 124 125 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 126 static void check_audio_bandwidth_hdmi( 127 const struct audio_crtc_info *crtc_info, 128 uint32_t channel_count, 129 union audio_sample_rates *sample_rates) 130 { 131 uint32_t samples; 132 uint32_t h_blank; 133 bool limit_freq_to_48_khz = false; 134 bool limit_freq_to_88_2_khz = false; 135 bool limit_freq_to_96_khz = false; 136 bool limit_freq_to_174_4_khz = false; 137 if (!crtc_info) 138 return; 139 140 /* For two channels supported return whatever sink support,unmodified*/ 141 if (channel_count > 2) { 142 143 /* Based on HDMI spec 1.3 Table 7.5 */ 144 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 145 (crtc_info->v_active <= 576) && 146 !(crtc_info->interlaced) && 147 !(crtc_info->pixel_repetition == 2 || 148 crtc_info->pixel_repetition == 4)) { 149 limit_freq_to_48_khz = true; 150 151 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 152 (crtc_info->v_active <= 576) && 153 (crtc_info->interlaced) && 154 (crtc_info->pixel_repetition == 2)) { 155 limit_freq_to_88_2_khz = true; 156 157 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) && 158 (crtc_info->v_active <= 576) && 159 !(crtc_info->interlaced)) { 160 limit_freq_to_174_4_khz = true; 161 } 162 } 163 164 /* Also do some calculation for the available Audio Bandwidth for the 165 * 8 ch (i.e. for the Layout 1 => ch > 2) 166 */ 167 h_blank = crtc_info->h_total - crtc_info->h_active; 168 169 if (crtc_info->pixel_repetition) 170 h_blank *= crtc_info->pixel_repetition; 171 172 /*based on HDMI spec 1.3 Table 7.5 */ 173 h_blank -= 58; 174 /*for Control Period */ 175 h_blank -= 16; 176 177 samples = h_blank * 10; 178 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 179 * of Audio samples per line multiplied by 10 - Layout 1) 180 */ 181 samples /= 32; 182 samples *= crtc_info->v_active; 183 /*Number of samples multiplied by 10, per second */ 184 samples *= crtc_info->refresh_rate; 185 /*Number of Audio samples per second */ 186 samples /= 10; 187 188 /* @todo do it after deep color is implemented 189 * 8xx - deep color bandwidth scaling 190 * Extra bandwidth is avaliable in deep color b/c link runs faster than 191 * pixel rate. This has the effect of allowing more tmds characters to 192 * be transmitted during blank 193 */ 194 195 switch (crtc_info->color_depth) { 196 case COLOR_DEPTH_888: 197 samples *= 4; 198 break; 199 case COLOR_DEPTH_101010: 200 samples *= 5; 201 break; 202 case COLOR_DEPTH_121212: 203 samples *= 6; 204 break; 205 default: 206 samples *= 4; 207 break; 208 } 209 210 samples /= 4; 211 212 /*check limitation*/ 213 if (samples < 88200) 214 limit_freq_to_48_khz = true; 215 else if (samples < 96000) 216 limit_freq_to_88_2_khz = true; 217 else if (samples < 176400) 218 limit_freq_to_96_khz = true; 219 else if (samples < 192000) 220 limit_freq_to_174_4_khz = true; 221 222 if (sample_rates != NULL) { 223 /* limit frequencies */ 224 if (limit_freq_to_174_4_khz) 225 sample_rates->rate.RATE_192 = 0; 226 227 if (limit_freq_to_96_khz) { 228 sample_rates->rate.RATE_192 = 0; 229 sample_rates->rate.RATE_176_4 = 0; 230 } 231 if (limit_freq_to_88_2_khz) { 232 sample_rates->rate.RATE_192 = 0; 233 sample_rates->rate.RATE_176_4 = 0; 234 sample_rates->rate.RATE_96 = 0; 235 } 236 if (limit_freq_to_48_khz) { 237 sample_rates->rate.RATE_192 = 0; 238 sample_rates->rate.RATE_176_4 = 0; 239 sample_rates->rate.RATE_96 = 0; 240 sample_rates->rate.RATE_88_2 = 0; 241 } 242 } 243 } 244 245 /*For DP SST, calculate if specified sample rates can fit into a given timing */ 246 static void check_audio_bandwidth_dpsst( 247 const struct audio_crtc_info *crtc_info, 248 uint32_t channel_count, 249 union audio_sample_rates *sample_rates) 250 { 251 /* do nothing */ 252 } 253 254 /*For DP MST, calculate if specified sample rates can fit into a given timing */ 255 static void check_audio_bandwidth_dpmst( 256 const struct audio_crtc_info *crtc_info, 257 uint32_t channel_count, 258 union audio_sample_rates *sample_rates) 259 { 260 /* do nothing */ 261 } 262 263 static void check_audio_bandwidth( 264 const struct audio_crtc_info *crtc_info, 265 uint32_t channel_count, 266 enum signal_type signal, 267 union audio_sample_rates *sample_rates) 268 { 269 switch (signal) { 270 case SIGNAL_TYPE_HDMI_TYPE_A: 271 check_audio_bandwidth_hdmi( 272 crtc_info, channel_count, sample_rates); 273 break; 274 case SIGNAL_TYPE_EDP: 275 case SIGNAL_TYPE_DISPLAY_PORT: 276 check_audio_bandwidth_dpsst( 277 crtc_info, channel_count, sample_rates); 278 break; 279 case SIGNAL_TYPE_DISPLAY_PORT_MST: 280 check_audio_bandwidth_dpmst( 281 crtc_info, channel_count, sample_rates); 282 break; 283 default: 284 break; 285 } 286 } 287 288 /* expose/not expose HBR capability to Audio driver */ 289 static void set_high_bit_rate_capable( 290 struct audio *audio, 291 bool capable) 292 { 293 uint32_t value = 0; 294 295 /* set high bit rate audio capable*/ 296 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 297 298 set_reg_field_value(value, capable, 299 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 300 HBR_CAPABLE); 301 302 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 303 } 304 305 /* set video latency in in ms/2+1 */ 306 static void set_video_latency( 307 struct audio *audio, 308 int latency_in_ms) 309 { 310 uint32_t value = 0; 311 312 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 313 return; 314 315 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 316 317 set_reg_field_value(value, latency_in_ms, 318 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 319 VIDEO_LIPSYNC); 320 321 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 322 value); 323 } 324 325 /* set audio latency in in ms/2+1 */ 326 static void set_audio_latency( 327 struct audio *audio, 328 int latency_in_ms) 329 { 330 uint32_t value = 0; 331 332 if (latency_in_ms < 0) 333 latency_in_ms = 0; 334 335 if (latency_in_ms > 255) 336 latency_in_ms = 255; 337 338 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 339 340 set_reg_field_value(value, latency_in_ms, 341 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 342 AUDIO_LIPSYNC); 343 344 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 345 value); 346 } 347 348 void dce_aud_az_enable(struct audio *audio) 349 { 350 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 351 DC_LOGGER_INIT(); 352 353 set_reg_field_value(value, 1, 354 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 355 CLOCK_GATING_DISABLE); 356 set_reg_field_value(value, 1, 357 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 358 AUDIO_ENABLED); 359 360 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 361 set_reg_field_value(value, 0, 362 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 363 CLOCK_GATING_DISABLE); 364 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 365 366 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", 367 audio->inst, value); 368 } 369 370 void dce_aud_az_disable(struct audio *audio) 371 { 372 uint32_t value; 373 DC_LOGGER_INIT(); 374 375 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 376 set_reg_field_value(value, 1, 377 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 378 CLOCK_GATING_DISABLE); 379 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 380 381 set_reg_field_value(value, 0, 382 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 383 AUDIO_ENABLED); 384 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 385 386 set_reg_field_value(value, 0, 387 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 388 CLOCK_GATING_DISABLE); 389 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 390 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 391 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", 392 audio->inst, value); 393 } 394 395 void dce_aud_az_configure( 396 struct audio *audio, 397 enum signal_type signal, 398 const struct audio_crtc_info *crtc_info, 399 const struct audio_info *audio_info) 400 { 401 struct dce_audio *aud = DCE_AUD(audio); 402 403 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 404 uint32_t value; 405 uint32_t field = 0; 406 enum audio_format_code audio_format_code; 407 uint32_t format_index; 408 uint32_t index; 409 bool is_ac3_supported = false; 410 union audio_sample_rates sample_rate; 411 uint32_t strlen = 0; 412 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 413 set_reg_field_value(value, 1, 414 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 415 CLOCK_GATING_DISABLE); 416 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 417 418 /* Speaker Allocation */ 419 /* 420 uint32_t value; 421 uint32_t field = 0;*/ 422 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 423 424 set_reg_field_value(value, 425 speakers, 426 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 427 SPEAKER_ALLOCATION); 428 429 /* LFE_PLAYBACK_LEVEL = LFEPBL 430 * LFEPBL = 0 : Unknown or refer to other information 431 * LFEPBL = 1 : 0dB playback 432 * LFEPBL = 2 : +10dB playback 433 * LFE_BL = 3 : Reserved 434 */ 435 set_reg_field_value(value, 436 0, 437 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 438 LFE_PLAYBACK_LEVEL); 439 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 440 * why are we writing to it? DCE8 does not write this */ 441 442 443 set_reg_field_value(value, 444 0, 445 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 446 HDMI_CONNECTION); 447 448 set_reg_field_value(value, 449 0, 450 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 451 DP_CONNECTION); 452 453 field = get_reg_field_value(value, 454 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 455 EXTRA_CONNECTION_INFO); 456 457 field &= ~0x1; 458 459 set_reg_field_value(value, 460 field, 461 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 462 EXTRA_CONNECTION_INFO); 463 464 /* set audio for output signal */ 465 switch (signal) { 466 case SIGNAL_TYPE_HDMI_TYPE_A: 467 set_reg_field_value(value, 468 1, 469 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 470 HDMI_CONNECTION); 471 472 break; 473 474 case SIGNAL_TYPE_EDP: 475 case SIGNAL_TYPE_DISPLAY_PORT: 476 case SIGNAL_TYPE_DISPLAY_PORT_MST: 477 set_reg_field_value(value, 478 1, 479 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 480 DP_CONNECTION); 481 break; 482 default: 483 BREAK_TO_DEBUGGER(); 484 break; 485 } 486 487 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 488 489 /* Audio Descriptors */ 490 /* pass through all formats */ 491 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 492 format_index++) { 493 audio_format_code = 494 (AUDIO_FORMAT_CODE_FIRST + format_index); 495 496 /* those are unsupported, skip programming */ 497 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 498 audio_format_code == AUDIO_FORMAT_CODE_DST) 499 continue; 500 501 value = 0; 502 503 /* check if supported */ 504 if (is_audio_format_supported( 505 audio_info, audio_format_code, &index)) { 506 const struct audio_mode *audio_mode = 507 &audio_info->modes[index]; 508 union audio_sample_rates sample_rates = 509 audio_mode->sample_rates; 510 uint8_t byte2 = audio_mode->max_bit_rate; 511 uint8_t channel_count = audio_mode->channel_count; 512 513 /* adjust specific properties */ 514 switch (audio_format_code) { 515 case AUDIO_FORMAT_CODE_LINEARPCM: { 516 517 check_audio_bandwidth( 518 crtc_info, 519 channel_count, 520 signal, 521 &sample_rates); 522 523 byte2 = audio_mode->sample_size; 524 525 set_reg_field_value(value, 526 sample_rates.all, 527 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 528 SUPPORTED_FREQUENCIES_STEREO); 529 } 530 break; 531 case AUDIO_FORMAT_CODE_AC3: 532 is_ac3_supported = true; 533 break; 534 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 535 case AUDIO_FORMAT_CODE_DTS_HD: 536 case AUDIO_FORMAT_CODE_MAT_MLP: 537 case AUDIO_FORMAT_CODE_DST: 538 case AUDIO_FORMAT_CODE_WMAPRO: 539 byte2 = audio_mode->vendor_specific; 540 break; 541 default: 542 break; 543 } 544 545 /* fill audio format data */ 546 set_reg_field_value(value, 547 channel_count - 1, 548 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 549 MAX_CHANNELS); 550 551 set_reg_field_value(value, 552 sample_rates.all, 553 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 554 SUPPORTED_FREQUENCIES); 555 556 set_reg_field_value(value, 557 byte2, 558 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 559 DESCRIPTOR_BYTE_2); 560 } /* if */ 561 562 AZ_REG_WRITE( 563 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 564 value); 565 } /* for */ 566 567 if (is_ac3_supported) 568 /* todo: this reg global. why program global register? */ 569 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 570 0x05); 571 572 /* check for 192khz/8-Ch support for HBR requirements */ 573 sample_rate.all = 0; 574 sample_rate.rate.RATE_192 = 1; 575 576 check_audio_bandwidth( 577 crtc_info, 578 8, 579 signal, 580 &sample_rate); 581 582 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 583 584 /* Audio and Video Lipsync */ 585 set_video_latency(audio, audio_info->video_latency); 586 set_audio_latency(audio, audio_info->audio_latency); 587 588 value = 0; 589 set_reg_field_value(value, audio_info->manufacture_id, 590 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 591 MANUFACTURER_ID); 592 593 set_reg_field_value(value, audio_info->product_id, 594 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 595 PRODUCT_ID); 596 597 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 598 value); 599 600 value = 0; 601 602 /*get display name string length */ 603 while (audio_info->display_name[strlen++] != '\0') { 604 if (strlen >= 605 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 606 break; 607 } 608 set_reg_field_value(value, strlen, 609 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 610 SINK_DESCRIPTION_LEN); 611 612 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 613 value); 614 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n", 615 audio->inst, value, audio_info->display_name); 616 617 /* 618 *write the port ID: 619 *PORT_ID0 = display index 620 *PORT_ID1 = 16bit BDF 621 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 622 */ 623 624 value = 0; 625 626 set_reg_field_value(value, audio_info->port_id[0], 627 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 628 PORT_ID0); 629 630 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 631 632 value = 0; 633 set_reg_field_value(value, audio_info->port_id[1], 634 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 635 PORT_ID1); 636 637 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 638 639 /*write the 18 char monitor string */ 640 641 value = 0; 642 set_reg_field_value(value, audio_info->display_name[0], 643 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 644 DESCRIPTION0); 645 646 set_reg_field_value(value, audio_info->display_name[1], 647 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 648 DESCRIPTION1); 649 650 set_reg_field_value(value, audio_info->display_name[2], 651 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 652 DESCRIPTION2); 653 654 set_reg_field_value(value, audio_info->display_name[3], 655 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 656 DESCRIPTION3); 657 658 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 659 660 value = 0; 661 set_reg_field_value(value, audio_info->display_name[4], 662 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 663 DESCRIPTION4); 664 665 set_reg_field_value(value, audio_info->display_name[5], 666 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 667 DESCRIPTION5); 668 669 set_reg_field_value(value, audio_info->display_name[6], 670 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 671 DESCRIPTION6); 672 673 set_reg_field_value(value, audio_info->display_name[7], 674 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 675 DESCRIPTION7); 676 677 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 678 679 value = 0; 680 set_reg_field_value(value, audio_info->display_name[8], 681 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 682 DESCRIPTION8); 683 684 set_reg_field_value(value, audio_info->display_name[9], 685 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 686 DESCRIPTION9); 687 688 set_reg_field_value(value, audio_info->display_name[10], 689 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 690 DESCRIPTION10); 691 692 set_reg_field_value(value, audio_info->display_name[11], 693 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 694 DESCRIPTION11); 695 696 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 697 698 value = 0; 699 set_reg_field_value(value, audio_info->display_name[12], 700 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 701 DESCRIPTION12); 702 703 set_reg_field_value(value, audio_info->display_name[13], 704 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 705 DESCRIPTION13); 706 707 set_reg_field_value(value, audio_info->display_name[14], 708 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 709 DESCRIPTION14); 710 711 set_reg_field_value(value, audio_info->display_name[15], 712 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 713 DESCRIPTION15); 714 715 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 716 717 value = 0; 718 set_reg_field_value(value, audio_info->display_name[16], 719 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 720 DESCRIPTION16); 721 722 set_reg_field_value(value, audio_info->display_name[17], 723 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 724 DESCRIPTION17); 725 726 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 727 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 728 set_reg_field_value(value, 0, 729 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 730 CLOCK_GATING_DISABLE); 731 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 732 } 733 734 /* 735 * todo: wall clk related functionality probably belong to clock_src. 736 */ 737 738 /* search pixel clock value for Azalia HDMI Audio */ 739 static void get_azalia_clock_info_hdmi( 740 uint32_t crtc_pixel_clock_100hz, 741 uint32_t actual_pixel_clock_100Hz, 742 struct azalia_clock_info *azalia_clock_info) 743 { 744 /* audio_dto_phase= 24 * 10,000; 745 * 24MHz in [100Hz] units */ 746 azalia_clock_info->audio_dto_phase = 747 24 * 10000; 748 749 /* audio_dto_module = PCLKFrequency * 10,000; 750 * [khz] -> [100Hz] */ 751 azalia_clock_info->audio_dto_module = 752 actual_pixel_clock_100Hz; 753 } 754 755 static void get_azalia_clock_info_dp( 756 uint32_t requested_pixel_clock_100Hz, 757 const struct audio_pll_info *pll_info, 758 struct azalia_clock_info *azalia_clock_info) 759 { 760 /* Reported dpDtoSourceClockInkhz value for 761 * DCE8 already adjusted for SS, do not need any 762 * adjustment here anymore 763 */ 764 765 /*audio_dto_phase = 24 * 10,000; 766 * 24MHz in [100Hz] units */ 767 azalia_clock_info->audio_dto_phase = 24 * 10000; 768 769 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 770 * [khz] ->[100Hz] */ 771 azalia_clock_info->audio_dto_module = 772 pll_info->dp_dto_source_clock_in_khz * 10; 773 } 774 775 void dce_aud_wall_dto_setup( 776 struct audio *audio, 777 enum signal_type signal, 778 const struct audio_crtc_info *crtc_info, 779 const struct audio_pll_info *pll_info) 780 { 781 struct dce_audio *aud = DCE_AUD(audio); 782 783 struct azalia_clock_info clock_info = { 0 }; 784 785 if (dc_is_hdmi_tmds_signal(signal)) { 786 uint32_t src_sel; 787 788 /*DTO0 Programming goal: 789 -generate 24MHz, 128*Fs from 24MHz 790 -use DTO0 when an active HDMI port is connected 791 (optionally a DP is connected) */ 792 793 /* calculate DTO settings */ 794 get_azalia_clock_info_hdmi( 795 crtc_info->requested_pixel_clock_100Hz, 796 crtc_info->calculated_pixel_clock_100Hz, 797 &clock_info); 798 799 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 800 "calculated_pixel_clock_100Hz =%d\n"\ 801 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 802 crtc_info->requested_pixel_clock_100Hz,\ 803 crtc_info->calculated_pixel_clock_100Hz,\ 804 clock_info.audio_dto_module,\ 805 clock_info.audio_dto_phase); 806 807 /* On TN/SI, Program DTO source select and DTO select before 808 programming DTO modulo and DTO phase. These bits must be 809 programmed first, otherwise there will be no HDMI audio at boot 810 up. This is a HW sequence change (different from old ASICs). 811 Caution when changing this programming sequence. 812 813 HDMI enabled, using DTO0 814 program master CRTC for DTO0 */ 815 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 816 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 817 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 818 DCCG_AUDIO_DTO_SEL, 0); 819 820 /* module */ 821 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 822 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 823 824 /* phase */ 825 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 826 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 827 } else { 828 /*DTO1 Programming goal: 829 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 830 -default is to used DTO1, and switch to DTO0 when an audio 831 master HDMI port is connected 832 -use as default for DP 833 834 calculate DTO settings */ 835 get_azalia_clock_info_dp( 836 crtc_info->requested_pixel_clock_100Hz, 837 pll_info, 838 &clock_info); 839 840 /* Program DTO select before programming DTO modulo and DTO 841 phase. default to use DTO1 */ 842 843 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 844 DCCG_AUDIO_DTO_SEL, 1); 845 846 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 847 * Select 512fs for DP TODO: web register definition 848 * does not match register header file 849 * DCE11 version it's commented out while DCE8 it's set to 1 850 */ 851 852 /* module */ 853 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 854 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 855 856 /* phase */ 857 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 858 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 859 860 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 861 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 862 863 } 864 } 865 866 #if defined(CONFIG_DRM_AMD_DC_SI) 867 static void dce60_aud_wall_dto_setup( 868 struct audio *audio, 869 enum signal_type signal, 870 const struct audio_crtc_info *crtc_info, 871 const struct audio_pll_info *pll_info) 872 { 873 struct dce_audio *aud = DCE_AUD(audio); 874 875 struct azalia_clock_info clock_info = { 0 }; 876 877 if (dc_is_hdmi_signal(signal)) { 878 uint32_t src_sel; 879 880 /*DTO0 Programming goal: 881 -generate 24MHz, 128*Fs from 24MHz 882 -use DTO0 when an active HDMI port is connected 883 (optionally a DP is connected) */ 884 885 /* calculate DTO settings */ 886 get_azalia_clock_info_hdmi( 887 crtc_info->requested_pixel_clock_100Hz, 888 crtc_info->calculated_pixel_clock_100Hz, 889 &clock_info); 890 891 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 892 "calculated_pixel_clock_100Hz =%d\n"\ 893 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 894 crtc_info->requested_pixel_clock_100Hz,\ 895 crtc_info->calculated_pixel_clock_100Hz,\ 896 clock_info.audio_dto_module,\ 897 clock_info.audio_dto_phase); 898 899 /* On TN/SI, Program DTO source select and DTO select before 900 programming DTO modulo and DTO phase. These bits must be 901 programmed first, otherwise there will be no HDMI audio at boot 902 up. This is a HW sequence change (different from old ASICs). 903 Caution when changing this programming sequence. 904 905 HDMI enabled, using DTO0 906 program master CRTC for DTO0 */ 907 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 908 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 909 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 910 DCCG_AUDIO_DTO_SEL, 0); 911 912 /* module */ 913 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 914 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 915 916 /* phase */ 917 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 918 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 919 } else { 920 /*DTO1 Programming goal: 921 -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs) 922 -default is to used DTO1, and switch to DTO0 when an audio 923 master HDMI port is connected 924 -use as default for DP 925 926 calculate DTO settings */ 927 get_azalia_clock_info_dp( 928 crtc_info->requested_pixel_clock_100Hz, 929 pll_info, 930 &clock_info); 931 932 /* Program DTO select before programming DTO modulo and DTO 933 phase. default to use DTO1 */ 934 935 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 936 DCCG_AUDIO_DTO_SEL, 1); 937 938 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 939 * Cannot select 512fs for DP 940 * 941 * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask 942 */ 943 944 /* module */ 945 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 946 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 947 948 /* phase */ 949 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 950 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 951 952 /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */ 953 954 } 955 } 956 #endif 957 958 static bool dce_aud_endpoint_valid(struct audio *audio) 959 { 960 uint32_t value; 961 uint32_t port_connectivity; 962 963 value = AZ_REG_READ( 964 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 965 966 port_connectivity = get_reg_field_value(value, 967 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 968 PORT_CONNECTIVITY); 969 970 return !(port_connectivity == 1); 971 } 972 973 /* initialize HW state */ 974 void dce_aud_hw_init( 975 struct audio *audio) 976 { 977 uint32_t value; 978 struct dce_audio *aud = DCE_AUD(audio); 979 980 /* we only need to program the following registers once, so we only do 981 it for the inst 0*/ 982 if (audio->inst != 0) 983 return; 984 985 /* Suport R5 - 32khz 986 * Suport R6 - 44.1khz 987 * Suport R7 - 48khz 988 */ 989 /*disable clock gating before write to endpoint register*/ 990 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 991 set_reg_field_value(value, 1, 992 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 993 CLOCK_GATING_DISABLE); 994 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 995 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 996 AUDIO_RATE_CAPABILITIES, 0x70); 997 998 /*Keep alive bit to verify HW block in BU. */ 999 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 1000 CLKSTOP, 1, 1001 EPSS, 1); 1002 set_reg_field_value(value, 0, 1003 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1004 CLOCK_GATING_DISABLE); 1005 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1006 } 1007 1008 static const struct audio_funcs funcs = { 1009 .endpoint_valid = dce_aud_endpoint_valid, 1010 .hw_init = dce_aud_hw_init, 1011 .wall_dto_setup = dce_aud_wall_dto_setup, 1012 .az_enable = dce_aud_az_enable, 1013 .az_disable = dce_aud_az_disable, 1014 .az_configure = dce_aud_az_configure, 1015 .destroy = dce_aud_destroy, 1016 }; 1017 1018 #if defined(CONFIG_DRM_AMD_DC_SI) 1019 static const struct audio_funcs dce60_funcs = { 1020 .endpoint_valid = dce_aud_endpoint_valid, 1021 .hw_init = dce_aud_hw_init, 1022 .wall_dto_setup = dce60_aud_wall_dto_setup, 1023 .az_enable = dce_aud_az_enable, 1024 .az_disable = dce_aud_az_disable, 1025 .az_configure = dce_aud_az_configure, 1026 .destroy = dce_aud_destroy, 1027 }; 1028 #endif 1029 1030 void dce_aud_destroy(struct audio **audio) 1031 { 1032 struct dce_audio *aud = DCE_AUD(*audio); 1033 1034 kfree(aud); 1035 *audio = NULL; 1036 } 1037 1038 struct audio *dce_audio_create( 1039 struct dc_context *ctx, 1040 unsigned int inst, 1041 const struct dce_audio_registers *reg, 1042 const struct dce_audio_shift *shifts, 1043 const struct dce_audio_mask *masks 1044 ) 1045 { 1046 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 1047 1048 if (audio == NULL) { 1049 ASSERT_CRITICAL(audio); 1050 return NULL; 1051 } 1052 1053 audio->base.ctx = ctx; 1054 audio->base.inst = inst; 1055 audio->base.funcs = &funcs; 1056 1057 audio->regs = reg; 1058 audio->shifts = shifts; 1059 audio->masks = masks; 1060 return &audio->base; 1061 } 1062 1063 #if defined(CONFIG_DRM_AMD_DC_SI) 1064 struct audio *dce60_audio_create( 1065 struct dc_context *ctx, 1066 unsigned int inst, 1067 const struct dce_audio_registers *reg, 1068 const struct dce_audio_shift *shifts, 1069 const struct dce_audio_mask *masks 1070 ) 1071 { 1072 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 1073 1074 if (audio == NULL) { 1075 ASSERT_CRITICAL(audio); 1076 return NULL; 1077 } 1078 1079 audio->base.ctx = ctx; 1080 audio->base.inst = inst; 1081 audio->base.funcs = &dce60_funcs; 1082 1083 audio->regs = reg; 1084 audio->shifts = shifts; 1085 audio->masks = masks; 1086 return &audio->base; 1087 } 1088 #endif 1089