1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dce_audio.h" 28 #include "dce/dce_11_0_d.h" 29 #include "dce/dce_11_0_sh_mask.h" 30 31 #define DCE_AUD(audio)\ 32 container_of(audio, struct dce_audio, base) 33 34 #define CTX \ 35 aud->base.ctx 36 #define REG(reg)\ 37 (aud->regs->reg) 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 aud->shifts->field_name, aud->masks->field_name 42 43 #define IX_REG(reg)\ 44 ix ## reg 45 46 #define AZ_REG_READ(reg_name) \ 47 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 48 49 #define AZ_REG_WRITE(reg_name, value) \ 50 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 51 52 static void write_indirect_azalia_reg(struct audio *audio, 53 uint32_t reg_index, 54 uint32_t reg_data) 55 { 56 struct dce_audio *aud = DCE_AUD(audio); 57 58 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 59 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 60 AZALIA_ENDPOINT_REG_INDEX, reg_index); 61 62 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 63 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 64 AZALIA_ENDPOINT_REG_DATA, reg_data); 65 66 dm_logger_write(CTX->logger, LOG_HW_AUDIO, 67 "AUDIO:write_indirect_azalia_reg: index: %u data: %u\n", 68 reg_index, reg_data); 69 } 70 71 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 72 { 73 struct dce_audio *aud = DCE_AUD(audio); 74 75 uint32_t value = 0; 76 77 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 78 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 79 AZALIA_ENDPOINT_REG_INDEX, reg_index); 80 81 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 82 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 83 84 dm_logger_write(CTX->logger, LOG_HW_AUDIO, 85 "AUDIO:read_indirect_azalia_reg: index: %u data: %u\n", 86 reg_index, value); 87 88 return value; 89 } 90 91 static bool is_audio_format_supported( 92 const struct audio_info *audio_info, 93 enum audio_format_code audio_format_code, 94 uint32_t *format_index) 95 { 96 uint32_t index; 97 uint32_t max_channe_index = 0; 98 bool found = false; 99 100 if (audio_info == NULL) 101 return found; 102 103 /* pass through whole array */ 104 for (index = 0; index < audio_info->mode_count; index++) { 105 if (audio_info->modes[index].format_code == audio_format_code) { 106 if (found) { 107 /* format has multiply entries, choose one with 108 * highst number of channels */ 109 if (audio_info->modes[index].channel_count > 110 audio_info->modes[max_channe_index].channel_count) { 111 max_channe_index = index; 112 } 113 } else { 114 /* format found, save it's index */ 115 found = true; 116 max_channe_index = index; 117 } 118 } 119 } 120 121 /* return index */ 122 if (found && format_index != NULL) 123 *format_index = max_channe_index; 124 125 return found; 126 } 127 128 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 129 static void check_audio_bandwidth_hdmi( 130 const struct audio_crtc_info *crtc_info, 131 uint32_t channel_count, 132 union audio_sample_rates *sample_rates) 133 { 134 uint32_t samples; 135 uint32_t h_blank; 136 bool limit_freq_to_48_khz = false; 137 bool limit_freq_to_88_2_khz = false; 138 bool limit_freq_to_96_khz = false; 139 bool limit_freq_to_174_4_khz = false; 140 141 /* For two channels supported return whatever sink support,unmodified*/ 142 if (channel_count > 2) { 143 144 /* Based on HDMI spec 1.3 Table 7.5 */ 145 if ((crtc_info->requested_pixel_clock <= 27000) && 146 (crtc_info->v_active <= 576) && 147 !(crtc_info->interlaced) && 148 !(crtc_info->pixel_repetition == 2 || 149 crtc_info->pixel_repetition == 4)) { 150 limit_freq_to_48_khz = true; 151 152 } else if ((crtc_info->requested_pixel_clock <= 27000) && 153 (crtc_info->v_active <= 576) && 154 (crtc_info->interlaced) && 155 (crtc_info->pixel_repetition == 2)) { 156 limit_freq_to_88_2_khz = true; 157 158 } else if ((crtc_info->requested_pixel_clock <= 54000) && 159 (crtc_info->v_active <= 576) && 160 !(crtc_info->interlaced)) { 161 limit_freq_to_174_4_khz = true; 162 } 163 } 164 165 /* Also do some calculation for the available Audio Bandwidth for the 166 * 8 ch (i.e. for the Layout 1 => ch > 2) 167 */ 168 h_blank = crtc_info->h_total - crtc_info->h_active; 169 170 if (crtc_info->pixel_repetition) 171 h_blank *= crtc_info->pixel_repetition; 172 173 /*based on HDMI spec 1.3 Table 7.5 */ 174 h_blank -= 58; 175 /*for Control Period */ 176 h_blank -= 16; 177 178 samples = h_blank * 10; 179 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 180 * of Audio samples per line multiplied by 10 - Layout 1) 181 */ 182 samples /= 32; 183 samples *= crtc_info->v_active; 184 /*Number of samples multiplied by 10, per second */ 185 samples *= crtc_info->refresh_rate; 186 /*Number of Audio samples per second */ 187 samples /= 10; 188 189 /* @todo do it after deep color is implemented 190 * 8xx - deep color bandwidth scaling 191 * Extra bandwidth is avaliable in deep color b/c link runs faster than 192 * pixel rate. This has the effect of allowing more tmds characters to 193 * be transmitted during blank 194 */ 195 196 switch (crtc_info->color_depth) { 197 case COLOR_DEPTH_888: 198 samples *= 4; 199 break; 200 case COLOR_DEPTH_101010: 201 samples *= 5; 202 break; 203 case COLOR_DEPTH_121212: 204 samples *= 6; 205 break; 206 default: 207 samples *= 4; 208 break; 209 } 210 211 samples /= 4; 212 213 /*check limitation*/ 214 if (samples < 88200) 215 limit_freq_to_48_khz = true; 216 else if (samples < 96000) 217 limit_freq_to_88_2_khz = true; 218 else if (samples < 176400) 219 limit_freq_to_96_khz = true; 220 else if (samples < 192000) 221 limit_freq_to_174_4_khz = true; 222 223 if (sample_rates != NULL) { 224 /* limit frequencies */ 225 if (limit_freq_to_174_4_khz) 226 sample_rates->rate.RATE_192 = 0; 227 228 if (limit_freq_to_96_khz) { 229 sample_rates->rate.RATE_192 = 0; 230 sample_rates->rate.RATE_176_4 = 0; 231 } 232 if (limit_freq_to_88_2_khz) { 233 sample_rates->rate.RATE_192 = 0; 234 sample_rates->rate.RATE_176_4 = 0; 235 sample_rates->rate.RATE_96 = 0; 236 } 237 if (limit_freq_to_48_khz) { 238 sample_rates->rate.RATE_192 = 0; 239 sample_rates->rate.RATE_176_4 = 0; 240 sample_rates->rate.RATE_96 = 0; 241 sample_rates->rate.RATE_88_2 = 0; 242 } 243 } 244 } 245 246 /*For DP SST, calculate if specified sample rates can fit into a given timing */ 247 static void check_audio_bandwidth_dpsst( 248 const struct audio_crtc_info *crtc_info, 249 uint32_t channel_count, 250 union audio_sample_rates *sample_rates) 251 { 252 /* do nothing */ 253 } 254 255 /*For DP MST, calculate if specified sample rates can fit into a given timing */ 256 static void check_audio_bandwidth_dpmst( 257 const struct audio_crtc_info *crtc_info, 258 uint32_t channel_count, 259 union audio_sample_rates *sample_rates) 260 { 261 /* do nothing */ 262 } 263 264 static void check_audio_bandwidth( 265 const struct audio_crtc_info *crtc_info, 266 uint32_t channel_count, 267 enum signal_type signal, 268 union audio_sample_rates *sample_rates) 269 { 270 switch (signal) { 271 case SIGNAL_TYPE_HDMI_TYPE_A: 272 check_audio_bandwidth_hdmi( 273 crtc_info, channel_count, sample_rates); 274 break; 275 case SIGNAL_TYPE_EDP: 276 case SIGNAL_TYPE_DISPLAY_PORT: 277 check_audio_bandwidth_dpsst( 278 crtc_info, channel_count, sample_rates); 279 break; 280 case SIGNAL_TYPE_DISPLAY_PORT_MST: 281 check_audio_bandwidth_dpmst( 282 crtc_info, channel_count, sample_rates); 283 break; 284 default: 285 break; 286 } 287 } 288 289 /* expose/not expose HBR capability to Audio driver */ 290 static void set_high_bit_rate_capable( 291 struct audio *audio, 292 bool capable) 293 { 294 uint32_t value = 0; 295 296 /* set high bit rate audio capable*/ 297 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 298 299 set_reg_field_value(value, capable, 300 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 301 HBR_CAPABLE); 302 303 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 304 } 305 306 /* set video latency in in ms/2+1 */ 307 static void set_video_latency( 308 struct audio *audio, 309 int latency_in_ms) 310 { 311 uint32_t value = 0; 312 313 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 314 return; 315 316 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 317 318 set_reg_field_value(value, latency_in_ms, 319 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 320 VIDEO_LIPSYNC); 321 322 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 323 value); 324 } 325 326 /* set audio latency in in ms/2+1 */ 327 static void set_audio_latency( 328 struct audio *audio, 329 int latency_in_ms) 330 { 331 uint32_t value = 0; 332 333 if (latency_in_ms < 0) 334 latency_in_ms = 0; 335 336 if (latency_in_ms > 255) 337 latency_in_ms = 255; 338 339 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 340 341 set_reg_field_value(value, latency_in_ms, 342 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 343 AUDIO_LIPSYNC); 344 345 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 346 value); 347 } 348 349 void dce_aud_az_enable(struct audio *audio) 350 { 351 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 352 353 if (get_reg_field_value(value, 354 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 355 AUDIO_ENABLED) != 1) 356 set_reg_field_value(value, 1, 357 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 358 AUDIO_ENABLED); 359 360 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 361 } 362 363 void dce_aud_az_disable(struct audio *audio) 364 { 365 uint32_t value; 366 367 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 368 369 set_reg_field_value(value, 0, 370 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 371 AUDIO_ENABLED); 372 373 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 374 } 375 376 void dce_aud_az_configure( 377 struct audio *audio, 378 enum signal_type signal, 379 const struct audio_crtc_info *crtc_info, 380 const struct audio_info *audio_info) 381 { 382 struct dce_audio *aud = DCE_AUD(audio); 383 384 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 385 uint32_t value; 386 uint32_t field = 0; 387 enum audio_format_code audio_format_code; 388 uint32_t format_index; 389 uint32_t index; 390 bool is_ac3_supported = false; 391 union audio_sample_rates sample_rate; 392 uint32_t strlen = 0; 393 394 /* Speaker Allocation */ 395 /* 396 uint32_t value; 397 uint32_t field = 0;*/ 398 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 399 400 set_reg_field_value(value, 401 speakers, 402 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 403 SPEAKER_ALLOCATION); 404 405 /* LFE_PLAYBACK_LEVEL = LFEPBL 406 * LFEPBL = 0 : Unknown or refer to other information 407 * LFEPBL = 1 : 0dB playback 408 * LFEPBL = 2 : +10dB playback 409 * LFE_BL = 3 : Reserved 410 */ 411 set_reg_field_value(value, 412 0, 413 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 414 LFE_PLAYBACK_LEVEL); 415 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 416 * why are we writing to it? DCE8 does not write this */ 417 418 419 set_reg_field_value(value, 420 0, 421 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 422 HDMI_CONNECTION); 423 424 set_reg_field_value(value, 425 0, 426 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 427 DP_CONNECTION); 428 429 field = get_reg_field_value(value, 430 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 431 EXTRA_CONNECTION_INFO); 432 433 field &= ~0x1; 434 435 set_reg_field_value(value, 436 field, 437 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 438 EXTRA_CONNECTION_INFO); 439 440 /* set audio for output signal */ 441 switch (signal) { 442 case SIGNAL_TYPE_HDMI_TYPE_A: 443 set_reg_field_value(value, 444 1, 445 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 446 HDMI_CONNECTION); 447 448 break; 449 450 case SIGNAL_TYPE_EDP: 451 case SIGNAL_TYPE_DISPLAY_PORT: 452 case SIGNAL_TYPE_DISPLAY_PORT_MST: 453 set_reg_field_value(value, 454 1, 455 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 456 DP_CONNECTION); 457 break; 458 default: 459 BREAK_TO_DEBUGGER(); 460 break; 461 } 462 463 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 464 465 /* Audio Descriptors */ 466 /* pass through all formats */ 467 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 468 format_index++) { 469 audio_format_code = 470 (AUDIO_FORMAT_CODE_FIRST + format_index); 471 472 /* those are unsupported, skip programming */ 473 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 474 audio_format_code == AUDIO_FORMAT_CODE_DST) 475 continue; 476 477 value = 0; 478 479 /* check if supported */ 480 if (is_audio_format_supported( 481 audio_info, audio_format_code, &index)) { 482 const struct audio_mode *audio_mode = 483 &audio_info->modes[index]; 484 union audio_sample_rates sample_rates = 485 audio_mode->sample_rates; 486 uint8_t byte2 = audio_mode->max_bit_rate; 487 488 /* adjust specific properties */ 489 switch (audio_format_code) { 490 case AUDIO_FORMAT_CODE_LINEARPCM: { 491 check_audio_bandwidth( 492 crtc_info, 493 audio_mode->channel_count, 494 signal, 495 &sample_rates); 496 497 byte2 = audio_mode->sample_size; 498 499 set_reg_field_value(value, 500 sample_rates.all, 501 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 502 SUPPORTED_FREQUENCIES_STEREO); 503 } 504 break; 505 case AUDIO_FORMAT_CODE_AC3: 506 is_ac3_supported = true; 507 break; 508 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 509 case AUDIO_FORMAT_CODE_DTS_HD: 510 case AUDIO_FORMAT_CODE_MAT_MLP: 511 case AUDIO_FORMAT_CODE_DST: 512 case AUDIO_FORMAT_CODE_WMAPRO: 513 byte2 = audio_mode->vendor_specific; 514 break; 515 default: 516 break; 517 } 518 519 /* fill audio format data */ 520 set_reg_field_value(value, 521 audio_mode->channel_count - 1, 522 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 523 MAX_CHANNELS); 524 525 set_reg_field_value(value, 526 sample_rates.all, 527 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 528 SUPPORTED_FREQUENCIES); 529 530 set_reg_field_value(value, 531 byte2, 532 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 533 DESCRIPTOR_BYTE_2); 534 } /* if */ 535 536 AZ_REG_WRITE( 537 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 538 value); 539 } /* for */ 540 541 if (is_ac3_supported) 542 /* todo: this reg global. why program global register? */ 543 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 544 0x05); 545 546 /* check for 192khz/8-Ch support for HBR requirements */ 547 sample_rate.all = 0; 548 sample_rate.rate.RATE_192 = 1; 549 550 check_audio_bandwidth( 551 crtc_info, 552 8, 553 signal, 554 &sample_rate); 555 556 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 557 558 /* Audio and Video Lipsync */ 559 set_video_latency(audio, audio_info->video_latency); 560 set_audio_latency(audio, audio_info->audio_latency); 561 562 value = 0; 563 set_reg_field_value(value, audio_info->manufacture_id, 564 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 565 MANUFACTURER_ID); 566 567 set_reg_field_value(value, audio_info->product_id, 568 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 569 PRODUCT_ID); 570 571 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 572 value); 573 574 value = 0; 575 576 /*get display name string length */ 577 while (audio_info->display_name[strlen++] != '\0') { 578 if (strlen >= 579 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 580 break; 581 } 582 set_reg_field_value(value, strlen, 583 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 584 SINK_DESCRIPTION_LEN); 585 586 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 587 value); 588 589 /* 590 *write the port ID: 591 *PORT_ID0 = display index 592 *PORT_ID1 = 16bit BDF 593 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 594 */ 595 596 value = 0; 597 598 set_reg_field_value(value, audio_info->port_id[0], 599 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 600 PORT_ID0); 601 602 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 603 604 value = 0; 605 set_reg_field_value(value, audio_info->port_id[1], 606 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 607 PORT_ID1); 608 609 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 610 611 /*write the 18 char monitor string */ 612 613 value = 0; 614 set_reg_field_value(value, audio_info->display_name[0], 615 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 616 DESCRIPTION0); 617 618 set_reg_field_value(value, audio_info->display_name[1], 619 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 620 DESCRIPTION1); 621 622 set_reg_field_value(value, audio_info->display_name[2], 623 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 624 DESCRIPTION2); 625 626 set_reg_field_value(value, audio_info->display_name[3], 627 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 628 DESCRIPTION3); 629 630 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 631 632 value = 0; 633 set_reg_field_value(value, audio_info->display_name[4], 634 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 635 DESCRIPTION4); 636 637 set_reg_field_value(value, audio_info->display_name[5], 638 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 639 DESCRIPTION5); 640 641 set_reg_field_value(value, audio_info->display_name[6], 642 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 643 DESCRIPTION6); 644 645 set_reg_field_value(value, audio_info->display_name[7], 646 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 647 DESCRIPTION7); 648 649 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 650 651 value = 0; 652 set_reg_field_value(value, audio_info->display_name[8], 653 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 654 DESCRIPTION8); 655 656 set_reg_field_value(value, audio_info->display_name[9], 657 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 658 DESCRIPTION9); 659 660 set_reg_field_value(value, audio_info->display_name[10], 661 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 662 DESCRIPTION10); 663 664 set_reg_field_value(value, audio_info->display_name[11], 665 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 666 DESCRIPTION11); 667 668 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 669 670 value = 0; 671 set_reg_field_value(value, audio_info->display_name[12], 672 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 673 DESCRIPTION12); 674 675 set_reg_field_value(value, audio_info->display_name[13], 676 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 677 DESCRIPTION13); 678 679 set_reg_field_value(value, audio_info->display_name[14], 680 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 681 DESCRIPTION14); 682 683 set_reg_field_value(value, audio_info->display_name[15], 684 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 685 DESCRIPTION15); 686 687 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 688 689 value = 0; 690 set_reg_field_value(value, audio_info->display_name[16], 691 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 692 DESCRIPTION16); 693 694 set_reg_field_value(value, audio_info->display_name[17], 695 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 696 DESCRIPTION17); 697 698 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 699 } 700 701 /* 702 * todo: wall clk related functionality probably belong to clock_src. 703 */ 704 705 /* search pixel clock value for Azalia HDMI Audio */ 706 static bool get_azalia_clock_info_hdmi( 707 uint32_t crtc_pixel_clock_in_khz, 708 uint32_t actual_pixel_clock_in_khz, 709 struct azalia_clock_info *azalia_clock_info) 710 { 711 if (azalia_clock_info == NULL) 712 return false; 713 714 /* audio_dto_phase= 24 * 10,000; 715 * 24MHz in [100Hz] units */ 716 azalia_clock_info->audio_dto_phase = 717 24 * 10000; 718 719 /* audio_dto_module = PCLKFrequency * 10,000; 720 * [khz] -> [100Hz] */ 721 azalia_clock_info->audio_dto_module = 722 actual_pixel_clock_in_khz * 10; 723 724 return true; 725 } 726 727 static bool get_azalia_clock_info_dp( 728 uint32_t requested_pixel_clock_in_khz, 729 const struct audio_pll_info *pll_info, 730 struct azalia_clock_info *azalia_clock_info) 731 { 732 if (pll_info == NULL || azalia_clock_info == NULL) 733 return false; 734 735 /* Reported dpDtoSourceClockInkhz value for 736 * DCE8 already adjusted for SS, do not need any 737 * adjustment here anymore 738 */ 739 740 /*audio_dto_phase = 24 * 10,000; 741 * 24MHz in [100Hz] units */ 742 azalia_clock_info->audio_dto_phase = 24 * 10000; 743 744 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 745 * [khz] ->[100Hz] */ 746 azalia_clock_info->audio_dto_module = 747 pll_info->dp_dto_source_clock_in_khz * 10; 748 749 return true; 750 } 751 752 void dce_aud_wall_dto_setup( 753 struct audio *audio, 754 enum signal_type signal, 755 const struct audio_crtc_info *crtc_info, 756 const struct audio_pll_info *pll_info) 757 { 758 struct dce_audio *aud = DCE_AUD(audio); 759 760 struct azalia_clock_info clock_info = { 0 }; 761 762 if (dc_is_hdmi_signal(signal)) { 763 uint32_t src_sel; 764 765 /*DTO0 Programming goal: 766 -generate 24MHz, 128*Fs from 24MHz 767 -use DTO0 when an active HDMI port is connected 768 (optionally a DP is connected) */ 769 770 /* calculate DTO settings */ 771 get_azalia_clock_info_hdmi( 772 crtc_info->requested_pixel_clock, 773 crtc_info->calculated_pixel_clock, 774 &clock_info); 775 776 dm_logger_write(audio->ctx->logger, LOG_HW_AUDIO,\ 777 "\n%s:Input::requested_pixel_clock = %d"\ 778 "calculated_pixel_clock =%d\n"\ 779 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 780 crtc_info->requested_pixel_clock,\ 781 crtc_info->calculated_pixel_clock,\ 782 clock_info.audio_dto_module,\ 783 clock_info.audio_dto_phase); 784 785 /* On TN/SI, Program DTO source select and DTO select before 786 programming DTO modulo and DTO phase. These bits must be 787 programmed first, otherwise there will be no HDMI audio at boot 788 up. This is a HW sequence change (different from old ASICs). 789 Caution when changing this programming sequence. 790 791 HDMI enabled, using DTO0 792 program master CRTC for DTO0 */ 793 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 794 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 795 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 796 DCCG_AUDIO_DTO_SEL, 0); 797 798 /* module */ 799 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 800 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 801 802 /* phase */ 803 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 804 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 805 } else { 806 /*DTO1 Programming goal: 807 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 808 -default is to used DTO1, and switch to DTO0 when an audio 809 master HDMI port is connected 810 -use as default for DP 811 812 calculate DTO settings */ 813 get_azalia_clock_info_dp( 814 crtc_info->requested_pixel_clock, 815 pll_info, 816 &clock_info); 817 818 /* Program DTO select before programming DTO modulo and DTO 819 phase. default to use DTO1 */ 820 821 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 822 DCCG_AUDIO_DTO_SEL, 1); 823 824 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 825 DCCG_AUDIO_DTO_SEL, 1); 826 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 827 * Select 512fs for DP TODO: web register definition 828 * does not match register header file 829 * DCE11 version it's commented out while DCE8 it's set to 1 830 */ 831 832 /* module */ 833 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 834 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 835 836 /* phase */ 837 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 838 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 839 840 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 841 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 842 843 } 844 } 845 846 bool dce_aud_endpoint_valid( 847 struct audio *audio) 848 { 849 uint32_t value; 850 uint32_t port_connectivity; 851 852 value = AZ_REG_READ( 853 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 854 855 port_connectivity = get_reg_field_value(value, 856 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 857 PORT_CONNECTIVITY); 858 859 return !(port_connectivity == 1); 860 } 861 862 /* initialize HW state */ 863 void dce_aud_hw_init( 864 struct audio *audio) 865 { 866 struct dce_audio *aud = DCE_AUD(audio); 867 868 /* we only need to program the following registers once, so we only do 869 it for the inst 0*/ 870 if (audio->inst != 0) 871 return; 872 873 /* Suport R5 - 32khz 874 * Suport R6 - 44.1khz 875 * Suport R7 - 48khz 876 */ 877 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 878 AUDIO_RATE_CAPABILITIES, 0x70); 879 880 /*Keep alive bit to verify HW block in BU. */ 881 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 882 CLKSTOP, 1, 883 EPSS, 1); 884 } 885 886 static const struct audio_funcs funcs = { 887 .endpoint_valid = dce_aud_endpoint_valid, 888 .hw_init = dce_aud_hw_init, 889 .wall_dto_setup = dce_aud_wall_dto_setup, 890 .az_enable = dce_aud_az_enable, 891 .az_disable = dce_aud_az_disable, 892 .az_configure = dce_aud_az_configure, 893 .destroy = dce_aud_destroy, 894 }; 895 896 void dce_aud_destroy(struct audio **audio) 897 { 898 struct dce_audio *aud = DCE_AUD(*audio); 899 900 kfree(aud); 901 *audio = NULL; 902 } 903 904 struct audio *dce_audio_create( 905 struct dc_context *ctx, 906 unsigned int inst, 907 const struct dce_audio_registers *reg, 908 const struct dce_audio_shift *shifts, 909 const struct dce_aduio_mask *masks 910 ) 911 { 912 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 913 914 if (audio == NULL) { 915 ASSERT_CRITICAL(audio); 916 return NULL; 917 } 918 919 audio->base.ctx = ctx; 920 audio->base.inst = inst; 921 audio->base.funcs = &funcs; 922 923 audio->regs = reg; 924 audio->shifts = shifts; 925 audio->masks = masks; 926 927 return &audio->base; 928 } 929 930