1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef _DCE_ABM_H_ 28 #define _DCE_ABM_H_ 29 30 #include "abm.h" 31 32 #define ABM_COMMON_REG_LIST_DCE_BASE() \ 33 SR(BL_PWM_PERIOD_CNTL), \ 34 SR(BL_PWM_CNTL), \ 35 SR(BL_PWM_CNTL2), \ 36 SR(BL_PWM_GRP1_REG_LOCK), \ 37 SR(LVTMA_PWRSEQ_REF_DIV), \ 38 SR(MASTER_COMM_CNTL_REG), \ 39 SR(MASTER_COMM_CMD_REG), \ 40 SR(MASTER_COMM_DATA_REG1), \ 41 SR(DMCU_STATUS) 42 43 #define ABM_DCE110_COMMON_REG_LIST() \ 44 ABM_COMMON_REG_LIST_DCE_BASE(), \ 45 SR(DC_ABM1_HG_SAMPLE_RATE), \ 46 SR(DC_ABM1_LS_SAMPLE_RATE), \ 47 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 48 SR(DC_ABM1_HG_MISC_CTRL), \ 49 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 50 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 51 SR(BL1_PWM_TARGET_ABM_LEVEL), \ 52 SR(BL1_PWM_USER_LEVEL), \ 53 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 54 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 55 SR(BIOS_SCRATCH_2) 56 57 #define ABM_SF(reg_name, field_name, post_fix)\ 58 .field_name = reg_name ## __ ## field_name ## post_fix 59 60 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 61 ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \ 62 ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \ 63 ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \ 64 ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \ 65 ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \ 66 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \ 67 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \ 68 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \ 69 ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \ 70 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 71 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 72 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ 73 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh), \ 74 ABM_SF(DMCU_STATUS, UC_IN_RESET, mask_sh) 75 76 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ 77 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 78 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 79 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 80 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 81 ABM1_HG_VMAX_SEL, mask_sh), \ 82 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 83 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 84 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 85 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 86 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 87 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 88 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 89 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 90 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \ 91 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 92 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \ 93 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 94 ABM_SF(BL1_PWM_USER_LEVEL, \ 95 BL1_PWM_USER_LEVEL, mask_sh), \ 96 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 97 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 98 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 99 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 100 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 101 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 102 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 103 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 104 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 105 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 106 107 108 #define ABM_REG_FIELD_LIST(type) \ 109 type ABM1_HG_NUM_OF_BINS_SEL; \ 110 type ABM1_HG_VMAX_SEL; \ 111 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \ 112 type ABM1_IPCSC_COEFF_SEL_R; \ 113 type ABM1_IPCSC_COEFF_SEL_G; \ 114 type ABM1_IPCSC_COEFF_SEL_B; \ 115 type BL1_PWM_CURRENT_ABM_LEVEL; \ 116 type BL1_PWM_TARGET_ABM_LEVEL; \ 117 type BL1_PWM_USER_LEVEL; \ 118 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \ 119 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \ 120 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \ 121 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \ 122 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \ 123 type BL_PWM_PERIOD; \ 124 type BL_PWM_PERIOD_BITCNT; \ 125 type BL_ACTIVE_INT_FRAC_CNT; \ 126 type BL_PWM_FRACTIONAL_EN; \ 127 type MASTER_COMM_INTERRUPT; \ 128 type MASTER_COMM_CMD_REG_BYTE0; \ 129 type MASTER_COMM_CMD_REG_BYTE1; \ 130 type MASTER_COMM_CMD_REG_BYTE2; \ 131 type BL_PWM_REF_DIV; \ 132 type BL_PWM_EN; \ 133 type UC_IN_RESET; \ 134 type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \ 135 type BL_PWM_GRP1_REG_LOCK; \ 136 type BL_PWM_GRP1_REG_UPDATE_PENDING 137 138 struct dce_abm_shift { 139 ABM_REG_FIELD_LIST(uint8_t); 140 }; 141 142 struct dce_abm_mask { 143 ABM_REG_FIELD_LIST(uint32_t); 144 }; 145 146 struct dce_abm_registers { 147 uint32_t BL_PWM_PERIOD_CNTL; 148 uint32_t BL_PWM_CNTL; 149 uint32_t BL_PWM_CNTL2; 150 uint32_t LVTMA_PWRSEQ_REF_DIV; 151 uint32_t DC_ABM1_HG_SAMPLE_RATE; 152 uint32_t DC_ABM1_LS_SAMPLE_RATE; 153 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; 154 uint32_t DC_ABM1_HG_MISC_CTRL; 155 uint32_t DC_ABM1_IPCSC_COEFF_SEL; 156 uint32_t BL1_PWM_CURRENT_ABM_LEVEL; 157 uint32_t BL1_PWM_TARGET_ABM_LEVEL; 158 uint32_t BL1_PWM_USER_LEVEL; 159 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES; 160 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; 161 uint32_t MASTER_COMM_CNTL_REG; 162 uint32_t MASTER_COMM_CMD_REG; 163 uint32_t MASTER_COMM_DATA_REG1; 164 uint32_t BIOS_SCRATCH_2; 165 uint32_t DMCU_STATUS; 166 uint32_t BL_PWM_GRP1_REG_LOCK; 167 }; 168 169 struct dce_abm { 170 struct abm base; 171 const struct dce_abm_registers *regs; 172 const struct dce_abm_shift *abm_shift; 173 const struct dce_abm_mask *abm_mask; 174 }; 175 176 struct abm *dce_abm_create( 177 struct dc_context *ctx, 178 const struct dce_abm_registers *regs, 179 const struct dce_abm_shift *abm_shift, 180 const struct dce_abm_mask *abm_mask); 181 182 void dce_abm_destroy(struct abm **abm); 183 184 #endif /* _DCE_ABM_H_ */ 185