1 /*
2  * Copyright 2012-16 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #ifndef _DCE_ABM_H_
28 #define _DCE_ABM_H_
29 
30 #include "abm.h"
31 
32 #define ABM_COMMON_REG_LIST_DCE_BASE() \
33 	SR(BL_PWM_PERIOD_CNTL), \
34 	SR(BL_PWM_CNTL), \
35 	SR(BL_PWM_CNTL2), \
36 	SR(BL_PWM_GRP1_REG_LOCK), \
37 	SR(LVTMA_PWRSEQ_REF_DIV), \
38 	SR(MASTER_COMM_CNTL_REG), \
39 	SR(MASTER_COMM_CMD_REG), \
40 	SR(MASTER_COMM_DATA_REG1)
41 
42 #define ABM_DCE110_COMMON_REG_LIST() \
43 	ABM_COMMON_REG_LIST_DCE_BASE(), \
44 	SR(DC_ABM1_HG_SAMPLE_RATE), \
45 	SR(DC_ABM1_LS_SAMPLE_RATE), \
46 	SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
47 	SR(DC_ABM1_HG_MISC_CTRL), \
48 	SR(DC_ABM1_IPCSC_COEFF_SEL), \
49 	SR(BL1_PWM_CURRENT_ABM_LEVEL), \
50 	SR(BL1_PWM_TARGET_ABM_LEVEL), \
51 	SR(BL1_PWM_USER_LEVEL), \
52 	SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
53 	SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
54 	SR(BIOS_SCRATCH_2)
55 
56 #define ABM_DCN10_REG_LIST(id)\
57 	ABM_COMMON_REG_LIST_DCE_BASE(), \
58 	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
59 	SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
60 	SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
61 	SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
62 	SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
63 	SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
64 	SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
65 	SRI(BL1_PWM_USER_LEVEL, ABM, id), \
66 	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
67 	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
68 	NBIO_SR(BIOS_SCRATCH_2)
69 
70 #define ABM_SF(reg_name, field_name, post_fix)\
71 	.field_name = reg_name ## __ ## field_name ## post_fix
72 
73 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
74 	ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
75 	ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
76 	ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
77 	ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
78 	ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
79 	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
80 	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
81 	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \
82 	ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
83 	ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
84 	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
85 	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
86 	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
87 
88 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \
89 	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
90 	ABM_SF(DC_ABM1_HG_MISC_CTRL, \
91 			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
92 	ABM_SF(DC_ABM1_HG_MISC_CTRL, \
93 			ABM1_HG_VMAX_SEL, mask_sh), \
94 	ABM_SF(DC_ABM1_HG_MISC_CTRL, \
95 			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
96 	ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
97 			ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
98 	ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
99 			ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
100 	ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
101 			ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
102 	ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
103 			BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
104 	ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
105 			BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
106 	ABM_SF(BL1_PWM_USER_LEVEL, \
107 			BL1_PWM_USER_LEVEL, mask_sh), \
108 	ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
109 			ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
110 	ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
111 			ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
112 	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
113 			ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
114 	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
115 			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
116 	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
117 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
118 
119 #define ABM_MASK_SH_LIST_DCN10(mask_sh) \
120 	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
121 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
122 			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
123 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
124 			ABM1_HG_VMAX_SEL, mask_sh), \
125 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
126 			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
127 	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
128 			ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
129 	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
130 			ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
131 	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
132 			ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
133 	ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
134 			BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
135 	ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
136 			BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
137 	ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
138 			BL1_PWM_USER_LEVEL, mask_sh), \
139 	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
140 			ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
141 	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
142 			ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
143 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
144 			ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
145 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
146 			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
147 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
148 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
149 
150 #define ABM_REG_FIELD_LIST(type) \
151 	type ABM1_HG_NUM_OF_BINS_SEL; \
152 	type ABM1_HG_VMAX_SEL; \
153 	type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
154 	type ABM1_IPCSC_COEFF_SEL_R; \
155 	type ABM1_IPCSC_COEFF_SEL_G; \
156 	type ABM1_IPCSC_COEFF_SEL_B; \
157 	type BL1_PWM_CURRENT_ABM_LEVEL; \
158 	type BL1_PWM_TARGET_ABM_LEVEL; \
159 	type BL1_PWM_USER_LEVEL; \
160 	type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
161 	type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
162 	type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
163 	type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
164 	type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
165 	type BL_PWM_PERIOD; \
166 	type BL_PWM_PERIOD_BITCNT; \
167 	type BL_ACTIVE_INT_FRAC_CNT; \
168 	type BL_PWM_FRACTIONAL_EN; \
169 	type MASTER_COMM_INTERRUPT; \
170 	type MASTER_COMM_CMD_REG_BYTE0; \
171 	type MASTER_COMM_CMD_REG_BYTE1; \
172 	type MASTER_COMM_CMD_REG_BYTE2; \
173 	type BL_PWM_REF_DIV; \
174 	type BL_PWM_EN; \
175 	type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
176 	type BL_PWM_GRP1_REG_LOCK; \
177 	type BL_PWM_GRP1_REG_UPDATE_PENDING
178 
179 struct dce_abm_shift {
180 	ABM_REG_FIELD_LIST(uint8_t);
181 };
182 
183 struct dce_abm_mask {
184 	ABM_REG_FIELD_LIST(uint32_t);
185 };
186 
187 struct dce_abm_registers {
188 	uint32_t BL_PWM_PERIOD_CNTL;
189 	uint32_t BL_PWM_CNTL;
190 	uint32_t BL_PWM_CNTL2;
191 	uint32_t LVTMA_PWRSEQ_REF_DIV;
192 	uint32_t DC_ABM1_HG_SAMPLE_RATE;
193 	uint32_t DC_ABM1_LS_SAMPLE_RATE;
194 	uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
195 	uint32_t DC_ABM1_HG_MISC_CTRL;
196 	uint32_t DC_ABM1_IPCSC_COEFF_SEL;
197 	uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
198 	uint32_t BL1_PWM_TARGET_ABM_LEVEL;
199 	uint32_t BL1_PWM_USER_LEVEL;
200 	uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
201 	uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
202 	uint32_t MASTER_COMM_CNTL_REG;
203 	uint32_t MASTER_COMM_CMD_REG;
204 	uint32_t MASTER_COMM_DATA_REG1;
205 	uint32_t BIOS_SCRATCH_2;
206 	uint32_t BL_PWM_GRP1_REG_LOCK;
207 };
208 
209 struct dce_abm {
210 	struct abm base;
211 	const struct dce_abm_registers *regs;
212 	const struct dce_abm_shift *abm_shift;
213 	const struct dce_abm_mask *abm_mask;
214 };
215 
216 struct abm *dce_abm_create(
217 	struct dc_context *ctx,
218 	const struct dce_abm_registers *regs,
219 	const struct dce_abm_shift *abm_shift,
220 	const struct dce_abm_mask *abm_mask);
221 
222 void dce_abm_destroy(struct abm **abm);
223 
224 #endif /* _DCE_ABM_H_ */
225