1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce_abm.h" 27 #include "dm_services.h" 28 #include "reg_helper.h" 29 #include "fixed32_32.h" 30 #include "dc.h" 31 32 #include "atom.h" 33 34 35 #define TO_DCE_ABM(abm)\ 36 container_of(abm, struct dce_abm, base) 37 38 #define REG(reg) \ 39 (abm_dce->regs->reg) 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name 44 45 #define CTX \ 46 abm_dce->base.ctx 47 48 #define MCP_ABM_LEVEL_SET 0x65 49 #define MCP_ABM_PIPE_SET 0x66 50 #define MCP_BL_SET 0x67 51 52 #define MCP_DISABLE_ABM_IMMEDIATELY 255 53 54 55 static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce) 56 { 57 uint64_t current_backlight; 58 uint32_t round_result; 59 uint32_t pwm_period_cntl, bl_period, bl_int_count; 60 uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en; 61 uint32_t bl_period_mask, bl_pwm_mask; 62 63 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL); 64 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); 65 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); 66 67 bl_pwm_cntl = REG_READ(BL_PWM_CNTL); 68 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); 69 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); 70 71 if (bl_int_count == 0) 72 bl_int_count = 16; 73 74 bl_period_mask = (1 << bl_int_count) - 1; 75 bl_period &= bl_period_mask; 76 77 bl_pwm_mask = bl_period_mask << (16 - bl_int_count); 78 79 if (fractional_duty_cycle_en == 0) 80 bl_pwm &= bl_pwm_mask; 81 else 82 bl_pwm &= 0xFFFF; 83 84 current_backlight = bl_pwm << (1 + bl_int_count); 85 86 if (bl_period == 0) 87 bl_period = 0xFFFF; 88 89 current_backlight = div_u64(current_backlight, bl_period); 90 current_backlight = (current_backlight + 1) >> 1; 91 92 current_backlight = (uint64_t)(current_backlight) * bl_period; 93 94 round_result = (uint32_t)(current_backlight & 0xFFFFFFFF); 95 96 round_result = (round_result >> (bl_int_count-1)) & 1; 97 98 current_backlight >>= bl_int_count; 99 current_backlight += round_result; 100 101 return (uint32_t)(current_backlight); 102 } 103 104 static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level) 105 { 106 uint32_t backlight_24bit; 107 uint32_t backlight_17bit; 108 uint32_t backlight_16bit; 109 uint32_t masked_pwm_period; 110 uint8_t rounding_bit; 111 uint8_t bit_count; 112 uint64_t active_duty_cycle; 113 uint32_t pwm_period_bitcnt; 114 115 /* 116 * 1. Convert 8-bit value to 17 bit U1.16 format 117 * (1 integer, 16 fractional bits) 118 */ 119 120 /* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value, 121 * effectively multiplying value by 256/255 122 * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF 123 */ 124 backlight_24bit = level * 0x10101; 125 126 /* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8 127 * used for rounding, take most significant bit of fraction for 128 * rounding, e.g. for 0xEFEFEF, rounding bit is 1 129 */ 130 rounding_bit = (backlight_24bit >> 7) & 1; 131 132 /* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit 133 * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1 134 */ 135 backlight_17bit = (backlight_24bit >> 8) + rounding_bit; 136 137 /* 138 * 2. Find 16 bit backlight active duty cycle, where 0 <= backlight 139 * active duty cycle <= backlight period 140 */ 141 142 /* 2.1 Apply bitmask for backlight period value based on value of BITCNT 143 */ 144 REG_GET_2(BL_PWM_PERIOD_CNTL, 145 BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt, 146 BL_PWM_PERIOD, &masked_pwm_period); 147 148 if (pwm_period_bitcnt == 0) 149 bit_count = 16; 150 else 151 bit_count = pwm_period_bitcnt; 152 153 /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ 154 masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1); 155 156 /* 2.2 Calculate integer active duty cycle required upper 16 bits 157 * contain integer component, lower 16 bits contain fractional component 158 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24 159 */ 160 active_duty_cycle = backlight_17bit * masked_pwm_period; 161 162 /* 2.3 Calculate 16 bit active duty cycle from integer and fractional 163 * components shift by bitCount then mask 16 bits and add rounding bit 164 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 165 */ 166 backlight_16bit = active_duty_cycle >> bit_count; 167 backlight_16bit &= 0xFFFF; 168 backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; 169 170 /* 171 * 3. Program register with updated value 172 */ 173 174 /* 3.1 Lock group 2 backlight registers */ 175 176 REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK, 177 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1, 178 BL_PWM_GRP1_REG_LOCK, 1); 179 180 // 3.2 Write new active duty cycle 181 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); 182 183 /* 3.3 Unlock group 2 backlight registers */ 184 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, 185 BL_PWM_GRP1_REG_LOCK, 0); 186 187 /* 5.4.4 Wait for pending bit to be cleared */ 188 REG_WAIT(BL_PWM_GRP1_REG_LOCK, 189 BL_PWM_GRP1_REG_UPDATE_PENDING, 0, 190 1, 10000); 191 } 192 193 static void dmcu_set_backlight_level( 194 struct dce_abm *abm_dce, 195 uint32_t level, 196 uint32_t frame_ramp, 197 uint32_t controller_id) 198 { 199 unsigned int backlight_16_bit = (level * 0x10101) >> 8; 200 unsigned int backlight_17_bit = backlight_16_bit + 201 (((backlight_16_bit & 0x80) >> 7) & 1); 202 uint32_t rampingBoundary = 0xFFFF; 203 uint32_t s2; 204 205 /* set ramping boundary */ 206 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); 207 208 /* setDMCUParam_Pipe */ 209 REG_UPDATE_2(MASTER_COMM_CMD_REG, 210 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET, 211 MASTER_COMM_CMD_REG_BYTE1, controller_id); 212 213 /* notifyDMCUMsg */ 214 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 215 216 /* waitDMCUReadyForCmd */ 217 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 218 0, 1, 80000); 219 220 /* setDMCUParam_BL */ 221 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit); 222 223 /* write ramp */ 224 if (controller_id == 0) 225 frame_ramp = 0; 226 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); 227 228 /* setDMCUParam_Cmd */ 229 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); 230 231 /* notifyDMCUMsg */ 232 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 233 234 /* UpdateRequestedBacklightLevel */ 235 s2 = REG_READ(BIOS_SCRATCH_2); 236 237 s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 238 level &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >> 239 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 240 s2 |= (level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 241 242 REG_WRITE(BIOS_SCRATCH_2, s2); 243 } 244 245 static void dce_abm_init(struct abm *abm) 246 { 247 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 248 unsigned int backlight = get_current_backlight_16_bit(abm_dce); 249 250 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); 251 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); 252 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); 253 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); 254 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); 255 256 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, 257 ABM1_HG_NUM_OF_BINS_SEL, 0, 258 ABM1_HG_VMAX_SEL, 1, 259 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0); 260 261 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, 262 ABM1_IPCSC_COEFF_SEL_R, 2, 263 ABM1_IPCSC_COEFF_SEL_G, 4, 264 ABM1_IPCSC_COEFF_SEL_B, 2); 265 266 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL, 267 BL1_PWM_CURRENT_ABM_LEVEL, backlight); 268 269 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL, 270 BL1_PWM_TARGET_ABM_LEVEL, backlight); 271 272 REG_UPDATE(BL1_PWM_USER_LEVEL, 273 BL1_PWM_USER_LEVEL, backlight); 274 275 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, 276 ABM1_LS_MIN_PIXEL_VALUE_THRES, 0, 277 ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000); 278 279 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, 280 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1, 281 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1, 282 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1); 283 } 284 285 static unsigned int dce_abm_get_current_backlight_8_bit(struct abm *abm) 286 { 287 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 288 unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL); 289 290 return (backlight >> 8); 291 } 292 293 static bool dce_abm_set_level(struct abm *abm, uint32_t level) 294 { 295 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 296 297 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 298 1, 80000); 299 300 /* setDMCUParam_ABMLevel */ 301 REG_UPDATE_2(MASTER_COMM_CMD_REG, 302 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET, 303 MASTER_COMM_CMD_REG_BYTE2, level); 304 305 /* notifyDMCUMsg */ 306 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 307 308 return true; 309 } 310 311 static bool dce_abm_immediate_disable(struct abm *abm) 312 { 313 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 314 315 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 316 1, 80000); 317 318 /* setDMCUParam_ABMLevel */ 319 REG_UPDATE_2(MASTER_COMM_CMD_REG, 320 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET, 321 MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY); 322 323 /* notifyDMCUMsg */ 324 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 325 326 return true; 327 } 328 329 static bool dce_abm_init_backlight(struct abm *abm) 330 { 331 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 332 uint32_t value; 333 334 /* It must not be 0, so we have to restore them 335 * Bios bug w/a - period resets to zero, 336 * restoring to cache values which is always correct 337 */ 338 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); 339 if (value == 0 || value == 1) { 340 if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) { 341 REG_WRITE(BL_PWM_CNTL, 342 abm->stored_backlight_registers.BL_PWM_CNTL); 343 REG_WRITE(BL_PWM_CNTL2, 344 abm->stored_backlight_registers.BL_PWM_CNTL2); 345 REG_WRITE(BL_PWM_PERIOD_CNTL, 346 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL); 347 REG_UPDATE(LVTMA_PWRSEQ_REF_DIV, 348 BL_PWM_REF_DIV, 349 abm->stored_backlight_registers. 350 LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); 351 } else { 352 /* TODO: Note: This should not really happen since VBIOS 353 * should have initialized PWM registers on boot. 354 */ 355 REG_WRITE(BL_PWM_CNTL, 0xC000FA00); 356 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); 357 } 358 } else { 359 abm->stored_backlight_registers.BL_PWM_CNTL = 360 REG_READ(BL_PWM_CNTL); 361 abm->stored_backlight_registers.BL_PWM_CNTL2 = 362 REG_READ(BL_PWM_CNTL2); 363 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 364 REG_READ(BL_PWM_PERIOD_CNTL); 365 366 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, 367 &abm->stored_backlight_registers. 368 LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); 369 } 370 371 /* Have driver take backlight control 372 * TakeBacklightControl(true) 373 */ 374 value = REG_READ(BIOS_SCRATCH_2); 375 value |= ATOM_S2_VRI_BRIGHT_ENABLE; 376 REG_WRITE(BIOS_SCRATCH_2, value); 377 378 /* Enable the backlight output */ 379 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); 380 381 /* Unlock group 2 backlight registers */ 382 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, 383 BL_PWM_GRP1_REG_LOCK, 0); 384 385 return true; 386 } 387 388 static bool dce_abm_set_backlight_level( 389 struct abm *abm, 390 unsigned int backlight_level, 391 unsigned int frame_ramp, 392 unsigned int controller_id, 393 bool use_smooth_brightness) 394 { 395 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 396 397 dm_logger_write(abm->ctx->logger, LOG_BACKLIGHT, 398 "New Backlight level: %d (0x%X)\n", 399 backlight_level, backlight_level); 400 401 /* If DMCU is in reset state, DMCU is uninitialized */ 402 if (use_smooth_brightness) 403 dmcu_set_backlight_level(abm_dce, 404 backlight_level, 405 frame_ramp, 406 controller_id); 407 else 408 driver_set_backlight_level(abm_dce, backlight_level); 409 410 return true; 411 } 412 413 static const struct abm_funcs dce_funcs = { 414 .abm_init = dce_abm_init, 415 .set_abm_level = dce_abm_set_level, 416 .init_backlight = dce_abm_init_backlight, 417 .set_backlight_level = dce_abm_set_backlight_level, 418 .get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit, 419 .set_abm_immediate_disable = dce_abm_immediate_disable 420 }; 421 422 static void dce_abm_construct( 423 struct dce_abm *abm_dce, 424 struct dc_context *ctx, 425 const struct dce_abm_registers *regs, 426 const struct dce_abm_shift *abm_shift, 427 const struct dce_abm_mask *abm_mask) 428 { 429 struct abm *base = &abm_dce->base; 430 431 base->ctx = ctx; 432 base->funcs = &dce_funcs; 433 base->stored_backlight_registers.BL_PWM_CNTL = 0; 434 base->stored_backlight_registers.BL_PWM_CNTL2 = 0; 435 base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0; 436 base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0; 437 438 abm_dce->regs = regs; 439 abm_dce->abm_shift = abm_shift; 440 abm_dce->abm_mask = abm_mask; 441 } 442 443 struct abm *dce_abm_create( 444 struct dc_context *ctx, 445 const struct dce_abm_registers *regs, 446 const struct dce_abm_shift *abm_shift, 447 const struct dce_abm_mask *abm_mask) 448 { 449 struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL); 450 451 if (abm_dce == NULL) { 452 BREAK_TO_DEBUGGER(); 453 return NULL; 454 } 455 456 dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask); 457 458 abm_dce->base.funcs = &dce_funcs; 459 460 return &abm_dce->base; 461 } 462 463 void dce_abm_destroy(struct abm **abm) 464 { 465 struct dce_abm *abm_dce = TO_DCE_ABM(*abm); 466 467 kfree(abm_dce); 468 *abm = NULL; 469 } 470