1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce_abm.h" 27 #include "dm_services.h" 28 #include "reg_helper.h" 29 #include "fixed31_32.h" 30 #include "dc.h" 31 32 #include "atom.h" 33 34 35 #define TO_DCE_ABM(abm)\ 36 container_of(abm, struct dce_abm, base) 37 38 #define REG(reg) \ 39 (abm_dce->regs->reg) 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name 44 45 #define DC_LOGGER \ 46 abm->ctx->logger 47 #define CTX \ 48 abm_dce->base.ctx 49 50 #define MCP_ABM_LEVEL_SET 0x65 51 #define MCP_ABM_PIPE_SET 0x66 52 #define MCP_BL_SET 0x67 53 54 #define MCP_DISABLE_ABM_IMMEDIATELY 255 55 56 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id) 57 { 58 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 59 uint32_t rampingBoundary = 0xFFFF; 60 61 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 62 1, 80000); 63 64 /* set ramping boundary */ 65 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); 66 67 /* setDMCUParam_Pipe */ 68 REG_UPDATE_2(MASTER_COMM_CMD_REG, 69 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET, 70 MASTER_COMM_CMD_REG_BYTE1, controller_id); 71 72 /* notifyDMCUMsg */ 73 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 74 75 return true; 76 } 77 78 static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_abm *abm_dce) 79 { 80 uint64_t current_backlight; 81 uint32_t round_result; 82 uint32_t pwm_period_cntl, bl_period, bl_int_count; 83 uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en; 84 uint32_t bl_period_mask, bl_pwm_mask; 85 86 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL); 87 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); 88 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); 89 90 bl_pwm_cntl = REG_READ(BL_PWM_CNTL); 91 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); 92 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); 93 94 if (bl_int_count == 0) 95 bl_int_count = 16; 96 97 bl_period_mask = (1 << bl_int_count) - 1; 98 bl_period &= bl_period_mask; 99 100 bl_pwm_mask = bl_period_mask << (16 - bl_int_count); 101 102 if (fractional_duty_cycle_en == 0) 103 bl_pwm &= bl_pwm_mask; 104 else 105 bl_pwm &= 0xFFFF; 106 107 current_backlight = bl_pwm << (1 + bl_int_count); 108 109 if (bl_period == 0) 110 bl_period = 0xFFFF; 111 112 current_backlight = div_u64(current_backlight, bl_period); 113 current_backlight = (current_backlight + 1) >> 1; 114 115 current_backlight = (uint64_t)(current_backlight) * bl_period; 116 117 round_result = (uint32_t)(current_backlight & 0xFFFFFFFF); 118 119 round_result = (round_result >> (bl_int_count-1)) & 1; 120 121 current_backlight >>= bl_int_count; 122 current_backlight += round_result; 123 124 return (uint32_t)(current_backlight); 125 } 126 127 static void driver_set_backlight_level(struct dce_abm *abm_dce, 128 uint32_t backlight_pwm_u16_16) 129 { 130 uint32_t backlight_16bit; 131 uint32_t masked_pwm_period; 132 uint8_t bit_count; 133 uint64_t active_duty_cycle; 134 uint32_t pwm_period_bitcnt; 135 136 /* 137 * 1. Find 16 bit backlight active duty cycle, where 0 <= backlight 138 * active duty cycle <= backlight period 139 */ 140 141 /* 1.1 Apply bitmask for backlight period value based on value of BITCNT 142 */ 143 REG_GET_2(BL_PWM_PERIOD_CNTL, 144 BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt, 145 BL_PWM_PERIOD, &masked_pwm_period); 146 147 if (pwm_period_bitcnt == 0) 148 bit_count = 16; 149 else 150 bit_count = pwm_period_bitcnt; 151 152 /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ 153 masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1); 154 155 /* 1.2 Calculate integer active duty cycle required upper 16 bits 156 * contain integer component, lower 16 bits contain fractional component 157 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24 158 */ 159 active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period; 160 161 /* 1.3 Calculate 16 bit active duty cycle from integer and fractional 162 * components shift by bitCount then mask 16 bits and add rounding bit 163 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 164 */ 165 backlight_16bit = active_duty_cycle >> bit_count; 166 backlight_16bit &= 0xFFFF; 167 backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; 168 169 /* 170 * 2. Program register with updated value 171 */ 172 173 /* 2.1 Lock group 2 backlight registers */ 174 175 REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK, 176 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1, 177 BL_PWM_GRP1_REG_LOCK, 1); 178 179 // 2.2 Write new active duty cycle 180 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); 181 182 /* 2.3 Unlock group 2 backlight registers */ 183 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, 184 BL_PWM_GRP1_REG_LOCK, 0); 185 186 /* 3 Wait for pending bit to be cleared */ 187 REG_WAIT(BL_PWM_GRP1_REG_LOCK, 188 BL_PWM_GRP1_REG_UPDATE_PENDING, 0, 189 1, 10000); 190 } 191 192 static void dmcu_set_backlight_level( 193 struct dce_abm *abm_dce, 194 uint32_t backlight_pwm_u16_16, 195 uint32_t frame_ramp, 196 uint32_t controller_id) 197 { 198 unsigned int backlight_8_bit = 0; 199 uint32_t s2; 200 201 if (backlight_pwm_u16_16 & 0x10000) 202 // Check for max backlight condition 203 backlight_8_bit = 0xFF; 204 else 205 // Take MSB of fractional part since backlight is not max 206 backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF; 207 208 dce_abm_set_pipe(&abm_dce->base, controller_id); 209 210 /* waitDMCUReadyForCmd */ 211 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 212 0, 1, 80000); 213 214 /* setDMCUParam_BL */ 215 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16); 216 217 /* write ramp */ 218 if (controller_id == 0) 219 frame_ramp = 0; 220 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); 221 222 /* setDMCUParam_Cmd */ 223 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); 224 225 /* notifyDMCUMsg */ 226 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 227 228 /* UpdateRequestedBacklightLevel */ 229 s2 = REG_READ(BIOS_SCRATCH_2); 230 231 s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 232 backlight_8_bit &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >> 233 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 234 s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 235 236 REG_WRITE(BIOS_SCRATCH_2, s2); 237 } 238 239 static void dce_abm_init(struct abm *abm) 240 { 241 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 242 unsigned int backlight = calculate_16_bit_backlight_from_pwm(abm_dce); 243 244 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); 245 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); 246 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); 247 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); 248 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); 249 250 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, 251 ABM1_HG_NUM_OF_BINS_SEL, 0, 252 ABM1_HG_VMAX_SEL, 1, 253 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0); 254 255 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, 256 ABM1_IPCSC_COEFF_SEL_R, 2, 257 ABM1_IPCSC_COEFF_SEL_G, 4, 258 ABM1_IPCSC_COEFF_SEL_B, 2); 259 260 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL, 261 BL1_PWM_CURRENT_ABM_LEVEL, backlight); 262 263 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL, 264 BL1_PWM_TARGET_ABM_LEVEL, backlight); 265 266 REG_UPDATE(BL1_PWM_USER_LEVEL, 267 BL1_PWM_USER_LEVEL, backlight); 268 269 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, 270 ABM1_LS_MIN_PIXEL_VALUE_THRES, 0, 271 ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000); 272 273 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, 274 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1, 275 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1, 276 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1); 277 } 278 279 static unsigned int dce_abm_get_current_backlight(struct abm *abm) 280 { 281 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 282 unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL); 283 284 /* return backlight in hardware format which is unsigned 17 bits, with 285 * 1 bit integer and 16 bit fractional 286 */ 287 return backlight; 288 } 289 290 static unsigned int dce_abm_get_target_backlight(struct abm *abm) 291 { 292 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 293 unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL); 294 295 /* return backlight in hardware format which is unsigned 17 bits, with 296 * 1 bit integer and 16 bit fractional 297 */ 298 return backlight; 299 } 300 301 static bool dce_abm_set_level(struct abm *abm, uint32_t level) 302 { 303 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 304 305 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 306 1, 80000); 307 308 /* setDMCUParam_ABMLevel */ 309 REG_UPDATE_2(MASTER_COMM_CMD_REG, 310 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET, 311 MASTER_COMM_CMD_REG_BYTE2, level); 312 313 /* notifyDMCUMsg */ 314 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 315 316 return true; 317 } 318 319 static bool dce_abm_immediate_disable(struct abm *abm) 320 { 321 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 322 323 dce_abm_set_pipe(abm, MCP_DISABLE_ABM_IMMEDIATELY); 324 325 abm->stored_backlight_registers.BL_PWM_CNTL = 326 REG_READ(BL_PWM_CNTL); 327 abm->stored_backlight_registers.BL_PWM_CNTL2 = 328 REG_READ(BL_PWM_CNTL2); 329 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 330 REG_READ(BL_PWM_PERIOD_CNTL); 331 332 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, 333 &abm->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); 334 return true; 335 } 336 337 static bool dce_abm_init_backlight(struct abm *abm) 338 { 339 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 340 uint32_t value; 341 342 /* It must not be 0, so we have to restore them 343 * Bios bug w/a - period resets to zero, 344 * restoring to cache values which is always correct 345 */ 346 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); 347 if (value == 0 || value == 1) { 348 if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) { 349 REG_WRITE(BL_PWM_CNTL, 350 abm->stored_backlight_registers.BL_PWM_CNTL); 351 REG_WRITE(BL_PWM_CNTL2, 352 abm->stored_backlight_registers.BL_PWM_CNTL2); 353 REG_WRITE(BL_PWM_PERIOD_CNTL, 354 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL); 355 REG_UPDATE(LVTMA_PWRSEQ_REF_DIV, 356 BL_PWM_REF_DIV, 357 abm->stored_backlight_registers. 358 LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); 359 } else { 360 /* TODO: Note: This should not really happen since VBIOS 361 * should have initialized PWM registers on boot. 362 */ 363 REG_WRITE(BL_PWM_CNTL, 0xC000FA00); 364 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); 365 } 366 } else { 367 abm->stored_backlight_registers.BL_PWM_CNTL = 368 REG_READ(BL_PWM_CNTL); 369 abm->stored_backlight_registers.BL_PWM_CNTL2 = 370 REG_READ(BL_PWM_CNTL2); 371 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 372 REG_READ(BL_PWM_PERIOD_CNTL); 373 374 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, 375 &abm->stored_backlight_registers. 376 LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); 377 } 378 379 /* Have driver take backlight control 380 * TakeBacklightControl(true) 381 */ 382 value = REG_READ(BIOS_SCRATCH_2); 383 value |= ATOM_S2_VRI_BRIGHT_ENABLE; 384 REG_WRITE(BIOS_SCRATCH_2, value); 385 386 /* Enable the backlight output */ 387 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); 388 389 /* Unlock group 2 backlight registers */ 390 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, 391 BL_PWM_GRP1_REG_LOCK, 0); 392 393 return true; 394 } 395 396 static bool dce_abm_set_backlight_level_pwm( 397 struct abm *abm, 398 unsigned int backlight_pwm_u16_16, 399 unsigned int frame_ramp, 400 unsigned int controller_id, 401 bool use_smooth_brightness) 402 { 403 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 404 405 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", 406 backlight_pwm_u16_16, backlight_pwm_u16_16); 407 408 /* If DMCU is in reset state, DMCU is uninitialized */ 409 if (use_smooth_brightness) 410 dmcu_set_backlight_level(abm_dce, 411 backlight_pwm_u16_16, 412 frame_ramp, 413 controller_id); 414 else 415 driver_set_backlight_level(abm_dce, backlight_pwm_u16_16); 416 417 return true; 418 } 419 420 static const struct abm_funcs dce_funcs = { 421 .abm_init = dce_abm_init, 422 .set_abm_level = dce_abm_set_level, 423 .init_backlight = dce_abm_init_backlight, 424 .set_pipe = dce_abm_set_pipe, 425 .set_backlight_level_pwm = dce_abm_set_backlight_level_pwm, 426 .get_current_backlight = dce_abm_get_current_backlight, 427 .get_target_backlight = dce_abm_get_target_backlight, 428 .set_abm_immediate_disable = dce_abm_immediate_disable 429 }; 430 431 static void dce_abm_construct( 432 struct dce_abm *abm_dce, 433 struct dc_context *ctx, 434 const struct dce_abm_registers *regs, 435 const struct dce_abm_shift *abm_shift, 436 const struct dce_abm_mask *abm_mask) 437 { 438 struct abm *base = &abm_dce->base; 439 440 base->ctx = ctx; 441 base->funcs = &dce_funcs; 442 base->stored_backlight_registers.BL_PWM_CNTL = 0; 443 base->stored_backlight_registers.BL_PWM_CNTL2 = 0; 444 base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0; 445 base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0; 446 447 abm_dce->regs = regs; 448 abm_dce->abm_shift = abm_shift; 449 abm_dce->abm_mask = abm_mask; 450 } 451 452 struct abm *dce_abm_create( 453 struct dc_context *ctx, 454 const struct dce_abm_registers *regs, 455 const struct dce_abm_shift *abm_shift, 456 const struct dce_abm_mask *abm_mask) 457 { 458 struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL); 459 460 if (abm_dce == NULL) { 461 BREAK_TO_DEBUGGER(); 462 return NULL; 463 } 464 465 dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask); 466 467 abm_dce->base.funcs = &dce_funcs; 468 469 return &abm_dce->base; 470 } 471 472 void dce_abm_destroy(struct abm **abm) 473 { 474 struct dce_abm *abm_dce = TO_DCE_ABM(*abm); 475 476 kfree(abm_dce); 477 *abm = NULL; 478 } 479