1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_dp_types.h" 36 #include "dc_hw_types.h" 37 #include "dal_types.h" 38 #include "grph_object_defs.h" 39 40 #ifdef CONFIG_DRM_AMD_DC_HDCP 41 #include "dm_cp_psp.h" 42 #endif 43 44 /* forward declarations */ 45 struct dc_plane_state; 46 struct dc_stream_state; 47 struct dc_link; 48 struct dc_sink; 49 struct dal; 50 struct dc_dmub_srv; 51 52 /******************************** 53 * Environment definitions 54 ********************************/ 55 enum dce_environment { 56 DCE_ENV_PRODUCTION_DRV = 0, 57 /* Emulation on FPGA, in "Maximus" System. 58 * This environment enforces that *only* DC registers accessed. 59 * (access to non-DC registers will hang FPGA) */ 60 DCE_ENV_FPGA_MAXIMUS, 61 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 62 * requirements of Diagnostics team. */ 63 DCE_ENV_DIAG, 64 /* 65 * Guest VM system, DC HW may exist but is not virtualized and 66 * should not be used. SW support for VDI only. 67 */ 68 DCE_ENV_VIRTUAL_HW 69 }; 70 71 /* Note: use these macro definitions instead of direct comparison! */ 72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ 73 (dce_environment == DCE_ENV_FPGA_MAXIMUS) 74 75 #define IS_DIAG_DC(dce_environment) \ 76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) 77 78 struct dc_perf_trace { 79 unsigned long read_count; 80 unsigned long write_count; 81 unsigned long last_entry_read; 82 unsigned long last_entry_write; 83 }; 84 85 #define DC_MAX_EDID_BUFFER_SIZE 2048 86 #define DC_EDID_BLOCK_SIZE 128 87 #define MAX_SURFACE_NUM 4 88 #define NUM_PIXEL_FORMATS 10 89 #define MAX_REPEATER_CNT 8 90 91 #include "dc_ddc_types.h" 92 93 enum tiling_mode { 94 TILING_MODE_INVALID, 95 TILING_MODE_LINEAR, 96 TILING_MODE_TILED, 97 TILING_MODE_COUNT 98 }; 99 100 enum view_3d_format { 101 VIEW_3D_FORMAT_NONE = 0, 102 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 103 VIEW_3D_FORMAT_SIDE_BY_SIDE, 104 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 105 VIEW_3D_FORMAT_COUNT, 106 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 107 }; 108 109 enum plane_stereo_format { 110 PLANE_STEREO_FORMAT_NONE = 0, 111 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 112 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 113 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 114 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 115 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 116 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 117 }; 118 119 /* TODO: Find way to calculate number of bits 120 * Please increase if pixel_format enum increases 121 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 122 */ 123 124 enum dc_edid_connector_type { 125 DC_EDID_CONNECTOR_UNKNOWN = 0, 126 DC_EDID_CONNECTOR_ANALOG = 1, 127 DC_EDID_CONNECTOR_DIGITAL = 10, 128 DC_EDID_CONNECTOR_DVI = 11, 129 DC_EDID_CONNECTOR_HDMIA = 12, 130 DC_EDID_CONNECTOR_MDDI = 14, 131 DC_EDID_CONNECTOR_DISPLAYPORT = 15 132 }; 133 134 enum dc_edid_status { 135 EDID_OK, 136 EDID_BAD_INPUT, 137 EDID_NO_RESPONSE, 138 EDID_BAD_CHECKSUM, 139 EDID_THE_SAME, 140 EDID_FALL_BACK, 141 }; 142 143 enum act_return_status { 144 ACT_SUCCESS, 145 ACT_LINK_LOST, 146 ACT_FAILED 147 }; 148 149 /* audio capability from EDID*/ 150 struct dc_cea_audio_mode { 151 uint8_t format_code; /* ucData[0] [6:3]*/ 152 uint8_t channel_count; /* ucData[0] [2:0]*/ 153 uint8_t sample_rate; /* ucData[1]*/ 154 union { 155 uint8_t sample_size; /* for LPCM*/ 156 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 157 uint8_t max_bit_rate; 158 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 159 }; 160 }; 161 162 struct dc_edid { 163 uint32_t length; 164 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 165 }; 166 167 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 168 * is used. In this case we assume speaker location are: front left, front 169 * right and front center. */ 170 #define DEFAULT_SPEAKER_LOCATION 5 171 172 #define DC_MAX_AUDIO_DESC_COUNT 16 173 174 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 175 176 union display_content_support { 177 unsigned int raw; 178 struct { 179 unsigned int valid_content_type :1; 180 unsigned int game_content :1; 181 unsigned int cinema_content :1; 182 unsigned int photo_content :1; 183 unsigned int graphics_content :1; 184 unsigned int reserved :27; 185 } bits; 186 }; 187 188 struct dc_panel_patch { 189 unsigned int dppowerup_delay; 190 unsigned int extra_t12_ms; 191 unsigned int extra_delay_backlight_off; 192 unsigned int extra_t7_ms; 193 unsigned int skip_scdc_overwrite; 194 unsigned int delay_ignore_msa; 195 unsigned int disable_fec; 196 unsigned int extra_t3_ms; 197 unsigned int max_dsc_target_bpp_limit; 198 unsigned int skip_avmute; 199 }; 200 201 struct dc_edid_caps { 202 /* sink identification */ 203 uint16_t manufacturer_id; 204 uint16_t product_id; 205 uint32_t serial_number; 206 uint8_t manufacture_week; 207 uint8_t manufacture_year; 208 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 209 210 /* audio caps */ 211 uint8_t speaker_flags; 212 uint32_t audio_mode_count; 213 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 214 uint32_t audio_latency; 215 uint32_t video_latency; 216 217 union display_content_support content_support; 218 219 uint8_t qs_bit; 220 uint8_t qy_bit; 221 222 uint32_t max_tmds_clk_mhz; 223 224 /*HDMI 2.0 caps*/ 225 bool lte_340mcsc_scramble; 226 227 bool edid_hdmi; 228 bool hdr_supported; 229 230 struct dc_panel_patch panel_patch; 231 }; 232 233 struct dc_mode_flags { 234 /* note: part of refresh rate flag*/ 235 uint32_t INTERLACE :1; 236 /* native display timing*/ 237 uint32_t NATIVE :1; 238 /* preferred is the recommended mode, one per display */ 239 uint32_t PREFERRED :1; 240 /* true if this mode should use reduced blanking timings 241 *_not_ related to the Reduced Blanking adjustment*/ 242 uint32_t REDUCED_BLANKING :1; 243 /* note: part of refreshrate flag*/ 244 uint32_t VIDEO_OPTIMIZED_RATE :1; 245 /* should be reported to upper layers as mode_flags*/ 246 uint32_t PACKED_PIXEL_FORMAT :1; 247 /*< preferred view*/ 248 uint32_t PREFERRED_VIEW :1; 249 /* this timing should be used only in tiled mode*/ 250 uint32_t TILED_MODE :1; 251 uint32_t DSE_MODE :1; 252 /* Refresh rate divider when Miracast sink is using a 253 different rate than the output display device 254 Must be zero for wired displays and non-zero for 255 Miracast displays*/ 256 uint32_t MIRACAST_REFRESH_DIVIDER; 257 }; 258 259 260 enum dc_timing_source { 261 TIMING_SOURCE_UNDEFINED, 262 263 /* explicitly specifed by user, most important*/ 264 TIMING_SOURCE_USER_FORCED, 265 TIMING_SOURCE_USER_OVERRIDE, 266 TIMING_SOURCE_CUSTOM, 267 TIMING_SOURCE_EXPLICIT, 268 269 /* explicitly specified by the display device, more important*/ 270 TIMING_SOURCE_EDID_CEA_SVD_3D, 271 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 272 TIMING_SOURCE_EDID_CEA_SVD_420, 273 TIMING_SOURCE_EDID_DETAILED, 274 TIMING_SOURCE_EDID_ESTABLISHED, 275 TIMING_SOURCE_EDID_STANDARD, 276 TIMING_SOURCE_EDID_CEA_SVD, 277 TIMING_SOURCE_EDID_CVT_3BYTE, 278 TIMING_SOURCE_EDID_4BYTE, 279 TIMING_SOURCE_VBIOS, 280 TIMING_SOURCE_CV, 281 TIMING_SOURCE_TV, 282 TIMING_SOURCE_HDMI_VIC, 283 284 /* implicitly specified by display device, still safe but less important*/ 285 TIMING_SOURCE_DEFAULT, 286 287 /* only used for custom base modes */ 288 TIMING_SOURCE_CUSTOM_BASE, 289 290 /* these timing might not work, least important*/ 291 TIMING_SOURCE_RANGELIMIT, 292 TIMING_SOURCE_OS_FORCED, 293 TIMING_SOURCE_IMPLICIT, 294 295 /* only used by default mode list*/ 296 TIMING_SOURCE_BASICMODE, 297 298 TIMING_SOURCE_COUNT 299 }; 300 301 302 struct stereo_3d_features { 303 bool supported ; 304 bool allTimings ; 305 bool cloneMode ; 306 bool scaling ; 307 bool singleFrameSWPacked; 308 }; 309 310 enum dc_timing_support_method { 311 TIMING_SUPPORT_METHOD_UNDEFINED, 312 TIMING_SUPPORT_METHOD_EXPLICIT, 313 TIMING_SUPPORT_METHOD_IMPLICIT, 314 TIMING_SUPPORT_METHOD_NATIVE 315 }; 316 317 struct dc_mode_info { 318 uint32_t pixel_width; 319 uint32_t pixel_height; 320 uint32_t field_rate; 321 /* Vertical refresh rate for progressive modes. 322 * Field rate for interlaced modes.*/ 323 324 enum dc_timing_standard timing_standard; 325 enum dc_timing_source timing_source; 326 struct dc_mode_flags flags; 327 }; 328 329 enum dc_power_state { 330 DC_POWER_STATE_ON = 1, 331 DC_POWER_STATE_STANDBY, 332 DC_POWER_STATE_SUSPEND, 333 DC_POWER_STATE_OFF 334 }; 335 336 /* DC PowerStates */ 337 enum dc_video_power_state { 338 DC_VIDEO_POWER_UNSPECIFIED = 0, 339 DC_VIDEO_POWER_ON = 1, 340 DC_VIDEO_POWER_STANDBY, 341 DC_VIDEO_POWER_SUSPEND, 342 DC_VIDEO_POWER_OFF, 343 DC_VIDEO_POWER_HIBERNATE, 344 DC_VIDEO_POWER_SHUTDOWN, 345 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 346 DC_VIDEO_POWER_AFTER_RESET, 347 DC_VIDEO_POWER_MAXIMUM 348 }; 349 350 enum dc_acpi_cm_power_state { 351 DC_ACPI_CM_POWER_STATE_D0 = 1, 352 DC_ACPI_CM_POWER_STATE_D1 = 2, 353 DC_ACPI_CM_POWER_STATE_D2 = 4, 354 DC_ACPI_CM_POWER_STATE_D3 = 8 355 }; 356 357 enum dc_connection_type { 358 dc_connection_none, 359 dc_connection_single, 360 dc_connection_mst_branch, 361 dc_connection_sst_branch 362 }; 363 364 struct dc_csc_adjustments { 365 struct fixed31_32 contrast; 366 struct fixed31_32 saturation; 367 struct fixed31_32 brightness; 368 struct fixed31_32 hue; 369 }; 370 371 enum dpcd_downstream_port_max_bpc { 372 DOWN_STREAM_MAX_8BPC = 0, 373 DOWN_STREAM_MAX_10BPC, 374 DOWN_STREAM_MAX_12BPC, 375 DOWN_STREAM_MAX_16BPC 376 }; 377 378 379 enum link_training_offset { 380 DPRX = 0, 381 LTTPR_PHY_REPEATER1 = 1, 382 LTTPR_PHY_REPEATER2 = 2, 383 LTTPR_PHY_REPEATER3 = 3, 384 LTTPR_PHY_REPEATER4 = 4, 385 LTTPR_PHY_REPEATER5 = 5, 386 LTTPR_PHY_REPEATER6 = 6, 387 LTTPR_PHY_REPEATER7 = 7, 388 LTTPR_PHY_REPEATER8 = 8 389 }; 390 391 struct dc_lttpr_caps { 392 union dpcd_rev revision; 393 uint8_t mode; 394 uint8_t max_lane_count; 395 uint8_t max_link_rate; 396 uint8_t phy_repeater_cnt; 397 uint8_t max_ext_timeout; 398 #if defined(CONFIG_DRM_AMD_DC_DCN) 399 union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; 400 union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; 401 #endif 402 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 403 }; 404 405 #if defined(CONFIG_DRM_AMD_DC_DCN) 406 struct dc_dongle_dfp_cap_ext { 407 bool supported; 408 uint16_t max_pixel_rate_in_mps; 409 uint16_t max_video_h_active_width; 410 uint16_t max_video_v_active_height; 411 struct dp_encoding_format_caps encoding_format_caps; 412 struct dp_color_depth_caps rgb_color_depth_caps; 413 struct dp_color_depth_caps ycbcr444_color_depth_caps; 414 struct dp_color_depth_caps ycbcr422_color_depth_caps; 415 struct dp_color_depth_caps ycbcr420_color_depth_caps; 416 }; 417 #endif 418 419 struct dc_dongle_caps { 420 /* dongle type (DP converter, CV smart dongle) */ 421 enum display_dongle_type dongle_type; 422 bool extendedCapValid; 423 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 424 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 425 bool is_dp_hdmi_s3d_converter; 426 bool is_dp_hdmi_ycbcr422_pass_through; 427 bool is_dp_hdmi_ycbcr420_pass_through; 428 bool is_dp_hdmi_ycbcr422_converter; 429 bool is_dp_hdmi_ycbcr420_converter; 430 uint32_t dp_hdmi_max_bpc; 431 uint32_t dp_hdmi_max_pixel_clk_in_khz; 432 #if defined(CONFIG_DRM_AMD_DC_DCN) 433 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 434 #endif 435 }; 436 /* Scaling format */ 437 enum scaling_transformation { 438 SCALING_TRANSFORMATION_UNINITIALIZED, 439 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 440 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 441 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 442 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 443 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 444 SCALING_TRANSFORMATION_INVALID = 0x80000000, 445 446 /* Flag the first and last */ 447 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 448 SCALING_TRANSFORMATION_END = 449 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 450 }; 451 452 enum display_content_type { 453 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 454 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 455 DISPLAY_CONTENT_TYPE_PHOTO = 2, 456 DISPLAY_CONTENT_TYPE_CINEMA = 4, 457 DISPLAY_CONTENT_TYPE_GAME = 8 458 }; 459 460 enum cm_gamut_adjust_type { 461 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 462 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 463 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 464 }; 465 466 struct cm_grph_csc_adjustment { 467 struct fixed31_32 temperature_matrix[12]; 468 enum cm_gamut_adjust_type gamut_adjust_type; 469 enum cm_gamut_coef_format gamut_coef_format; 470 }; 471 472 /* writeback */ 473 struct dwb_stereo_params { 474 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 475 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 476 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 477 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 478 }; 479 480 struct dc_dwb_cnv_params { 481 unsigned int src_width; /* input active width */ 482 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 483 unsigned int crop_width; /* cropped window width at cnv output */ 484 bool crop_en; /* window cropping enable in cnv */ 485 unsigned int crop_height; /* cropped window height at cnv output */ 486 unsigned int crop_x; /* cropped window start x value at cnv output */ 487 unsigned int crop_y; /* cropped window start y value at cnv output */ 488 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 489 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 490 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 491 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 492 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 493 }; 494 495 struct dc_dwb_params { 496 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 497 unsigned int hdr_mult; /* must be in FP1.6.12 */ 498 struct cm_grph_csc_adjustment csc_params; 499 struct dwb_stereo_params stereo_params; 500 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 501 unsigned int dest_width; /* Destination width */ 502 unsigned int dest_height; /* Destination height */ 503 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 504 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 505 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 506 struct scaling_taps scaler_taps; /* Scaling taps */ 507 enum dwb_subsample_position subsample_position; 508 struct dc_transfer_func *out_transfer_func; 509 }; 510 511 /* audio*/ 512 513 union audio_sample_rates { 514 struct sample_rates { 515 uint8_t RATE_32:1; 516 uint8_t RATE_44_1:1; 517 uint8_t RATE_48:1; 518 uint8_t RATE_88_2:1; 519 uint8_t RATE_96:1; 520 uint8_t RATE_176_4:1; 521 uint8_t RATE_192:1; 522 } rate; 523 524 uint8_t all; 525 }; 526 527 struct audio_speaker_flags { 528 uint32_t FL_FR:1; 529 uint32_t LFE:1; 530 uint32_t FC:1; 531 uint32_t RL_RR:1; 532 uint32_t RC:1; 533 uint32_t FLC_FRC:1; 534 uint32_t RLC_RRC:1; 535 uint32_t SUPPORT_AI:1; 536 }; 537 538 struct audio_speaker_info { 539 uint32_t ALLSPEAKERS:7; 540 uint32_t SUPPORT_AI:1; 541 }; 542 543 544 struct audio_info_flags { 545 546 union { 547 548 struct audio_speaker_flags speaker_flags; 549 struct audio_speaker_info info; 550 551 uint8_t all; 552 }; 553 }; 554 555 enum audio_format_code { 556 AUDIO_FORMAT_CODE_FIRST = 1, 557 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 558 559 AUDIO_FORMAT_CODE_AC3, 560 /*Layers 1 & 2 */ 561 AUDIO_FORMAT_CODE_MPEG1, 562 /*MPEG1 Layer 3 */ 563 AUDIO_FORMAT_CODE_MP3, 564 /*multichannel */ 565 AUDIO_FORMAT_CODE_MPEG2, 566 AUDIO_FORMAT_CODE_AAC, 567 AUDIO_FORMAT_CODE_DTS, 568 AUDIO_FORMAT_CODE_ATRAC, 569 AUDIO_FORMAT_CODE_1BITAUDIO, 570 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 571 AUDIO_FORMAT_CODE_DTS_HD, 572 AUDIO_FORMAT_CODE_MAT_MLP, 573 AUDIO_FORMAT_CODE_DST, 574 AUDIO_FORMAT_CODE_WMAPRO, 575 AUDIO_FORMAT_CODE_LAST, 576 AUDIO_FORMAT_CODE_COUNT = 577 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 578 }; 579 580 struct audio_mode { 581 /* ucData[0] [6:3] */ 582 enum audio_format_code format_code; 583 /* ucData[0] [2:0] */ 584 uint8_t channel_count; 585 /* ucData[1] */ 586 union audio_sample_rates sample_rates; 587 union { 588 /* for LPCM */ 589 uint8_t sample_size; 590 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 591 uint8_t max_bit_rate; 592 /* for Audio Formats 9-15 */ 593 uint8_t vendor_specific; 594 }; 595 }; 596 597 struct audio_info { 598 struct audio_info_flags flags; 599 uint32_t video_latency; 600 uint32_t audio_latency; 601 uint32_t display_index; 602 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 603 uint32_t manufacture_id; 604 uint32_t product_id; 605 /* PortID used for ContainerID when defined */ 606 uint32_t port_id[2]; 607 uint32_t mode_count; 608 /* this field must be last in this struct */ 609 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 610 }; 611 struct audio_check { 612 unsigned int audio_packet_type; 613 unsigned int max_audiosample_rate; 614 unsigned int acat; 615 }; 616 enum dc_infoframe_type { 617 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 618 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 619 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 620 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 621 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 622 }; 623 624 struct dc_info_packet { 625 bool valid; 626 uint8_t hb0; 627 uint8_t hb1; 628 uint8_t hb2; 629 uint8_t hb3; 630 uint8_t sb[32]; 631 }; 632 633 struct dc_info_packet_128 { 634 bool valid; 635 uint8_t hb0; 636 uint8_t hb1; 637 uint8_t hb2; 638 uint8_t hb3; 639 uint8_t sb[128]; 640 }; 641 642 #define DC_PLANE_UPDATE_TIMES_MAX 10 643 644 struct dc_plane_flip_time { 645 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 646 unsigned int index; 647 unsigned int prev_update_time_in_us; 648 }; 649 650 enum dc_psr_state { 651 PSR_STATE0 = 0x0, 652 PSR_STATE1, 653 PSR_STATE1a, 654 PSR_STATE2, 655 PSR_STATE2a, 656 PSR_STATE2b, 657 PSR_STATE3, 658 PSR_STATE3Init, 659 PSR_STATE4, 660 PSR_STATE4a, 661 PSR_STATE4b, 662 PSR_STATE4c, 663 PSR_STATE4d, 664 PSR_STATE5, 665 PSR_STATE5a, 666 PSR_STATE5b, 667 PSR_STATE5c, 668 PSR_STATE_INVALID = 0xFF 669 }; 670 671 struct psr_config { 672 unsigned char psr_version; 673 unsigned int psr_rfb_setup_time; 674 bool psr_exit_link_training_required; 675 bool psr_frame_capture_indication_req; 676 unsigned int psr_sdp_transmit_line_num_deadline; 677 bool allow_smu_optimizations; 678 bool allow_multi_disp_optimizations; 679 }; 680 681 union dmcu_psr_level { 682 struct { 683 unsigned int SKIP_CRC:1; 684 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 685 unsigned int SKIP_PHY_POWER_DOWN:1; 686 unsigned int SKIP_AUX_ACK_CHECK:1; 687 unsigned int SKIP_CRTC_DISABLE:1; 688 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 689 unsigned int SKIP_SMU_NOTIFICATION:1; 690 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 691 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 692 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 693 unsigned int RESERVED:22; 694 } bits; 695 unsigned int u32all; 696 }; 697 698 enum physical_phy_id { 699 PHYLD_0, 700 PHYLD_1, 701 PHYLD_2, 702 PHYLD_3, 703 PHYLD_4, 704 PHYLD_5, 705 PHYLD_6, 706 PHYLD_7, 707 PHYLD_8, 708 PHYLD_9, 709 PHYLD_COUNT, 710 PHYLD_UNKNOWN = (-1L) 711 }; 712 713 enum phy_type { 714 PHY_TYPE_UNKNOWN = 1, 715 PHY_TYPE_PCIE_PHY = 2, 716 PHY_TYPE_UNIPHY = 3, 717 }; 718 719 struct psr_context { 720 /* ddc line */ 721 enum channel_id channel; 722 /* Transmitter id */ 723 enum transmitter transmitterId; 724 /* Engine Id is used for Dig Be source select */ 725 enum engine_id engineId; 726 /* Controller Id used for Dig Fe source select */ 727 enum controller_id controllerId; 728 /* Pcie or Uniphy */ 729 enum phy_type phyType; 730 /* Physical PHY Id used by SMU interpretation */ 731 enum physical_phy_id smuPhyId; 732 /* Vertical total pixels from crtc timing. 733 * This is used for static screen detection. 734 * ie. If we want to detect half a frame, 735 * we use this to determine the hyst lines. 736 */ 737 unsigned int crtcTimingVerticalTotal; 738 /* PSR supported from panel capabilities and 739 * current display configuration 740 */ 741 bool psrSupportedDisplayConfig; 742 /* Whether fast link training is supported by the panel */ 743 bool psrExitLinkTrainingRequired; 744 /* If RFB setup time is greater than the total VBLANK time, 745 * it is not possible for the sink to capture the video frame 746 * in the same frame the SDP is sent. In this case, 747 * the frame capture indication bit should be set and an extra 748 * static frame should be transmitted to the sink. 749 */ 750 bool psrFrameCaptureIndicationReq; 751 /* Set the last possible line SDP may be transmitted without violating 752 * the RFB setup time or entering the active video frame. 753 */ 754 unsigned int sdpTransmitLineNumDeadline; 755 /* The VSync rate in Hz used to calculate the 756 * step size for smooth brightness feature 757 */ 758 unsigned int vsync_rate_hz; 759 unsigned int skipPsrWaitForPllLock; 760 unsigned int numberOfControllers; 761 /* Unused, for future use. To indicate that first changed frame from 762 * state3 shouldn't result in psr_inactive, but rather to perform 763 * an automatic single frame rfb_update. 764 */ 765 bool rfb_update_auto_en; 766 /* Number of frame before entering static screen */ 767 unsigned int timehyst_frames; 768 /* Partial frames before entering static screen */ 769 unsigned int hyst_lines; 770 /* # of repeated AUX transaction attempts to make before 771 * indicating failure to the driver 772 */ 773 unsigned int aux_repeats; 774 /* Controls hw blocks to power down during PSR active state */ 775 union dmcu_psr_level psr_level; 776 /* Controls additional delay after remote frame capture before 777 * continuing powerd own 778 */ 779 unsigned int frame_delay; 780 bool allow_smu_optimizations; 781 bool allow_multi_disp_optimizations; 782 }; 783 784 struct colorspace_transform { 785 struct fixed31_32 matrix[12]; 786 bool enable_remap; 787 }; 788 789 enum i2c_mot_mode { 790 I2C_MOT_UNDEF, 791 I2C_MOT_TRUE, 792 I2C_MOT_FALSE 793 }; 794 795 struct AsicStateEx { 796 unsigned int memoryClock; 797 unsigned int displayClock; 798 unsigned int engineClock; 799 unsigned int maxSupportedDppClock; 800 unsigned int dppClock; 801 unsigned int socClock; 802 unsigned int dcfClockDeepSleep; 803 unsigned int fClock; 804 unsigned int phyClock; 805 }; 806 807 808 enum dc_clock_type { 809 DC_CLOCK_TYPE_DISPCLK = 0, 810 DC_CLOCK_TYPE_DPPCLK = 1, 811 }; 812 813 struct dc_clock_config { 814 uint32_t max_clock_khz; 815 uint32_t min_clock_khz; 816 uint32_t bw_requirequired_clock_khz; 817 uint32_t current_clock_khz;/*current clock in use*/ 818 }; 819 820 struct hw_asic_id { 821 uint32_t chip_id; 822 uint32_t chip_family; 823 uint32_t pci_revision_id; 824 uint32_t hw_internal_rev; 825 uint32_t vram_type; 826 uint32_t vram_width; 827 uint32_t feature_flags; 828 uint32_t fake_paths_num; 829 void *atombios_base_address; 830 }; 831 832 struct dc_context { 833 struct dc *dc; 834 835 void *driver_context; /* e.g. amdgpu_device */ 836 struct dc_perf_trace *perf_trace; 837 void *cgs_device; 838 839 enum dce_environment dce_environment; 840 struct hw_asic_id asic_id; 841 842 /* todo: below should probably move to dc. to facilitate removal 843 * of AS we will store these here 844 */ 845 enum dce_version dce_version; 846 struct dc_bios *dc_bios; 847 bool created_bios; 848 struct gpio_service *gpio_service; 849 uint32_t dc_sink_id_count; 850 uint32_t dc_stream_id_count; 851 uint32_t dc_edp_id_count; 852 uint64_t fbc_gpu_addr; 853 struct dc_dmub_srv *dmub_srv; 854 #ifdef CONFIG_DRM_AMD_DC_HDCP 855 struct cp_psp cp_psp; 856 #endif 857 858 }; 859 860 /* DSC DPCD capabilities */ 861 union dsc_slice_caps1 { 862 struct { 863 uint8_t NUM_SLICES_1 : 1; 864 uint8_t NUM_SLICES_2 : 1; 865 uint8_t RESERVED : 1; 866 uint8_t NUM_SLICES_4 : 1; 867 uint8_t NUM_SLICES_6 : 1; 868 uint8_t NUM_SLICES_8 : 1; 869 uint8_t NUM_SLICES_10 : 1; 870 uint8_t NUM_SLICES_12 : 1; 871 } bits; 872 uint8_t raw; 873 }; 874 875 union dsc_slice_caps2 { 876 struct { 877 uint8_t NUM_SLICES_16 : 1; 878 uint8_t NUM_SLICES_20 : 1; 879 uint8_t NUM_SLICES_24 : 1; 880 uint8_t RESERVED : 5; 881 } bits; 882 uint8_t raw; 883 }; 884 885 union dsc_color_formats { 886 struct { 887 uint8_t RGB : 1; 888 uint8_t YCBCR_444 : 1; 889 uint8_t YCBCR_SIMPLE_422 : 1; 890 uint8_t YCBCR_NATIVE_422 : 1; 891 uint8_t YCBCR_NATIVE_420 : 1; 892 uint8_t RESERVED : 3; 893 } bits; 894 uint8_t raw; 895 }; 896 897 union dsc_color_depth { 898 struct { 899 uint8_t RESERVED1 : 1; 900 uint8_t COLOR_DEPTH_8_BPC : 1; 901 uint8_t COLOR_DEPTH_10_BPC : 1; 902 uint8_t COLOR_DEPTH_12_BPC : 1; 903 uint8_t RESERVED2 : 3; 904 } bits; 905 uint8_t raw; 906 }; 907 908 struct dsc_dec_dpcd_caps { 909 bool is_dsc_supported; 910 uint8_t dsc_version; 911 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 912 union dsc_slice_caps1 slice_caps1; 913 union dsc_slice_caps2 slice_caps2; 914 int32_t lb_bit_depth; 915 bool is_block_pred_supported; 916 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 917 union dsc_color_formats color_formats; 918 union dsc_color_depth color_depth; 919 int32_t throughput_mode_0_mps; /* In MPs */ 920 int32_t throughput_mode_1_mps; /* In MPs */ 921 int32_t max_slice_width; 922 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 923 924 /* Extended DSC caps */ 925 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 926 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 927 uint32_t branch_max_line_width; 928 bool is_dp; 929 }; 930 931 struct dc_golden_table { 932 uint16_t dc_golden_table_ver; 933 uint32_t aux_dphy_rx_control0_val; 934 uint32_t aux_dphy_tx_control_val; 935 uint32_t aux_dphy_rx_control1_val; 936 uint32_t dc_gpio_aux_ctrl_0_val; 937 uint32_t dc_gpio_aux_ctrl_1_val; 938 uint32_t dc_gpio_aux_ctrl_2_val; 939 uint32_t dc_gpio_aux_ctrl_3_val; 940 uint32_t dc_gpio_aux_ctrl_4_val; 941 uint32_t dc_gpio_aux_ctrl_5_val; 942 }; 943 944 enum dc_gpu_mem_alloc_type { 945 DC_MEM_ALLOC_TYPE_GART, 946 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 947 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 948 DC_MEM_ALLOC_TYPE_AGP 949 }; 950 951 enum dc_psr_version { 952 DC_PSR_VERSION_1 = 0, 953 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 954 }; 955 956 /* Possible values of display_endpoint_id.endpoint */ 957 enum display_endpoint_type { 958 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 959 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 960 DISPLAY_ENDPOINT_UNKNOWN = -1 961 }; 962 963 /* Extends graphics_object_id with an additional member 'ep_type' for 964 * distinguishing between physical endpoints (with entries in BIOS connector table) and 965 * logical endpoints. 966 */ 967 struct display_endpoint_id { 968 struct graphics_object_id link_id; 969 enum display_endpoint_type ep_type; 970 }; 971 972 #endif /* DC_TYPES_H_ */ 973