1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 /* Note: use these macro definitions instead of direct comparison! */ 73 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ 74 (dce_environment == DCE_ENV_FPGA_MAXIMUS) 75 76 #define IS_DIAG_DC(dce_environment) \ 77 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) 78 79 struct dc_perf_trace { 80 unsigned long read_count; 81 unsigned long write_count; 82 unsigned long last_entry_read; 83 unsigned long last_entry_write; 84 }; 85 86 #define MAX_SURFACE_NUM 4 87 #define NUM_PIXEL_FORMATS 10 88 89 enum tiling_mode { 90 TILING_MODE_INVALID, 91 TILING_MODE_LINEAR, 92 TILING_MODE_TILED, 93 TILING_MODE_COUNT 94 }; 95 96 enum view_3d_format { 97 VIEW_3D_FORMAT_NONE = 0, 98 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 99 VIEW_3D_FORMAT_SIDE_BY_SIDE, 100 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 101 VIEW_3D_FORMAT_COUNT, 102 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 103 }; 104 105 enum plane_stereo_format { 106 PLANE_STEREO_FORMAT_NONE = 0, 107 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 108 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 109 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 110 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 111 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 112 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 113 }; 114 115 /* TODO: Find way to calculate number of bits 116 * Please increase if pixel_format enum increases 117 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 118 */ 119 120 enum dc_edid_connector_type { 121 DC_EDID_CONNECTOR_UNKNOWN = 0, 122 DC_EDID_CONNECTOR_ANALOG = 1, 123 DC_EDID_CONNECTOR_DIGITAL = 10, 124 DC_EDID_CONNECTOR_DVI = 11, 125 DC_EDID_CONNECTOR_HDMIA = 12, 126 DC_EDID_CONNECTOR_MDDI = 14, 127 DC_EDID_CONNECTOR_DISPLAYPORT = 15 128 }; 129 130 enum dc_edid_status { 131 EDID_OK, 132 EDID_BAD_INPUT, 133 EDID_NO_RESPONSE, 134 EDID_BAD_CHECKSUM, 135 EDID_THE_SAME, 136 EDID_FALL_BACK, 137 EDID_PARTIAL_VALID, 138 }; 139 140 enum act_return_status { 141 ACT_SUCCESS, 142 ACT_LINK_LOST, 143 ACT_FAILED 144 }; 145 146 /* audio capability from EDID*/ 147 struct dc_cea_audio_mode { 148 uint8_t format_code; /* ucData[0] [6:3]*/ 149 uint8_t channel_count; /* ucData[0] [2:0]*/ 150 uint8_t sample_rate; /* ucData[1]*/ 151 union { 152 uint8_t sample_size; /* for LPCM*/ 153 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 154 uint8_t max_bit_rate; 155 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 156 }; 157 }; 158 159 struct dc_edid { 160 uint32_t length; 161 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 162 }; 163 164 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 165 * is used. In this case we assume speaker location are: front left, front 166 * right and front center. */ 167 #define DEFAULT_SPEAKER_LOCATION 5 168 169 #define DC_MAX_AUDIO_DESC_COUNT 16 170 171 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 172 173 union display_content_support { 174 unsigned int raw; 175 struct { 176 unsigned int valid_content_type :1; 177 unsigned int game_content :1; 178 unsigned int cinema_content :1; 179 unsigned int photo_content :1; 180 unsigned int graphics_content :1; 181 unsigned int reserved :27; 182 } bits; 183 }; 184 185 struct dc_panel_patch { 186 unsigned int dppowerup_delay; 187 unsigned int extra_t12_ms; 188 unsigned int extra_delay_backlight_off; 189 unsigned int extra_t7_ms; 190 unsigned int skip_scdc_overwrite; 191 unsigned int delay_ignore_msa; 192 unsigned int disable_fec; 193 unsigned int extra_t3_ms; 194 unsigned int max_dsc_target_bpp_limit; 195 unsigned int embedded_tiled_slave; 196 unsigned int disable_fams; 197 unsigned int skip_avmute; 198 unsigned int mst_start_top_delay; 199 }; 200 201 struct dc_edid_caps { 202 /* sink identification */ 203 uint16_t manufacturer_id; 204 uint16_t product_id; 205 uint32_t serial_number; 206 uint8_t manufacture_week; 207 uint8_t manufacture_year; 208 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 209 210 /* audio caps */ 211 uint8_t speaker_flags; 212 uint32_t audio_mode_count; 213 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 214 uint32_t audio_latency; 215 uint32_t video_latency; 216 217 union display_content_support content_support; 218 219 uint8_t qs_bit; 220 uint8_t qy_bit; 221 222 uint32_t max_tmds_clk_mhz; 223 224 /*HDMI 2.0 caps*/ 225 bool lte_340mcsc_scramble; 226 227 bool edid_hdmi; 228 bool hdr_supported; 229 230 struct dc_panel_patch panel_patch; 231 }; 232 233 struct dc_mode_flags { 234 /* note: part of refresh rate flag*/ 235 uint32_t INTERLACE :1; 236 /* native display timing*/ 237 uint32_t NATIVE :1; 238 /* preferred is the recommended mode, one per display */ 239 uint32_t PREFERRED :1; 240 /* true if this mode should use reduced blanking timings 241 *_not_ related to the Reduced Blanking adjustment*/ 242 uint32_t REDUCED_BLANKING :1; 243 /* note: part of refreshrate flag*/ 244 uint32_t VIDEO_OPTIMIZED_RATE :1; 245 /* should be reported to upper layers as mode_flags*/ 246 uint32_t PACKED_PIXEL_FORMAT :1; 247 /*< preferred view*/ 248 uint32_t PREFERRED_VIEW :1; 249 /* this timing should be used only in tiled mode*/ 250 uint32_t TILED_MODE :1; 251 uint32_t DSE_MODE :1; 252 /* Refresh rate divider when Miracast sink is using a 253 different rate than the output display device 254 Must be zero for wired displays and non-zero for 255 Miracast displays*/ 256 uint32_t MIRACAST_REFRESH_DIVIDER; 257 }; 258 259 260 enum dc_timing_source { 261 TIMING_SOURCE_UNDEFINED, 262 263 /* explicitly specifed by user, most important*/ 264 TIMING_SOURCE_USER_FORCED, 265 TIMING_SOURCE_USER_OVERRIDE, 266 TIMING_SOURCE_CUSTOM, 267 TIMING_SOURCE_EXPLICIT, 268 269 /* explicitly specified by the display device, more important*/ 270 TIMING_SOURCE_EDID_CEA_SVD_3D, 271 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 272 TIMING_SOURCE_EDID_CEA_SVD_420, 273 TIMING_SOURCE_EDID_DETAILED, 274 TIMING_SOURCE_EDID_ESTABLISHED, 275 TIMING_SOURCE_EDID_STANDARD, 276 TIMING_SOURCE_EDID_CEA_SVD, 277 TIMING_SOURCE_EDID_CVT_3BYTE, 278 TIMING_SOURCE_EDID_4BYTE, 279 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 280 TIMING_SOURCE_EDID_CEA_RID, 281 TIMING_SOURCE_VBIOS, 282 TIMING_SOURCE_CV, 283 TIMING_SOURCE_TV, 284 TIMING_SOURCE_HDMI_VIC, 285 286 /* implicitly specified by display device, still safe but less important*/ 287 TIMING_SOURCE_DEFAULT, 288 289 /* only used for custom base modes */ 290 TIMING_SOURCE_CUSTOM_BASE, 291 292 /* these timing might not work, least important*/ 293 TIMING_SOURCE_RANGELIMIT, 294 TIMING_SOURCE_OS_FORCED, 295 TIMING_SOURCE_IMPLICIT, 296 297 /* only used by default mode list*/ 298 TIMING_SOURCE_BASICMODE, 299 300 TIMING_SOURCE_COUNT 301 }; 302 303 304 struct stereo_3d_features { 305 bool supported ; 306 bool allTimings ; 307 bool cloneMode ; 308 bool scaling ; 309 bool singleFrameSWPacked; 310 }; 311 312 enum dc_timing_support_method { 313 TIMING_SUPPORT_METHOD_UNDEFINED, 314 TIMING_SUPPORT_METHOD_EXPLICIT, 315 TIMING_SUPPORT_METHOD_IMPLICIT, 316 TIMING_SUPPORT_METHOD_NATIVE 317 }; 318 319 struct dc_mode_info { 320 uint32_t pixel_width; 321 uint32_t pixel_height; 322 uint32_t field_rate; 323 /* Vertical refresh rate for progressive modes. 324 * Field rate for interlaced modes.*/ 325 326 enum dc_timing_standard timing_standard; 327 enum dc_timing_source timing_source; 328 struct dc_mode_flags flags; 329 }; 330 331 enum dc_power_state { 332 DC_POWER_STATE_ON = 1, 333 DC_POWER_STATE_STANDBY, 334 DC_POWER_STATE_SUSPEND, 335 DC_POWER_STATE_OFF 336 }; 337 338 /* DC PowerStates */ 339 enum dc_video_power_state { 340 DC_VIDEO_POWER_UNSPECIFIED = 0, 341 DC_VIDEO_POWER_ON = 1, 342 DC_VIDEO_POWER_STANDBY, 343 DC_VIDEO_POWER_SUSPEND, 344 DC_VIDEO_POWER_OFF, 345 DC_VIDEO_POWER_HIBERNATE, 346 DC_VIDEO_POWER_SHUTDOWN, 347 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 348 DC_VIDEO_POWER_AFTER_RESET, 349 DC_VIDEO_POWER_MAXIMUM 350 }; 351 352 enum dc_acpi_cm_power_state { 353 DC_ACPI_CM_POWER_STATE_D0 = 1, 354 DC_ACPI_CM_POWER_STATE_D1 = 2, 355 DC_ACPI_CM_POWER_STATE_D2 = 4, 356 DC_ACPI_CM_POWER_STATE_D3 = 8 357 }; 358 359 enum dc_connection_type { 360 dc_connection_none, 361 dc_connection_single, 362 dc_connection_mst_branch, 363 dc_connection_sst_branch 364 }; 365 366 struct dc_csc_adjustments { 367 struct fixed31_32 contrast; 368 struct fixed31_32 saturation; 369 struct fixed31_32 brightness; 370 struct fixed31_32 hue; 371 }; 372 373 /* Scaling format */ 374 enum scaling_transformation { 375 SCALING_TRANSFORMATION_UNINITIALIZED, 376 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 377 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 378 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 379 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 380 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 381 SCALING_TRANSFORMATION_INVALID = 0x80000000, 382 383 /* Flag the first and last */ 384 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 385 SCALING_TRANSFORMATION_END = 386 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 387 }; 388 389 enum display_content_type { 390 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 391 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 392 DISPLAY_CONTENT_TYPE_PHOTO = 2, 393 DISPLAY_CONTENT_TYPE_CINEMA = 4, 394 DISPLAY_CONTENT_TYPE_GAME = 8 395 }; 396 397 enum cm_gamut_adjust_type { 398 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 399 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 400 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 401 }; 402 403 struct cm_grph_csc_adjustment { 404 struct fixed31_32 temperature_matrix[12]; 405 enum cm_gamut_adjust_type gamut_adjust_type; 406 enum cm_gamut_coef_format gamut_coef_format; 407 }; 408 409 /* writeback */ 410 struct dwb_stereo_params { 411 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 412 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 413 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 414 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 415 }; 416 417 struct dc_dwb_cnv_params { 418 unsigned int src_width; /* input active width */ 419 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 420 unsigned int crop_width; /* cropped window width at cnv output */ 421 bool crop_en; /* window cropping enable in cnv */ 422 unsigned int crop_height; /* cropped window height at cnv output */ 423 unsigned int crop_x; /* cropped window start x value at cnv output */ 424 unsigned int crop_y; /* cropped window start y value at cnv output */ 425 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 426 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 427 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 428 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 429 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 430 }; 431 432 struct dc_dwb_params { 433 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 434 unsigned int hdr_mult; /* must be in FP1.6.12 */ 435 struct cm_grph_csc_adjustment csc_params; 436 struct dwb_stereo_params stereo_params; 437 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 438 unsigned int dest_width; /* Destination width */ 439 unsigned int dest_height; /* Destination height */ 440 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 441 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 442 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 443 struct scaling_taps scaler_taps; /* Scaling taps */ 444 enum dwb_subsample_position subsample_position; 445 struct dc_transfer_func *out_transfer_func; 446 }; 447 448 /* audio*/ 449 450 union audio_sample_rates { 451 struct sample_rates { 452 uint8_t RATE_32:1; 453 uint8_t RATE_44_1:1; 454 uint8_t RATE_48:1; 455 uint8_t RATE_88_2:1; 456 uint8_t RATE_96:1; 457 uint8_t RATE_176_4:1; 458 uint8_t RATE_192:1; 459 } rate; 460 461 uint8_t all; 462 }; 463 464 struct audio_speaker_flags { 465 uint32_t FL_FR:1; 466 uint32_t LFE:1; 467 uint32_t FC:1; 468 uint32_t RL_RR:1; 469 uint32_t RC:1; 470 uint32_t FLC_FRC:1; 471 uint32_t RLC_RRC:1; 472 uint32_t SUPPORT_AI:1; 473 }; 474 475 struct audio_speaker_info { 476 uint32_t ALLSPEAKERS:7; 477 uint32_t SUPPORT_AI:1; 478 }; 479 480 481 struct audio_info_flags { 482 483 union { 484 485 struct audio_speaker_flags speaker_flags; 486 struct audio_speaker_info info; 487 488 uint8_t all; 489 }; 490 }; 491 492 enum audio_format_code { 493 AUDIO_FORMAT_CODE_FIRST = 1, 494 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 495 496 AUDIO_FORMAT_CODE_AC3, 497 /*Layers 1 & 2 */ 498 AUDIO_FORMAT_CODE_MPEG1, 499 /*MPEG1 Layer 3 */ 500 AUDIO_FORMAT_CODE_MP3, 501 /*multichannel */ 502 AUDIO_FORMAT_CODE_MPEG2, 503 AUDIO_FORMAT_CODE_AAC, 504 AUDIO_FORMAT_CODE_DTS, 505 AUDIO_FORMAT_CODE_ATRAC, 506 AUDIO_FORMAT_CODE_1BITAUDIO, 507 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 508 AUDIO_FORMAT_CODE_DTS_HD, 509 AUDIO_FORMAT_CODE_MAT_MLP, 510 AUDIO_FORMAT_CODE_DST, 511 AUDIO_FORMAT_CODE_WMAPRO, 512 AUDIO_FORMAT_CODE_LAST, 513 AUDIO_FORMAT_CODE_COUNT = 514 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 515 }; 516 517 struct audio_mode { 518 /* ucData[0] [6:3] */ 519 enum audio_format_code format_code; 520 /* ucData[0] [2:0] */ 521 uint8_t channel_count; 522 /* ucData[1] */ 523 union audio_sample_rates sample_rates; 524 union { 525 /* for LPCM */ 526 uint8_t sample_size; 527 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 528 uint8_t max_bit_rate; 529 /* for Audio Formats 9-15 */ 530 uint8_t vendor_specific; 531 }; 532 }; 533 534 struct audio_info { 535 struct audio_info_flags flags; 536 uint32_t video_latency; 537 uint32_t audio_latency; 538 uint32_t display_index; 539 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 540 uint32_t manufacture_id; 541 uint32_t product_id; 542 /* PortID used for ContainerID when defined */ 543 uint32_t port_id[2]; 544 uint32_t mode_count; 545 /* this field must be last in this struct */ 546 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 547 }; 548 struct audio_check { 549 unsigned int audio_packet_type; 550 unsigned int max_audiosample_rate; 551 unsigned int acat; 552 }; 553 enum dc_infoframe_type { 554 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 555 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 556 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 557 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 558 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 559 }; 560 561 struct dc_info_packet { 562 bool valid; 563 uint8_t hb0; 564 uint8_t hb1; 565 uint8_t hb2; 566 uint8_t hb3; 567 uint8_t sb[32]; 568 }; 569 570 struct dc_info_packet_128 { 571 bool valid; 572 uint8_t hb0; 573 uint8_t hb1; 574 uint8_t hb2; 575 uint8_t hb3; 576 uint8_t sb[128]; 577 }; 578 579 #define DC_PLANE_UPDATE_TIMES_MAX 10 580 581 struct dc_plane_flip_time { 582 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 583 unsigned int index; 584 unsigned int prev_update_time_in_us; 585 }; 586 587 enum dc_psr_state { 588 PSR_STATE0 = 0x0, 589 PSR_STATE1, 590 PSR_STATE1a, 591 PSR_STATE2, 592 PSR_STATE2a, 593 PSR_STATE2b, 594 PSR_STATE3, 595 PSR_STATE3Init, 596 PSR_STATE4, 597 PSR_STATE4a, 598 PSR_STATE4b, 599 PSR_STATE4c, 600 PSR_STATE4d, 601 PSR_STATE4_FULL_FRAME, 602 PSR_STATE4a_FULL_FRAME, 603 PSR_STATE4b_FULL_FRAME, 604 PSR_STATE4c_FULL_FRAME, 605 PSR_STATE4_FULL_FRAME_POWERUP, 606 PSR_STATE5, 607 PSR_STATE5a, 608 PSR_STATE5b, 609 PSR_STATE5c, 610 PSR_STATE_HWLOCK_MGR, 611 PSR_STATE_POLLVUPDATE, 612 PSR_STATE_INVALID = 0xFF 613 }; 614 615 struct psr_config { 616 unsigned char psr_version; 617 unsigned int psr_rfb_setup_time; 618 bool psr_exit_link_training_required; 619 bool psr_frame_capture_indication_req; 620 unsigned int psr_sdp_transmit_line_num_deadline; 621 bool allow_smu_optimizations; 622 bool allow_multi_disp_optimizations; 623 /* Panel self refresh 2 selective update granularity required */ 624 bool su_granularity_required; 625 /* psr2 selective update y granularity capability */ 626 uint8_t su_y_granularity; 627 unsigned int line_time_in_us; 628 uint8_t rate_control_caps; 629 uint16_t dsc_slice_height; 630 }; 631 632 union dmcu_psr_level { 633 struct { 634 unsigned int SKIP_CRC:1; 635 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 636 unsigned int SKIP_PHY_POWER_DOWN:1; 637 unsigned int SKIP_AUX_ACK_CHECK:1; 638 unsigned int SKIP_CRTC_DISABLE:1; 639 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 640 unsigned int SKIP_SMU_NOTIFICATION:1; 641 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 642 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 643 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 644 unsigned int DISABLE_ALPM:1; 645 unsigned int ALPM_DEFAULT_PD_MODE:1; 646 unsigned int RESERVED:20; 647 } bits; 648 unsigned int u32all; 649 }; 650 651 enum physical_phy_id { 652 PHYLD_0, 653 PHYLD_1, 654 PHYLD_2, 655 PHYLD_3, 656 PHYLD_4, 657 PHYLD_5, 658 PHYLD_6, 659 PHYLD_7, 660 PHYLD_8, 661 PHYLD_9, 662 PHYLD_COUNT, 663 PHYLD_UNKNOWN = (-1L) 664 }; 665 666 enum phy_type { 667 PHY_TYPE_UNKNOWN = 1, 668 PHY_TYPE_PCIE_PHY = 2, 669 PHY_TYPE_UNIPHY = 3, 670 }; 671 672 struct psr_context { 673 /* ddc line */ 674 enum channel_id channel; 675 /* Transmitter id */ 676 enum transmitter transmitterId; 677 /* Engine Id is used for Dig Be source select */ 678 enum engine_id engineId; 679 /* Controller Id used for Dig Fe source select */ 680 enum controller_id controllerId; 681 /* Pcie or Uniphy */ 682 enum phy_type phyType; 683 /* Physical PHY Id used by SMU interpretation */ 684 enum physical_phy_id smuPhyId; 685 /* Vertical total pixels from crtc timing. 686 * This is used for static screen detection. 687 * ie. If we want to detect half a frame, 688 * we use this to determine the hyst lines. 689 */ 690 unsigned int crtcTimingVerticalTotal; 691 /* PSR supported from panel capabilities and 692 * current display configuration 693 */ 694 bool psrSupportedDisplayConfig; 695 /* Whether fast link training is supported by the panel */ 696 bool psrExitLinkTrainingRequired; 697 /* If RFB setup time is greater than the total VBLANK time, 698 * it is not possible for the sink to capture the video frame 699 * in the same frame the SDP is sent. In this case, 700 * the frame capture indication bit should be set and an extra 701 * static frame should be transmitted to the sink. 702 */ 703 bool psrFrameCaptureIndicationReq; 704 /* Set the last possible line SDP may be transmitted without violating 705 * the RFB setup time or entering the active video frame. 706 */ 707 unsigned int sdpTransmitLineNumDeadline; 708 /* The VSync rate in Hz used to calculate the 709 * step size for smooth brightness feature 710 */ 711 unsigned int vsync_rate_hz; 712 unsigned int skipPsrWaitForPllLock; 713 unsigned int numberOfControllers; 714 /* Unused, for future use. To indicate that first changed frame from 715 * state3 shouldn't result in psr_inactive, but rather to perform 716 * an automatic single frame rfb_update. 717 */ 718 bool rfb_update_auto_en; 719 /* Number of frame before entering static screen */ 720 unsigned int timehyst_frames; 721 /* Partial frames before entering static screen */ 722 unsigned int hyst_lines; 723 /* # of repeated AUX transaction attempts to make before 724 * indicating failure to the driver 725 */ 726 unsigned int aux_repeats; 727 /* Controls hw blocks to power down during PSR active state */ 728 union dmcu_psr_level psr_level; 729 /* Controls additional delay after remote frame capture before 730 * continuing powerd own 731 */ 732 unsigned int frame_delay; 733 bool allow_smu_optimizations; 734 bool allow_multi_disp_optimizations; 735 /* Panel self refresh 2 selective update granularity required */ 736 bool su_granularity_required; 737 /* psr2 selective update y granularity capability */ 738 uint8_t su_y_granularity; 739 unsigned int line_time_in_us; 740 uint8_t rate_control_caps; 741 uint16_t dsc_slice_height; 742 }; 743 744 struct colorspace_transform { 745 struct fixed31_32 matrix[12]; 746 bool enable_remap; 747 }; 748 749 enum i2c_mot_mode { 750 I2C_MOT_UNDEF, 751 I2C_MOT_TRUE, 752 I2C_MOT_FALSE 753 }; 754 755 struct AsicStateEx { 756 unsigned int memoryClock; 757 unsigned int displayClock; 758 unsigned int engineClock; 759 unsigned int maxSupportedDppClock; 760 unsigned int dppClock; 761 unsigned int socClock; 762 unsigned int dcfClockDeepSleep; 763 unsigned int fClock; 764 unsigned int phyClock; 765 }; 766 767 768 enum dc_clock_type { 769 DC_CLOCK_TYPE_DISPCLK = 0, 770 DC_CLOCK_TYPE_DPPCLK = 1, 771 }; 772 773 struct dc_clock_config { 774 uint32_t max_clock_khz; 775 uint32_t min_clock_khz; 776 uint32_t bw_requirequired_clock_khz; 777 uint32_t current_clock_khz;/*current clock in use*/ 778 }; 779 780 struct hw_asic_id { 781 uint32_t chip_id; 782 uint32_t chip_family; 783 uint32_t pci_revision_id; 784 uint32_t hw_internal_rev; 785 uint32_t vram_type; 786 uint32_t vram_width; 787 uint32_t feature_flags; 788 uint32_t fake_paths_num; 789 void *atombios_base_address; 790 }; 791 792 struct dc_context { 793 struct dc *dc; 794 795 void *driver_context; /* e.g. amdgpu_device */ 796 struct dc_perf_trace *perf_trace; 797 void *cgs_device; 798 799 enum dce_environment dce_environment; 800 struct hw_asic_id asic_id; 801 802 /* todo: below should probably move to dc. to facilitate removal 803 * of AS we will store these here 804 */ 805 enum dce_version dce_version; 806 struct dc_bios *dc_bios; 807 bool created_bios; 808 struct gpio_service *gpio_service; 809 uint32_t dc_sink_id_count; 810 uint32_t dc_stream_id_count; 811 uint32_t dc_edp_id_count; 812 uint64_t fbc_gpu_addr; 813 struct dc_dmub_srv *dmub_srv; 814 struct cp_psp cp_psp; 815 uint32_t *dcn_reg_offsets; 816 uint32_t *nbio_reg_offsets; 817 }; 818 819 /* DSC DPCD capabilities */ 820 union dsc_slice_caps1 { 821 struct { 822 uint8_t NUM_SLICES_1 : 1; 823 uint8_t NUM_SLICES_2 : 1; 824 uint8_t RESERVED : 1; 825 uint8_t NUM_SLICES_4 : 1; 826 uint8_t NUM_SLICES_6 : 1; 827 uint8_t NUM_SLICES_8 : 1; 828 uint8_t NUM_SLICES_10 : 1; 829 uint8_t NUM_SLICES_12 : 1; 830 } bits; 831 uint8_t raw; 832 }; 833 834 union dsc_slice_caps2 { 835 struct { 836 uint8_t NUM_SLICES_16 : 1; 837 uint8_t NUM_SLICES_20 : 1; 838 uint8_t NUM_SLICES_24 : 1; 839 uint8_t RESERVED : 5; 840 } bits; 841 uint8_t raw; 842 }; 843 844 union dsc_color_formats { 845 struct { 846 uint8_t RGB : 1; 847 uint8_t YCBCR_444 : 1; 848 uint8_t YCBCR_SIMPLE_422 : 1; 849 uint8_t YCBCR_NATIVE_422 : 1; 850 uint8_t YCBCR_NATIVE_420 : 1; 851 uint8_t RESERVED : 3; 852 } bits; 853 uint8_t raw; 854 }; 855 856 union dsc_color_depth { 857 struct { 858 uint8_t RESERVED1 : 1; 859 uint8_t COLOR_DEPTH_8_BPC : 1; 860 uint8_t COLOR_DEPTH_10_BPC : 1; 861 uint8_t COLOR_DEPTH_12_BPC : 1; 862 uint8_t RESERVED2 : 3; 863 } bits; 864 uint8_t raw; 865 }; 866 867 struct dsc_dec_dpcd_caps { 868 bool is_dsc_supported; 869 uint8_t dsc_version; 870 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 871 union dsc_slice_caps1 slice_caps1; 872 union dsc_slice_caps2 slice_caps2; 873 int32_t lb_bit_depth; 874 bool is_block_pred_supported; 875 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 876 union dsc_color_formats color_formats; 877 union dsc_color_depth color_depth; 878 int32_t throughput_mode_0_mps; /* In MPs */ 879 int32_t throughput_mode_1_mps; /* In MPs */ 880 int32_t max_slice_width; 881 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 882 883 /* Extended DSC caps */ 884 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 885 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 886 uint32_t branch_max_line_width; 887 bool is_dp; 888 }; 889 890 struct dc_golden_table { 891 uint16_t dc_golden_table_ver; 892 uint32_t aux_dphy_rx_control0_val; 893 uint32_t aux_dphy_tx_control_val; 894 uint32_t aux_dphy_rx_control1_val; 895 uint32_t dc_gpio_aux_ctrl_0_val; 896 uint32_t dc_gpio_aux_ctrl_1_val; 897 uint32_t dc_gpio_aux_ctrl_2_val; 898 uint32_t dc_gpio_aux_ctrl_3_val; 899 uint32_t dc_gpio_aux_ctrl_4_val; 900 uint32_t dc_gpio_aux_ctrl_5_val; 901 }; 902 903 enum dc_gpu_mem_alloc_type { 904 DC_MEM_ALLOC_TYPE_GART, 905 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 906 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 907 DC_MEM_ALLOC_TYPE_AGP 908 }; 909 910 enum dc_psr_version { 911 DC_PSR_VERSION_1 = 0, 912 DC_PSR_VERSION_SU_1 = 1, 913 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 914 }; 915 916 /* Possible values of display_endpoint_id.endpoint */ 917 enum display_endpoint_type { 918 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 919 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 920 DISPLAY_ENDPOINT_UNKNOWN = -1 921 }; 922 923 /* Extends graphics_object_id with an additional member 'ep_type' for 924 * distinguishing between physical endpoints (with entries in BIOS connector table) and 925 * logical endpoints. 926 */ 927 struct display_endpoint_id { 928 struct graphics_object_id link_id; 929 enum display_endpoint_type ep_type; 930 }; 931 932 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 933 struct otg_phy_mux { 934 uint8_t phy_output_num; 935 uint8_t otg_output_num; 936 }; 937 #endif 938 939 enum dc_detect_reason { 940 DETECT_REASON_BOOT, 941 DETECT_REASON_RESUMEFROMS3S4, 942 DETECT_REASON_HPD, 943 DETECT_REASON_HPDRX, 944 DETECT_REASON_FALLBACK, 945 DETECT_REASON_RETRAIN, 946 DETECT_REASON_TDR, 947 }; 948 949 struct dc_link_status { 950 bool link_active; 951 struct dpcd_caps *dpcd_caps; 952 }; 953 954 union hdcp_rx_caps { 955 struct { 956 uint8_t version; 957 uint8_t reserved; 958 struct { 959 uint8_t repeater : 1; 960 uint8_t hdcp_capable : 1; 961 uint8_t reserved : 6; 962 } byte0; 963 } fields; 964 uint8_t raw[3]; 965 }; 966 967 union hdcp_bcaps { 968 struct { 969 uint8_t HDCP_CAPABLE:1; 970 uint8_t REPEATER:1; 971 uint8_t RESERVED:6; 972 } bits; 973 uint8_t raw; 974 }; 975 976 struct hdcp_caps { 977 union hdcp_rx_caps rx_caps; 978 union hdcp_bcaps bcaps; 979 }; 980 981 /* DP MST stream allocation (payload bandwidth number) */ 982 struct link_mst_stream_allocation { 983 /* DIG front */ 984 const struct stream_encoder *stream_enc; 985 /* HPO DP Stream Encoder */ 986 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 987 /* associate DRM payload table with DC stream encoder */ 988 uint8_t vcp_id; 989 /* number of slots required for the DP stream in transport packet */ 990 uint8_t slot_count; 991 }; 992 993 #define MAX_CONTROLLER_NUM 6 994 995 /* DP MST stream allocation table */ 996 struct link_mst_stream_allocation_table { 997 /* number of DP video streams */ 998 int stream_count; 999 /* array of stream allocations */ 1000 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 1001 }; 1002 1003 /* PSR feature flags */ 1004 struct psr_settings { 1005 bool psr_feature_enabled; // PSR is supported by sink 1006 bool psr_allow_active; // PSR is currently active 1007 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1008 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1009 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1010 1011 /* These parameters are calculated in Driver, 1012 * based on display timing and Sink capabilities. 1013 * If VBLANK region is too small and Sink takes a long time 1014 * to set up RFB, it may take an extra frame to enter PSR state. 1015 */ 1016 bool psr_frame_capture_indication_req; 1017 unsigned int psr_sdp_transmit_line_num_deadline; 1018 uint8_t force_ffu_mode; 1019 unsigned int psr_power_opt; 1020 }; 1021 1022 /* To split out "global" and "per-panel" config settings. 1023 * Add a struct dc_panel_config under dc_link 1024 */ 1025 struct dc_panel_config { 1026 /* extra panel power sequence parameters */ 1027 struct pps { 1028 unsigned int extra_t3_ms; 1029 unsigned int extra_t7_ms; 1030 unsigned int extra_delay_backlight_off; 1031 unsigned int extra_post_t7_ms; 1032 unsigned int extra_pre_t11_ms; 1033 unsigned int extra_t12_ms; 1034 unsigned int extra_post_OUI_ms; 1035 } pps; 1036 /* nit brightness */ 1037 struct nits_brightness { 1038 unsigned int peak; /* nits */ 1039 unsigned int max_avg; /* nits */ 1040 unsigned int min; /* 1/10000 nits */ 1041 unsigned int max_nonboost_brightness_millinits; 1042 unsigned int min_brightness_millinits; 1043 } nits_brightness; 1044 /* PSR */ 1045 struct psr { 1046 bool disable_psr; 1047 bool disallow_psrsu; 1048 bool rc_disable; 1049 bool rc_allow_static_screen; 1050 bool rc_allow_fullscreen_VPB; 1051 } psr; 1052 /* ABM */ 1053 struct varib { 1054 unsigned int varibright_feature_enable; 1055 unsigned int def_varibright_level; 1056 unsigned int abm_config_setting; 1057 } varib; 1058 /* edp DSC */ 1059 struct dsc { 1060 bool disable_dsc_edp; 1061 unsigned int force_dsc_edp_policy; 1062 } dsc; 1063 /* eDP ILR */ 1064 struct ilr { 1065 bool optimize_edp_link_rate; /* eDP ILR */ 1066 } ilr; 1067 }; 1068 1069 /* 1070 * USB4 DPIA BW ALLOCATION STRUCTS 1071 */ 1072 struct dc_dpia_bw_alloc { 1073 int sink_verified_bw; // The Verified BW that sink can allocated and use that has been verified already 1074 int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated 1075 int sink_max_bw; // The Max BW that sink can require/support 1076 int estimated_bw; // The estimated available BW for this DPIA 1077 int bw_granularity; // BW Granularity 1078 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1079 bool response_ready; // Response ready from the CM side 1080 }; 1081 1082 #define MAX_SINKS_PER_LINK 4 1083 1084 enum dc_hpd_enable_select { 1085 HPD_EN_FOR_ALL_EDP = 0, 1086 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1087 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1088 }; 1089 1090 #endif /* DC_TYPES_H_ */ 1091