1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef DC_TYPES_H_
26 #define DC_TYPES_H_
27 
28 /* AND EdidUtility only needs a portion
29  * of this file, including the rest only
30  * causes additional issues.
31  */
32 #include "os_types.h"
33 #include "fixed31_32.h"
34 #include "irq_types.h"
35 #include "dc_dp_types.h"
36 #include "dc_hw_types.h"
37 #include "dal_types.h"
38 #include "grph_object_defs.h"
39 
40 #ifdef CONFIG_DRM_AMD_DC_HDCP
41 #include "dm_cp_psp.h"
42 #endif
43 
44 /* forward declarations */
45 struct dc_plane_state;
46 struct dc_stream_state;
47 struct dc_link;
48 struct dc_sink;
49 struct dal;
50 struct dc_dmub_srv;
51 
52 /********************************
53  * Environment definitions
54  ********************************/
55 enum dce_environment {
56 	DCE_ENV_PRODUCTION_DRV = 0,
57 	/* Emulation on FPGA, in "Maximus" System.
58 	 * This environment enforces that *only* DC registers accessed.
59 	 * (access to non-DC registers will hang FPGA) */
60 	DCE_ENV_FPGA_MAXIMUS,
61 	/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
62 	 * requirements of Diagnostics team. */
63 	DCE_ENV_DIAG,
64 	/*
65 	 * Guest VM system, DC HW may exist but is not virtualized and
66 	 * should not be used.  SW support for VDI only.
67 	 */
68 	DCE_ENV_VIRTUAL_HW
69 };
70 
71 /* Note: use these macro definitions instead of direct comparison! */
72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \
73 	(dce_environment == DCE_ENV_FPGA_MAXIMUS)
74 
75 #define IS_DIAG_DC(dce_environment) \
76 	(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
77 
78 struct dc_perf_trace {
79 	unsigned long read_count;
80 	unsigned long write_count;
81 	unsigned long last_entry_read;
82 	unsigned long last_entry_write;
83 };
84 
85 #define DC_MAX_EDID_BUFFER_SIZE 2048
86 #define DC_EDID_BLOCK_SIZE 128
87 #define MAX_SURFACE_NUM 4
88 #define NUM_PIXEL_FORMATS 10
89 #define MAX_REPEATER_CNT 8
90 
91 #include "dc_ddc_types.h"
92 
93 enum tiling_mode {
94 	TILING_MODE_INVALID,
95 	TILING_MODE_LINEAR,
96 	TILING_MODE_TILED,
97 	TILING_MODE_COUNT
98 };
99 
100 enum view_3d_format {
101 	VIEW_3D_FORMAT_NONE = 0,
102 	VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
103 	VIEW_3D_FORMAT_SIDE_BY_SIDE,
104 	VIEW_3D_FORMAT_TOP_AND_BOTTOM,
105 	VIEW_3D_FORMAT_COUNT,
106 	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
107 };
108 
109 enum plane_stereo_format {
110 	PLANE_STEREO_FORMAT_NONE = 0,
111 	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
112 	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
113 	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
114 	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
115 	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
116 	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
117 };
118 
119 /* TODO: Find way to calculate number of bits
120  *  Please increase if pixel_format enum increases
121  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
122  */
123 
124 enum dc_edid_connector_type {
125 	DC_EDID_CONNECTOR_UNKNOWN = 0,
126 	DC_EDID_CONNECTOR_ANALOG = 1,
127 	DC_EDID_CONNECTOR_DIGITAL = 10,
128 	DC_EDID_CONNECTOR_DVI = 11,
129 	DC_EDID_CONNECTOR_HDMIA = 12,
130 	DC_EDID_CONNECTOR_MDDI = 14,
131 	DC_EDID_CONNECTOR_DISPLAYPORT = 15
132 };
133 
134 enum dc_edid_status {
135 	EDID_OK,
136 	EDID_BAD_INPUT,
137 	EDID_NO_RESPONSE,
138 	EDID_BAD_CHECKSUM,
139 	EDID_THE_SAME,
140 	EDID_FALL_BACK,
141 	EDID_PARTIAL_VALID,
142 };
143 
144 enum act_return_status {
145 	ACT_SUCCESS,
146 	ACT_LINK_LOST,
147 	ACT_FAILED
148 };
149 
150 /* audio capability from EDID*/
151 struct dc_cea_audio_mode {
152 	uint8_t format_code; /* ucData[0] [6:3]*/
153 	uint8_t channel_count; /* ucData[0] [2:0]*/
154 	uint8_t sample_rate; /* ucData[1]*/
155 	union {
156 		uint8_t sample_size; /* for LPCM*/
157 		/*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
158 		uint8_t max_bit_rate;
159 		uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
160 	};
161 };
162 
163 struct dc_edid {
164 	uint32_t length;
165 	uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
166 };
167 
168 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
169  * is used. In this case we assume speaker location are: front left, front
170  * right and front center. */
171 #define DEFAULT_SPEAKER_LOCATION 5
172 
173 #define DC_MAX_AUDIO_DESC_COUNT 16
174 
175 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
176 
177 union display_content_support {
178 	unsigned int raw;
179 	struct {
180 		unsigned int valid_content_type :1;
181 		unsigned int game_content :1;
182 		unsigned int cinema_content :1;
183 		unsigned int photo_content :1;
184 		unsigned int graphics_content :1;
185 		unsigned int reserved :27;
186 	} bits;
187 };
188 
189 struct dc_panel_patch {
190 	unsigned int dppowerup_delay;
191 	unsigned int extra_t12_ms;
192 	unsigned int extra_delay_backlight_off;
193 	unsigned int extra_t7_ms;
194 	unsigned int skip_scdc_overwrite;
195 	unsigned int delay_ignore_msa;
196 	unsigned int disable_fec;
197 	unsigned int extra_t3_ms;
198 	unsigned int max_dsc_target_bpp_limit;
199 	unsigned int embedded_tiled_slave;
200 	unsigned int disable_fams;
201 	unsigned int skip_avmute;
202 	unsigned int mst_start_top_delay;
203 };
204 
205 struct dc_edid_caps {
206 	/* sink identification */
207 	uint16_t manufacturer_id;
208 	uint16_t product_id;
209 	uint32_t serial_number;
210 	uint8_t manufacture_week;
211 	uint8_t manufacture_year;
212 	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
213 
214 	/* audio caps */
215 	uint8_t speaker_flags;
216 	uint32_t audio_mode_count;
217 	struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
218 	uint32_t audio_latency;
219 	uint32_t video_latency;
220 
221 	union display_content_support content_support;
222 
223 	uint8_t qs_bit;
224 	uint8_t qy_bit;
225 
226 	uint32_t max_tmds_clk_mhz;
227 
228 	/*HDMI 2.0 caps*/
229 	bool lte_340mcsc_scramble;
230 
231 	bool edid_hdmi;
232 	bool hdr_supported;
233 
234 	struct dc_panel_patch panel_patch;
235 };
236 
237 struct dc_mode_flags {
238 	/* note: part of refresh rate flag*/
239 	uint32_t INTERLACE :1;
240 	/* native display timing*/
241 	uint32_t NATIVE :1;
242 	/* preferred is the recommended mode, one per display */
243 	uint32_t PREFERRED :1;
244 	/* true if this mode should use reduced blanking timings
245 	 *_not_ related to the Reduced Blanking adjustment*/
246 	uint32_t REDUCED_BLANKING :1;
247 	/* note: part of refreshrate flag*/
248 	uint32_t VIDEO_OPTIMIZED_RATE :1;
249 	/* should be reported to upper layers as mode_flags*/
250 	uint32_t PACKED_PIXEL_FORMAT :1;
251 	/*< preferred view*/
252 	uint32_t PREFERRED_VIEW :1;
253 	/* this timing should be used only in tiled mode*/
254 	uint32_t TILED_MODE :1;
255 	uint32_t DSE_MODE :1;
256 	/* Refresh rate divider when Miracast sink is using a
257 	 different rate than the output display device
258 	 Must be zero for wired displays and non-zero for
259 	 Miracast displays*/
260 	uint32_t MIRACAST_REFRESH_DIVIDER;
261 };
262 
263 
264 enum dc_timing_source {
265 	TIMING_SOURCE_UNDEFINED,
266 
267 	/* explicitly specifed by user, most important*/
268 	TIMING_SOURCE_USER_FORCED,
269 	TIMING_SOURCE_USER_OVERRIDE,
270 	TIMING_SOURCE_CUSTOM,
271 	TIMING_SOURCE_EXPLICIT,
272 
273 	/* explicitly specified by the display device, more important*/
274 	TIMING_SOURCE_EDID_CEA_SVD_3D,
275 	TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
276 	TIMING_SOURCE_EDID_CEA_SVD_420,
277 	TIMING_SOURCE_EDID_DETAILED,
278 	TIMING_SOURCE_EDID_ESTABLISHED,
279 	TIMING_SOURCE_EDID_STANDARD,
280 	TIMING_SOURCE_EDID_CEA_SVD,
281 	TIMING_SOURCE_EDID_CVT_3BYTE,
282 	TIMING_SOURCE_EDID_4BYTE,
283 	TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,
284 	TIMING_SOURCE_EDID_CEA_RID,
285 	TIMING_SOURCE_VBIOS,
286 	TIMING_SOURCE_CV,
287 	TIMING_SOURCE_TV,
288 	TIMING_SOURCE_HDMI_VIC,
289 
290 	/* implicitly specified by display device, still safe but less important*/
291 	TIMING_SOURCE_DEFAULT,
292 
293 	/* only used for custom base modes */
294 	TIMING_SOURCE_CUSTOM_BASE,
295 
296 	/* these timing might not work, least important*/
297 	TIMING_SOURCE_RANGELIMIT,
298 	TIMING_SOURCE_OS_FORCED,
299 	TIMING_SOURCE_IMPLICIT,
300 
301 	/* only used by default mode list*/
302 	TIMING_SOURCE_BASICMODE,
303 
304 	TIMING_SOURCE_COUNT
305 };
306 
307 
308 struct stereo_3d_features {
309 	bool supported			;
310 	bool allTimings			;
311 	bool cloneMode			;
312 	bool scaling			;
313 	bool singleFrameSWPacked;
314 };
315 
316 enum dc_timing_support_method {
317 	TIMING_SUPPORT_METHOD_UNDEFINED,
318 	TIMING_SUPPORT_METHOD_EXPLICIT,
319 	TIMING_SUPPORT_METHOD_IMPLICIT,
320 	TIMING_SUPPORT_METHOD_NATIVE
321 };
322 
323 struct dc_mode_info {
324 	uint32_t pixel_width;
325 	uint32_t pixel_height;
326 	uint32_t field_rate;
327 	/* Vertical refresh rate for progressive modes.
328 	* Field rate for interlaced modes.*/
329 
330 	enum dc_timing_standard timing_standard;
331 	enum dc_timing_source timing_source;
332 	struct dc_mode_flags flags;
333 };
334 
335 enum dc_power_state {
336 	DC_POWER_STATE_ON = 1,
337 	DC_POWER_STATE_STANDBY,
338 	DC_POWER_STATE_SUSPEND,
339 	DC_POWER_STATE_OFF
340 };
341 
342 /* DC PowerStates */
343 enum dc_video_power_state {
344 	DC_VIDEO_POWER_UNSPECIFIED = 0,
345 	DC_VIDEO_POWER_ON = 1,
346 	DC_VIDEO_POWER_STANDBY,
347 	DC_VIDEO_POWER_SUSPEND,
348 	DC_VIDEO_POWER_OFF,
349 	DC_VIDEO_POWER_HIBERNATE,
350 	DC_VIDEO_POWER_SHUTDOWN,
351 	DC_VIDEO_POWER_ULPS,	/* BACO or Ultra-Light-Power-State */
352 	DC_VIDEO_POWER_AFTER_RESET,
353 	DC_VIDEO_POWER_MAXIMUM
354 };
355 
356 enum dc_acpi_cm_power_state {
357 	DC_ACPI_CM_POWER_STATE_D0 = 1,
358 	DC_ACPI_CM_POWER_STATE_D1 = 2,
359 	DC_ACPI_CM_POWER_STATE_D2 = 4,
360 	DC_ACPI_CM_POWER_STATE_D3 = 8
361 };
362 
363 enum dc_connection_type {
364 	dc_connection_none,
365 	dc_connection_single,
366 	dc_connection_mst_branch,
367 	dc_connection_sst_branch
368 };
369 
370 struct dc_csc_adjustments {
371 	struct fixed31_32 contrast;
372 	struct fixed31_32 saturation;
373 	struct fixed31_32 brightness;
374 	struct fixed31_32 hue;
375 };
376 
377 enum dpcd_downstream_port_max_bpc {
378 	DOWN_STREAM_MAX_8BPC = 0,
379 	DOWN_STREAM_MAX_10BPC,
380 	DOWN_STREAM_MAX_12BPC,
381 	DOWN_STREAM_MAX_16BPC
382 };
383 
384 
385 enum link_training_offset {
386 	DPRX                = 0,
387 	LTTPR_PHY_REPEATER1 = 1,
388 	LTTPR_PHY_REPEATER2 = 2,
389 	LTTPR_PHY_REPEATER3 = 3,
390 	LTTPR_PHY_REPEATER4 = 4,
391 	LTTPR_PHY_REPEATER5 = 5,
392 	LTTPR_PHY_REPEATER6 = 6,
393 	LTTPR_PHY_REPEATER7 = 7,
394 	LTTPR_PHY_REPEATER8 = 8
395 };
396 
397 struct dc_lttpr_caps {
398 	union dpcd_rev revision;
399 	uint8_t mode;
400 	uint8_t max_lane_count;
401 	uint8_t max_link_rate;
402 	uint8_t phy_repeater_cnt;
403 	uint8_t max_ext_timeout;
404 	union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding;
405 	union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates;
406 	uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
407 };
408 
409 struct dc_dongle_dfp_cap_ext {
410 	bool supported;
411 	uint16_t max_pixel_rate_in_mps;
412 	uint16_t max_video_h_active_width;
413 	uint16_t max_video_v_active_height;
414 	struct dp_encoding_format_caps encoding_format_caps;
415 	struct dp_color_depth_caps rgb_color_depth_caps;
416 	struct dp_color_depth_caps ycbcr444_color_depth_caps;
417 	struct dp_color_depth_caps ycbcr422_color_depth_caps;
418 	struct dp_color_depth_caps ycbcr420_color_depth_caps;
419 };
420 
421 struct dc_dongle_caps {
422 	/* dongle type (DP converter, CV smart dongle) */
423 	enum display_dongle_type dongle_type;
424 	bool extendedCapValid;
425 	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
426 	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
427 	bool is_dp_hdmi_s3d_converter;
428 	bool is_dp_hdmi_ycbcr422_pass_through;
429 	bool is_dp_hdmi_ycbcr420_pass_through;
430 	bool is_dp_hdmi_ycbcr422_converter;
431 	bool is_dp_hdmi_ycbcr420_converter;
432 	uint32_t dp_hdmi_max_bpc;
433 	uint32_t dp_hdmi_max_pixel_clk_in_khz;
434 	uint32_t dp_hdmi_frl_max_link_bw_in_kbps;
435 	struct dc_dongle_dfp_cap_ext dfp_cap_ext;
436 };
437 /* Scaling format */
438 enum scaling_transformation {
439 	SCALING_TRANSFORMATION_UNINITIALIZED,
440 	SCALING_TRANSFORMATION_IDENTITY = 0x0001,
441 	SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
442 	SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
443 	SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
444 	SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
445 	SCALING_TRANSFORMATION_INVALID = 0x80000000,
446 
447 	/* Flag the first and last */
448 	SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
449 	SCALING_TRANSFORMATION_END =
450 		SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
451 };
452 
453 enum display_content_type {
454 	DISPLAY_CONTENT_TYPE_NO_DATA = 0,
455 	DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
456 	DISPLAY_CONTENT_TYPE_PHOTO = 2,
457 	DISPLAY_CONTENT_TYPE_CINEMA = 4,
458 	DISPLAY_CONTENT_TYPE_GAME = 8
459 };
460 
461 enum cm_gamut_adjust_type {
462 	CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
463 	CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
464 	CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
465 };
466 
467 struct cm_grph_csc_adjustment {
468 	struct fixed31_32 temperature_matrix[12];
469 	enum cm_gamut_adjust_type gamut_adjust_type;
470 	enum cm_gamut_coef_format gamut_coef_format;
471 };
472 
473 /* writeback */
474 struct dwb_stereo_params {
475 	bool				stereo_enabled;		/* false: normal mode, true: 3D stereo */
476 	enum dwb_stereo_type		stereo_type;		/* indicates stereo format */
477 	bool				stereo_polarity;	/* indicates left eye or right eye comes first in stereo mode */
478 	enum dwb_stereo_eye_select	stereo_eye_select;	/* indicate which eye should be captured */
479 };
480 
481 struct dc_dwb_cnv_params {
482 	unsigned int		src_width;	/* input active width */
483 	unsigned int		src_height;	/* input active height (half-active height in interlaced mode) */
484 	unsigned int		crop_width;	/* cropped window width at cnv output */
485 	bool			crop_en;	/* window cropping enable in cnv */
486 	unsigned int		crop_height;	/* cropped window height at cnv output */
487 	unsigned int		crop_x;		/* cropped window start x value at cnv output */
488 	unsigned int		crop_y;		/* cropped window start y value at cnv output */
489 	enum dwb_cnv_out_bpc cnv_out_bpc;	/* cnv output pixel depth - 8bpc or 10bpc */
490 	enum dwb_out_format	fc_out_format;	/* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
491 	enum dwb_out_denorm	out_denorm_mode;/* dwb output denormalization mode */
492 	unsigned int		out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
493 	unsigned int		out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
494 };
495 
496 struct dc_dwb_params {
497 	unsigned int			dwbscl_black_color; /* must be in FP1.5.10 */
498 	unsigned int			hdr_mult;	/* must be in FP1.6.12 */
499 	struct cm_grph_csc_adjustment	csc_params;
500 	struct dwb_stereo_params	stereo_params;
501 	struct dc_dwb_cnv_params	cnv_params;	/* CNV source size and cropping window parameters */
502 	unsigned int			dest_width;	/* Destination width */
503 	unsigned int			dest_height;	/* Destination height */
504 	enum dwb_scaler_mode		out_format;	/* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
505 	enum dwb_output_depth		output_depth;	/* output pixel depth - 8bpc or 10bpc */
506 	enum dwb_capture_rate		capture_rate;	/* controls the frame capture rate */
507 	struct scaling_taps 		scaler_taps;	/* Scaling taps */
508 	enum dwb_subsample_position	subsample_position;
509 	struct dc_transfer_func *out_transfer_func;
510 };
511 
512 /* audio*/
513 
514 union audio_sample_rates {
515 	struct sample_rates {
516 		uint8_t RATE_32:1;
517 		uint8_t RATE_44_1:1;
518 		uint8_t RATE_48:1;
519 		uint8_t RATE_88_2:1;
520 		uint8_t RATE_96:1;
521 		uint8_t RATE_176_4:1;
522 		uint8_t RATE_192:1;
523 	} rate;
524 
525 	uint8_t all;
526 };
527 
528 struct audio_speaker_flags {
529 	uint32_t FL_FR:1;
530 	uint32_t LFE:1;
531 	uint32_t FC:1;
532 	uint32_t RL_RR:1;
533 	uint32_t RC:1;
534 	uint32_t FLC_FRC:1;
535 	uint32_t RLC_RRC:1;
536 	uint32_t SUPPORT_AI:1;
537 };
538 
539 struct audio_speaker_info {
540 	uint32_t ALLSPEAKERS:7;
541 	uint32_t SUPPORT_AI:1;
542 };
543 
544 
545 struct audio_info_flags {
546 
547 	union {
548 
549 		struct audio_speaker_flags speaker_flags;
550 		struct audio_speaker_info   info;
551 
552 		uint8_t all;
553 	};
554 };
555 
556 enum audio_format_code {
557 	AUDIO_FORMAT_CODE_FIRST = 1,
558 	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
559 
560 	AUDIO_FORMAT_CODE_AC3,
561 	/*Layers 1 & 2 */
562 	AUDIO_FORMAT_CODE_MPEG1,
563 	/*MPEG1 Layer 3 */
564 	AUDIO_FORMAT_CODE_MP3,
565 	/*multichannel */
566 	AUDIO_FORMAT_CODE_MPEG2,
567 	AUDIO_FORMAT_CODE_AAC,
568 	AUDIO_FORMAT_CODE_DTS,
569 	AUDIO_FORMAT_CODE_ATRAC,
570 	AUDIO_FORMAT_CODE_1BITAUDIO,
571 	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
572 	AUDIO_FORMAT_CODE_DTS_HD,
573 	AUDIO_FORMAT_CODE_MAT_MLP,
574 	AUDIO_FORMAT_CODE_DST,
575 	AUDIO_FORMAT_CODE_WMAPRO,
576 	AUDIO_FORMAT_CODE_LAST,
577 	AUDIO_FORMAT_CODE_COUNT =
578 		AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
579 };
580 
581 struct audio_mode {
582 	 /* ucData[0] [6:3] */
583 	enum audio_format_code format_code;
584 	/* ucData[0] [2:0] */
585 	uint8_t channel_count;
586 	/* ucData[1] */
587 	union audio_sample_rates sample_rates;
588 	union {
589 		/* for LPCM */
590 		uint8_t sample_size;
591 		/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
592 		uint8_t max_bit_rate;
593 		/* for Audio Formats 9-15 */
594 		uint8_t vendor_specific;
595 	};
596 };
597 
598 struct audio_info {
599 	struct audio_info_flags flags;
600 	uint32_t video_latency;
601 	uint32_t audio_latency;
602 	uint32_t display_index;
603 	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
604 	uint32_t manufacture_id;
605 	uint32_t product_id;
606 	/* PortID used for ContainerID when defined */
607 	uint32_t port_id[2];
608 	uint32_t mode_count;
609 	/* this field must be last in this struct */
610 	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
611 };
612 struct audio_check {
613 	unsigned int audio_packet_type;
614 	unsigned int max_audiosample_rate;
615 	unsigned int acat;
616 };
617 enum dc_infoframe_type {
618 	DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
619 	DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
620 	DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
621 	DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
622 	DC_DP_INFOFRAME_TYPE_PPS = 0x10,
623 };
624 
625 struct dc_info_packet {
626 	bool valid;
627 	uint8_t hb0;
628 	uint8_t hb1;
629 	uint8_t hb2;
630 	uint8_t hb3;
631 	uint8_t sb[32];
632 };
633 
634 struct dc_info_packet_128 {
635 	bool valid;
636 	uint8_t hb0;
637 	uint8_t hb1;
638 	uint8_t hb2;
639 	uint8_t hb3;
640 	uint8_t sb[128];
641 };
642 
643 #define DC_PLANE_UPDATE_TIMES_MAX 10
644 
645 struct dc_plane_flip_time {
646 	unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
647 	unsigned int index;
648 	unsigned int prev_update_time_in_us;
649 };
650 
651 enum dc_psr_state {
652 	PSR_STATE0 = 0x0,
653 	PSR_STATE1,
654 	PSR_STATE1a,
655 	PSR_STATE2,
656 	PSR_STATE2a,
657 	PSR_STATE2b,
658 	PSR_STATE3,
659 	PSR_STATE3Init,
660 	PSR_STATE4,
661 	PSR_STATE4a,
662 	PSR_STATE4b,
663 	PSR_STATE4c,
664 	PSR_STATE4d,
665 	PSR_STATE4_FULL_FRAME,
666 	PSR_STATE4a_FULL_FRAME,
667 	PSR_STATE4b_FULL_FRAME,
668 	PSR_STATE4c_FULL_FRAME,
669 	PSR_STATE4_FULL_FRAME_POWERUP,
670 	PSR_STATE5,
671 	PSR_STATE5a,
672 	PSR_STATE5b,
673 	PSR_STATE5c,
674 	PSR_STATE_HWLOCK_MGR,
675 	PSR_STATE_POLLVUPDATE,
676 	PSR_STATE_INVALID = 0xFF
677 };
678 
679 struct psr_config {
680 	unsigned char psr_version;
681 	unsigned int psr_rfb_setup_time;
682 	bool psr_exit_link_training_required;
683 	bool psr_frame_capture_indication_req;
684 	unsigned int psr_sdp_transmit_line_num_deadline;
685 	bool allow_smu_optimizations;
686 	bool allow_multi_disp_optimizations;
687 	/* Panel self refresh 2 selective update granularity required */
688 	bool su_granularity_required;
689 	/* psr2 selective update y granularity capability */
690 	uint8_t su_y_granularity;
691 	unsigned int line_time_in_us;
692 	uint8_t rate_control_caps;
693 };
694 
695 union dmcu_psr_level {
696 	struct {
697 		unsigned int SKIP_CRC:1;
698 		unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
699 		unsigned int SKIP_PHY_POWER_DOWN:1;
700 		unsigned int SKIP_AUX_ACK_CHECK:1;
701 		unsigned int SKIP_CRTC_DISABLE:1;
702 		unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
703 		unsigned int SKIP_SMU_NOTIFICATION:1;
704 		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
705 		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
706 		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
707 		unsigned int DISABLE_ALPM:1;
708 		unsigned int ALPM_DEFAULT_PD_MODE:1;
709 		unsigned int RESERVED:20;
710 	} bits;
711 	unsigned int u32all;
712 };
713 
714 enum physical_phy_id {
715 	PHYLD_0,
716 	PHYLD_1,
717 	PHYLD_2,
718 	PHYLD_3,
719 	PHYLD_4,
720 	PHYLD_5,
721 	PHYLD_6,
722 	PHYLD_7,
723 	PHYLD_8,
724 	PHYLD_9,
725 	PHYLD_COUNT,
726 	PHYLD_UNKNOWN = (-1L)
727 };
728 
729 enum phy_type {
730 	PHY_TYPE_UNKNOWN  = 1,
731 	PHY_TYPE_PCIE_PHY = 2,
732 	PHY_TYPE_UNIPHY = 3,
733 };
734 
735 struct psr_context {
736 	/* ddc line */
737 	enum channel_id channel;
738 	/* Transmitter id */
739 	enum transmitter transmitterId;
740 	/* Engine Id is used for Dig Be source select */
741 	enum engine_id engineId;
742 	/* Controller Id used for Dig Fe source select */
743 	enum controller_id controllerId;
744 	/* Pcie or Uniphy */
745 	enum phy_type phyType;
746 	/* Physical PHY Id used by SMU interpretation */
747 	enum physical_phy_id smuPhyId;
748 	/* Vertical total pixels from crtc timing.
749 	 * This is used for static screen detection.
750 	 * ie. If we want to detect half a frame,
751 	 * we use this to determine the hyst lines.
752 	 */
753 	unsigned int crtcTimingVerticalTotal;
754 	/* PSR supported from panel capabilities and
755 	 * current display configuration
756 	 */
757 	bool psrSupportedDisplayConfig;
758 	/* Whether fast link training is supported by the panel */
759 	bool psrExitLinkTrainingRequired;
760 	/* If RFB setup time is greater than the total VBLANK time,
761 	 * it is not possible for the sink to capture the video frame
762 	 * in the same frame the SDP is sent. In this case,
763 	 * the frame capture indication bit should be set and an extra
764 	 * static frame should be transmitted to the sink.
765 	 */
766 	bool psrFrameCaptureIndicationReq;
767 	/* Set the last possible line SDP may be transmitted without violating
768 	 * the RFB setup time or entering the active video frame.
769 	 */
770 	unsigned int sdpTransmitLineNumDeadline;
771 	/* The VSync rate in Hz used to calculate the
772 	 * step size for smooth brightness feature
773 	 */
774 	unsigned int vsync_rate_hz;
775 	unsigned int skipPsrWaitForPllLock;
776 	unsigned int numberOfControllers;
777 	/* Unused, for future use. To indicate that first changed frame from
778 	 * state3 shouldn't result in psr_inactive, but rather to perform
779 	 * an automatic single frame rfb_update.
780 	 */
781 	bool rfb_update_auto_en;
782 	/* Number of frame before entering static screen */
783 	unsigned int timehyst_frames;
784 	/* Partial frames before entering static screen */
785 	unsigned int hyst_lines;
786 	/* # of repeated AUX transaction attempts to make before
787 	 * indicating failure to the driver
788 	 */
789 	unsigned int aux_repeats;
790 	/* Controls hw blocks to power down during PSR active state */
791 	union dmcu_psr_level psr_level;
792 	/* Controls additional delay after remote frame capture before
793 	 * continuing powerd own
794 	 */
795 	unsigned int frame_delay;
796 	bool allow_smu_optimizations;
797 	bool allow_multi_disp_optimizations;
798 	/* Panel self refresh 2 selective update granularity required */
799 	bool su_granularity_required;
800 	/* psr2 selective update y granularity capability */
801 	uint8_t su_y_granularity;
802 	unsigned int line_time_in_us;
803 	uint8_t rate_control_caps;
804 };
805 
806 struct colorspace_transform {
807 	struct fixed31_32 matrix[12];
808 	bool enable_remap;
809 };
810 
811 enum i2c_mot_mode {
812 	I2C_MOT_UNDEF,
813 	I2C_MOT_TRUE,
814 	I2C_MOT_FALSE
815 };
816 
817 struct AsicStateEx {
818 	unsigned int memoryClock;
819 	unsigned int displayClock;
820 	unsigned int engineClock;
821 	unsigned int maxSupportedDppClock;
822 	unsigned int dppClock;
823 	unsigned int socClock;
824 	unsigned int dcfClockDeepSleep;
825 	unsigned int fClock;
826 	unsigned int phyClock;
827 };
828 
829 
830 enum dc_clock_type {
831 	DC_CLOCK_TYPE_DISPCLK = 0,
832 	DC_CLOCK_TYPE_DPPCLK        = 1,
833 };
834 
835 struct dc_clock_config {
836 	uint32_t max_clock_khz;
837 	uint32_t min_clock_khz;
838 	uint32_t bw_requirequired_clock_khz;
839 	uint32_t current_clock_khz;/*current clock in use*/
840 };
841 
842 struct hw_asic_id {
843 	uint32_t chip_id;
844 	uint32_t chip_family;
845 	uint32_t pci_revision_id;
846 	uint32_t hw_internal_rev;
847 	uint32_t vram_type;
848 	uint32_t vram_width;
849 	uint32_t feature_flags;
850 	uint32_t fake_paths_num;
851 	void *atombios_base_address;
852 };
853 
854 struct dc_context {
855 	struct dc *dc;
856 
857 	void *driver_context; /* e.g. amdgpu_device */
858 	struct dc_perf_trace *perf_trace;
859 	void *cgs_device;
860 
861 	enum dce_environment dce_environment;
862 	struct hw_asic_id asic_id;
863 
864 	/* todo: below should probably move to dc.  to facilitate removal
865 	 * of AS we will store these here
866 	 */
867 	enum dce_version dce_version;
868 	struct dc_bios *dc_bios;
869 	bool created_bios;
870 	struct gpio_service *gpio_service;
871 	uint32_t dc_sink_id_count;
872 	uint32_t dc_stream_id_count;
873 	uint32_t dc_edp_id_count;
874 	uint64_t fbc_gpu_addr;
875 	struct dc_dmub_srv *dmub_srv;
876 #ifdef CONFIG_DRM_AMD_DC_HDCP
877 	struct cp_psp cp_psp;
878 #endif
879 	uint32_t *dcn_reg_offsets;
880 	uint32_t *nbio_reg_offsets;
881 };
882 
883 /* DSC DPCD capabilities */
884 union dsc_slice_caps1 {
885 	struct {
886 		uint8_t NUM_SLICES_1 : 1;
887 		uint8_t NUM_SLICES_2 : 1;
888 		uint8_t RESERVED : 1;
889 		uint8_t NUM_SLICES_4 : 1;
890 		uint8_t NUM_SLICES_6 : 1;
891 		uint8_t NUM_SLICES_8 : 1;
892 		uint8_t NUM_SLICES_10 : 1;
893 		uint8_t NUM_SLICES_12 : 1;
894 	} bits;
895 	uint8_t raw;
896 };
897 
898 union dsc_slice_caps2 {
899 	struct {
900 		uint8_t NUM_SLICES_16 : 1;
901 		uint8_t NUM_SLICES_20 : 1;
902 		uint8_t NUM_SLICES_24 : 1;
903 		uint8_t RESERVED : 5;
904 	} bits;
905 	uint8_t raw;
906 };
907 
908 union dsc_color_formats {
909 	struct {
910 		uint8_t RGB : 1;
911 		uint8_t YCBCR_444 : 1;
912 		uint8_t YCBCR_SIMPLE_422 : 1;
913 		uint8_t YCBCR_NATIVE_422 : 1;
914 		uint8_t YCBCR_NATIVE_420 : 1;
915 		uint8_t RESERVED : 3;
916 	} bits;
917 	uint8_t raw;
918 };
919 
920 union dsc_color_depth {
921 	struct {
922 		uint8_t RESERVED1 : 1;
923 		uint8_t COLOR_DEPTH_8_BPC : 1;
924 		uint8_t COLOR_DEPTH_10_BPC : 1;
925 		uint8_t COLOR_DEPTH_12_BPC : 1;
926 		uint8_t RESERVED2 : 3;
927 	} bits;
928 	uint8_t raw;
929 };
930 
931 struct dsc_dec_dpcd_caps {
932 	bool is_dsc_supported;
933 	uint8_t dsc_version;
934 	int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
935 	union dsc_slice_caps1 slice_caps1;
936 	union dsc_slice_caps2 slice_caps2;
937 	int32_t lb_bit_depth;
938 	bool is_block_pred_supported;
939 	int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
940 	union dsc_color_formats color_formats;
941 	union dsc_color_depth color_depth;
942 	int32_t throughput_mode_0_mps; /* In MPs */
943 	int32_t throughput_mode_1_mps; /* In MPs */
944 	int32_t max_slice_width;
945 	uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
946 
947 	/* Extended DSC caps */
948 	uint32_t branch_overall_throughput_0_mps; /* In MPs */
949 	uint32_t branch_overall_throughput_1_mps; /* In MPs */
950 	uint32_t branch_max_line_width;
951 	bool is_dp;
952 };
953 
954 struct dc_golden_table {
955 	uint16_t dc_golden_table_ver;
956 	uint32_t aux_dphy_rx_control0_val;
957 	uint32_t aux_dphy_tx_control_val;
958 	uint32_t aux_dphy_rx_control1_val;
959 	uint32_t dc_gpio_aux_ctrl_0_val;
960 	uint32_t dc_gpio_aux_ctrl_1_val;
961 	uint32_t dc_gpio_aux_ctrl_2_val;
962 	uint32_t dc_gpio_aux_ctrl_3_val;
963 	uint32_t dc_gpio_aux_ctrl_4_val;
964 	uint32_t dc_gpio_aux_ctrl_5_val;
965 };
966 
967 enum dc_gpu_mem_alloc_type {
968 	DC_MEM_ALLOC_TYPE_GART,
969 	DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
970 	DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
971 	DC_MEM_ALLOC_TYPE_AGP
972 };
973 
974 enum dc_psr_version {
975 	DC_PSR_VERSION_1			= 0,
976 	DC_PSR_VERSION_SU_1			= 1,
977 	DC_PSR_VERSION_UNSUPPORTED		= 0xFFFFFFFF,
978 };
979 
980 /* Possible values of display_endpoint_id.endpoint */
981 enum display_endpoint_type {
982 	DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */
983 	DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */
984 	DISPLAY_ENDPOINT_UNKNOWN = -1
985 };
986 
987 /* Extends graphics_object_id with an additional member 'ep_type' for
988  * distinguishing between physical endpoints (with entries in BIOS connector table) and
989  * logical endpoints.
990  */
991 struct display_endpoint_id {
992 	struct graphics_object_id link_id;
993 	enum display_endpoint_type ep_type;
994 };
995 
996 #endif /* DC_TYPES_H_ */
997